1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2013-2019 NVIDIA Corporation. 4 * Copyright (C) 2015 Rob Clark 5 */ 6 7 #ifndef DRM_TEGRA_DP_H 8 #define DRM_TEGRA_DP_H 1 9 10 struct drm_dp_aux; 11 12 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 13 14 /** 15 * struct drm_dp_link - DP link capabilities and configuration 16 * @revision: DP specification revision supported on the link 17 * @max_rate: maximum clock rate supported on the link 18 * @max_lanes: maximum number of lanes supported on the link 19 * @capabilities: bitmask of capabilities supported on the link 20 * @rate: currently configured link rate 21 * @lanes: currently configured number of lanes 22 */ 23 struct drm_dp_link { 24 unsigned char revision; 25 unsigned int max_rate; 26 unsigned int max_lanes; 27 unsigned long capabilities; 28 29 unsigned int rate; 30 unsigned int lanes; 31 }; 32 33 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 34 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 35 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 36 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 37 38 #endif 39