1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2013-2019 NVIDIA Corporation. 4 * Copyright (C) 2015 Rob Clark 5 */ 6 7 #ifndef DRM_TEGRA_DP_H 8 #define DRM_TEGRA_DP_H 1 9 10 #include <linux/types.h> 11 12 struct drm_display_info; 13 struct drm_display_mode; 14 struct drm_dp_aux; 15 16 /** 17 * struct drm_dp_link_caps - DP link capabilities 18 */ 19 struct drm_dp_link_caps { 20 /** 21 * @enhanced_framing: 22 * 23 * enhanced framing capability (mandatory as of DP 1.2) 24 */ 25 bool enhanced_framing; 26 27 /** 28 * tps3_supported: 29 * 30 * training pattern sequence 3 supported for equalization 31 */ 32 bool tps3_supported; 33 34 /** 35 * @fast_training: 36 * 37 * AUX CH handshake not required for link training 38 */ 39 bool fast_training; 40 41 /** 42 * @channel_coding: 43 * 44 * ANSI 8B/10B channel coding capability 45 */ 46 bool channel_coding; 47 48 /** 49 * @alternate_scrambler_reset: 50 * 51 * eDP alternate scrambler reset capability 52 */ 53 bool alternate_scrambler_reset; 54 }; 55 56 void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, 57 const struct drm_dp_link_caps *src); 58 59 /** 60 * struct drm_dp_link - DP link capabilities and configuration 61 * @revision: DP specification revision supported on the link 62 * @max_rate: maximum clock rate supported on the link 63 * @max_lanes: maximum number of lanes supported on the link 64 * @caps: capabilities supported on the link (see &drm_dp_link_caps) 65 * @aux_rd_interval: AUX read interval to use for training (in microseconds) 66 * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) 67 * @rate: currently configured link rate 68 * @lanes: currently configured number of lanes 69 * @rates: additional supported link rates in kHz (eDP 1.4) 70 * @num_rates: number of additional supported link rates (eDP 1.4) 71 */ 72 struct drm_dp_link { 73 unsigned char revision; 74 unsigned int max_rate; 75 unsigned int max_lanes; 76 77 struct drm_dp_link_caps caps; 78 79 /** 80 * @cr: clock recovery read interval 81 * @ce: channel equalization read interval 82 */ 83 struct { 84 unsigned int cr; 85 unsigned int ce; 86 } aux_rd_interval; 87 88 unsigned char edp; 89 90 unsigned int rate; 91 unsigned int lanes; 92 93 unsigned long rates[DP_MAX_SUPPORTED_RATES]; 94 unsigned int num_rates; 95 }; 96 97 int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate); 98 int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate); 99 void drm_dp_link_update_rates(struct drm_dp_link *link); 100 101 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 102 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 103 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 104 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 105 int drm_dp_link_choose(struct drm_dp_link *link, 106 const struct drm_display_mode *mode, 107 const struct drm_display_info *info); 108 109 #endif 110