1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2013-2019 NVIDIA Corporation. 4 * Copyright (C) 2015 Rob Clark 5 */ 6 7 #ifndef DRM_TEGRA_DP_H 8 #define DRM_TEGRA_DP_H 1 9 10 struct drm_dp_aux; 11 12 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 13 14 /** 15 * struct drm_dp_link - DP link capabilities 16 * @revision: DP specification revision supported on the link 17 * @rate: maximum clock rate supported on the link 18 * @num_lanes: maximum number of lanes supported on the link 19 * @capabilities: bitmask of capabilities supported on the link 20 */ 21 struct drm_dp_link { 22 unsigned char revision; 23 unsigned int rate; 24 unsigned int num_lanes; 25 unsigned long capabilities; 26 }; 27 28 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 29 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 30 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 31 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 32 33 #endif 34