1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/clk/tegra.h> 16 17 #include "drm.h" 18 #include "dc.h" 19 20 struct tegra_dc_window { 21 fixed20_12 x; 22 fixed20_12 y; 23 fixed20_12 w; 24 fixed20_12 h; 25 unsigned int outx; 26 unsigned int outy; 27 unsigned int outw; 28 unsigned int outh; 29 unsigned int stride; 30 unsigned int fmt; 31 }; 32 33 static const struct drm_crtc_funcs tegra_crtc_funcs = { 34 .set_config = drm_crtc_helper_set_config, 35 .destroy = drm_crtc_cleanup, 36 }; 37 38 static void tegra_crtc_dpms(struct drm_crtc *crtc, int mode) 39 { 40 } 41 42 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, 43 const struct drm_display_mode *mode, 44 struct drm_display_mode *adjusted) 45 { 46 return true; 47 } 48 49 static inline u32 compute_dda_inc(fixed20_12 inf, unsigned int out, bool v, 50 unsigned int bpp) 51 { 52 fixed20_12 outf = dfixed_init(out); 53 u32 dda_inc; 54 int max; 55 56 if (v) 57 max = 15; 58 else { 59 switch (bpp) { 60 case 2: 61 max = 8; 62 break; 63 64 default: 65 WARN_ON_ONCE(1); 66 /* fallthrough */ 67 case 4: 68 max = 4; 69 break; 70 } 71 } 72 73 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 74 inf.full -= dfixed_const(1); 75 76 dda_inc = dfixed_div(inf, outf); 77 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 78 79 return dda_inc; 80 } 81 82 static inline u32 compute_initial_dda(fixed20_12 in) 83 { 84 return dfixed_frac(in); 85 } 86 87 static int tegra_dc_set_timings(struct tegra_dc *dc, 88 struct drm_display_mode *mode) 89 { 90 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */ 91 unsigned int h_ref_to_sync = 0; 92 unsigned int v_ref_to_sync = 0; 93 unsigned long value; 94 95 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 96 97 value = (v_ref_to_sync << 16) | h_ref_to_sync; 98 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 99 100 value = ((mode->vsync_end - mode->vsync_start) << 16) | 101 ((mode->hsync_end - mode->hsync_start) << 0); 102 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 103 104 value = ((mode->vtotal - mode->vsync_end) << 16) | 105 ((mode->htotal - mode->hsync_end) << 0); 106 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 107 108 value = ((mode->vsync_start - mode->vdisplay) << 16) | 109 ((mode->hsync_start - mode->hdisplay) << 0); 110 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 111 112 value = (mode->vdisplay << 16) | mode->hdisplay; 113 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 114 115 return 0; 116 } 117 118 static int tegra_crtc_setup_clk(struct drm_crtc *crtc, 119 struct drm_display_mode *mode, 120 unsigned long *div) 121 { 122 unsigned long pclk = mode->clock * 1000, rate; 123 struct tegra_dc *dc = to_tegra_dc(crtc); 124 struct tegra_output *output = NULL; 125 struct drm_encoder *encoder; 126 long err; 127 128 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) 129 if (encoder->crtc == crtc) { 130 output = encoder_to_output(encoder); 131 break; 132 } 133 134 if (!output) 135 return -ENODEV; 136 137 /* 138 * This assumes that the display controller will divide its parent 139 * clock by 2 to generate the pixel clock. 140 */ 141 err = tegra_output_setup_clock(output, dc->clk, pclk * 2); 142 if (err < 0) { 143 dev_err(dc->dev, "failed to setup clock: %ld\n", err); 144 return err; 145 } 146 147 rate = clk_get_rate(dc->clk); 148 *div = (rate * 2 / pclk) - 2; 149 150 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div); 151 152 return 0; 153 } 154 155 static int tegra_crtc_mode_set(struct drm_crtc *crtc, 156 struct drm_display_mode *mode, 157 struct drm_display_mode *adjusted, 158 int x, int y, struct drm_framebuffer *old_fb) 159 { 160 struct tegra_framebuffer *fb = to_tegra_fb(crtc->fb); 161 struct tegra_dc *dc = to_tegra_dc(crtc); 162 unsigned int h_dda, v_dda, bpp; 163 struct tegra_dc_window win; 164 unsigned long div, value; 165 int err; 166 167 err = tegra_crtc_setup_clk(crtc, mode, &div); 168 if (err) { 169 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); 170 return err; 171 } 172 173 /* program display mode */ 174 tegra_dc_set_timings(dc, mode); 175 176 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 177 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 178 179 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 180 value &= ~LVS_OUTPUT_POLARITY_LOW; 181 value &= ~LHS_OUTPUT_POLARITY_LOW; 182 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 183 184 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 185 DISP_ORDER_RED_BLUE; 186 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 187 188 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS); 189 190 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; 191 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 192 193 /* setup window parameters */ 194 memset(&win, 0, sizeof(win)); 195 win.x.full = dfixed_const(0); 196 win.y.full = dfixed_const(0); 197 win.w.full = dfixed_const(mode->hdisplay); 198 win.h.full = dfixed_const(mode->vdisplay); 199 win.outx = 0; 200 win.outy = 0; 201 win.outw = mode->hdisplay; 202 win.outh = mode->vdisplay; 203 204 switch (crtc->fb->pixel_format) { 205 case DRM_FORMAT_XRGB8888: 206 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8; 207 break; 208 209 case DRM_FORMAT_RGB565: 210 win.fmt = WIN_COLOR_DEPTH_B5G6R5; 211 break; 212 213 default: 214 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8; 215 WARN_ON(1); 216 break; 217 } 218 219 bpp = crtc->fb->bits_per_pixel / 8; 220 win.stride = crtc->fb->pitches[0]; 221 222 /* program window registers */ 223 value = WINDOW_A_SELECT; 224 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); 225 226 tegra_dc_writel(dc, win.fmt, DC_WIN_COLOR_DEPTH); 227 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP); 228 229 value = V_POSITION(win.outy) | H_POSITION(win.outx); 230 tegra_dc_writel(dc, value, DC_WIN_POSITION); 231 232 value = V_SIZE(win.outh) | H_SIZE(win.outw); 233 tegra_dc_writel(dc, value, DC_WIN_SIZE); 234 235 value = V_PRESCALED_SIZE(dfixed_trunc(win.h)) | 236 H_PRESCALED_SIZE(dfixed_trunc(win.w) * bpp); 237 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); 238 239 h_dda = compute_dda_inc(win.w, win.outw, false, bpp); 240 v_dda = compute_dda_inc(win.h, win.outh, true, bpp); 241 242 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 243 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); 244 245 h_dda = compute_initial_dda(win.x); 246 v_dda = compute_initial_dda(win.y); 247 248 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); 249 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); 250 251 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); 252 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); 253 254 tegra_dc_writel(dc, fb->obj->paddr, DC_WINBUF_START_ADDR); 255 tegra_dc_writel(dc, win.stride, DC_WIN_LINE_STRIDE); 256 tegra_dc_writel(dc, dfixed_trunc(win.x) * bpp, 257 DC_WINBUF_ADDR_H_OFFSET); 258 tegra_dc_writel(dc, dfixed_trunc(win.y), DC_WINBUF_ADDR_V_OFFSET); 259 260 value = WIN_ENABLE; 261 262 if (bpp < 24) 263 value |= COLOR_EXPAND; 264 265 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 266 267 tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY); 268 tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN); 269 270 return 0; 271 } 272 273 static void tegra_crtc_prepare(struct drm_crtc *crtc) 274 { 275 struct tegra_dc *dc = to_tegra_dc(crtc); 276 unsigned int syncpt; 277 unsigned long value; 278 279 /* hardware initialization */ 280 tegra_periph_reset_deassert(dc->clk); 281 usleep_range(10000, 20000); 282 283 if (dc->pipe) 284 syncpt = SYNCPT_VBLANK1; 285 else 286 syncpt = SYNCPT_VBLANK0; 287 288 /* initialize display controller */ 289 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 290 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 291 292 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 293 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 294 295 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 296 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 297 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 298 299 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 300 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 301 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 302 303 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 304 value |= DISP_CTRL_MODE_C_DISPLAY; 305 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 306 307 /* initialize timer */ 308 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 309 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 310 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 311 312 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 313 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 314 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 315 316 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 317 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 318 319 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 320 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 321 } 322 323 static void tegra_crtc_commit(struct drm_crtc *crtc) 324 { 325 struct tegra_dc *dc = to_tegra_dc(crtc); 326 unsigned long update_mask; 327 unsigned long value; 328 329 update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 330 331 tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL); 332 333 value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE); 334 value |= FRAME_END_INT; 335 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 336 337 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 338 value |= FRAME_END_INT; 339 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 340 341 tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL); 342 } 343 344 static void tegra_crtc_load_lut(struct drm_crtc *crtc) 345 { 346 } 347 348 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 349 .dpms = tegra_crtc_dpms, 350 .mode_fixup = tegra_crtc_mode_fixup, 351 .mode_set = tegra_crtc_mode_set, 352 .prepare = tegra_crtc_prepare, 353 .commit = tegra_crtc_commit, 354 .load_lut = tegra_crtc_load_lut, 355 }; 356 357 static irqreturn_t tegra_drm_irq(int irq, void *data) 358 { 359 struct tegra_dc *dc = data; 360 unsigned long status; 361 362 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 363 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 364 365 if (status & FRAME_END_INT) { 366 /* 367 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 368 */ 369 } 370 371 if (status & VBLANK_INT) { 372 /* 373 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 374 */ 375 drm_handle_vblank(dc->base.dev, dc->pipe); 376 } 377 378 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 379 /* 380 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 381 */ 382 } 383 384 return IRQ_HANDLED; 385 } 386 387 static int tegra_dc_show_regs(struct seq_file *s, void *data) 388 { 389 struct drm_info_node *node = s->private; 390 struct tegra_dc *dc = node->info_ent->data; 391 392 #define DUMP_REG(name) \ 393 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \ 394 tegra_dc_readl(dc, name)) 395 396 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); 397 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 398 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); 399 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); 400 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); 401 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); 402 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); 403 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); 404 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); 405 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); 406 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); 407 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); 408 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); 409 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); 410 DUMP_REG(DC_CMD_DISPLAY_COMMAND); 411 DUMP_REG(DC_CMD_SIGNAL_RAISE); 412 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); 413 DUMP_REG(DC_CMD_INT_STATUS); 414 DUMP_REG(DC_CMD_INT_MASK); 415 DUMP_REG(DC_CMD_INT_ENABLE); 416 DUMP_REG(DC_CMD_INT_TYPE); 417 DUMP_REG(DC_CMD_INT_POLARITY); 418 DUMP_REG(DC_CMD_SIGNAL_RAISE1); 419 DUMP_REG(DC_CMD_SIGNAL_RAISE2); 420 DUMP_REG(DC_CMD_SIGNAL_RAISE3); 421 DUMP_REG(DC_CMD_STATE_ACCESS); 422 DUMP_REG(DC_CMD_STATE_CONTROL); 423 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); 424 DUMP_REG(DC_CMD_REG_ACT_CONTROL); 425 DUMP_REG(DC_COM_CRC_CONTROL); 426 DUMP_REG(DC_COM_CRC_CHECKSUM); 427 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); 428 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); 429 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); 430 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); 431 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); 432 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); 433 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); 434 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); 435 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); 436 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); 437 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); 438 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); 439 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); 440 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); 441 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); 442 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); 443 DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); 444 DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); 445 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); 446 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); 447 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); 448 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); 449 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); 450 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); 451 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); 452 DUMP_REG(DC_COM_PIN_MISC_CONTROL); 453 DUMP_REG(DC_COM_PIN_PM0_CONTROL); 454 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); 455 DUMP_REG(DC_COM_PIN_PM1_CONTROL); 456 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); 457 DUMP_REG(DC_COM_SPI_CONTROL); 458 DUMP_REG(DC_COM_SPI_START_BYTE); 459 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); 460 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); 461 DUMP_REG(DC_COM_HSPI_CS_DC); 462 DUMP_REG(DC_COM_SCRATCH_REGISTER_A); 463 DUMP_REG(DC_COM_SCRATCH_REGISTER_B); 464 DUMP_REG(DC_COM_GPIO_CTRL); 465 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); 466 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); 467 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); 468 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); 469 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); 470 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); 471 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 472 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); 473 DUMP_REG(DC_DISP_REF_TO_SYNC); 474 DUMP_REG(DC_DISP_SYNC_WIDTH); 475 DUMP_REG(DC_DISP_BACK_PORCH); 476 DUMP_REG(DC_DISP_ACTIVE); 477 DUMP_REG(DC_DISP_FRONT_PORCH); 478 DUMP_REG(DC_DISP_H_PULSE0_CONTROL); 479 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); 480 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); 481 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); 482 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); 483 DUMP_REG(DC_DISP_H_PULSE1_CONTROL); 484 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); 485 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); 486 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); 487 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); 488 DUMP_REG(DC_DISP_H_PULSE2_CONTROL); 489 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); 490 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); 491 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); 492 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); 493 DUMP_REG(DC_DISP_V_PULSE0_CONTROL); 494 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); 495 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); 496 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); 497 DUMP_REG(DC_DISP_V_PULSE1_CONTROL); 498 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); 499 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); 500 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); 501 DUMP_REG(DC_DISP_V_PULSE2_CONTROL); 502 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); 503 DUMP_REG(DC_DISP_V_PULSE3_CONTROL); 504 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); 505 DUMP_REG(DC_DISP_M0_CONTROL); 506 DUMP_REG(DC_DISP_M1_CONTROL); 507 DUMP_REG(DC_DISP_DI_CONTROL); 508 DUMP_REG(DC_DISP_PP_CONTROL); 509 DUMP_REG(DC_DISP_PP_SELECT_A); 510 DUMP_REG(DC_DISP_PP_SELECT_B); 511 DUMP_REG(DC_DISP_PP_SELECT_C); 512 DUMP_REG(DC_DISP_PP_SELECT_D); 513 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); 514 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); 515 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); 516 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); 517 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); 518 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); 519 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); 520 DUMP_REG(DC_DISP_BORDER_COLOR); 521 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); 522 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); 523 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); 524 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); 525 DUMP_REG(DC_DISP_CURSOR_FOREGROUND); 526 DUMP_REG(DC_DISP_CURSOR_BACKGROUND); 527 DUMP_REG(DC_DISP_CURSOR_START_ADDR); 528 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); 529 DUMP_REG(DC_DISP_CURSOR_POSITION); 530 DUMP_REG(DC_DISP_CURSOR_POSITION_NS); 531 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); 532 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); 533 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); 534 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); 535 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); 536 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); 537 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); 538 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); 539 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); 540 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); 541 DUMP_REG(DC_DISP_DAC_CRT_CTRL); 542 DUMP_REG(DC_DISP_DISP_MISC_CONTROL); 543 DUMP_REG(DC_DISP_SD_CONTROL); 544 DUMP_REG(DC_DISP_SD_CSC_COEFF); 545 DUMP_REG(DC_DISP_SD_LUT(0)); 546 DUMP_REG(DC_DISP_SD_LUT(1)); 547 DUMP_REG(DC_DISP_SD_LUT(2)); 548 DUMP_REG(DC_DISP_SD_LUT(3)); 549 DUMP_REG(DC_DISP_SD_LUT(4)); 550 DUMP_REG(DC_DISP_SD_LUT(5)); 551 DUMP_REG(DC_DISP_SD_LUT(6)); 552 DUMP_REG(DC_DISP_SD_LUT(7)); 553 DUMP_REG(DC_DISP_SD_LUT(8)); 554 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); 555 DUMP_REG(DC_DISP_DC_PIXEL_COUNT); 556 DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); 557 DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); 558 DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); 559 DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); 560 DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); 561 DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); 562 DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); 563 DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); 564 DUMP_REG(DC_DISP_SD_BL_TF(0)); 565 DUMP_REG(DC_DISP_SD_BL_TF(1)); 566 DUMP_REG(DC_DISP_SD_BL_TF(2)); 567 DUMP_REG(DC_DISP_SD_BL_TF(3)); 568 DUMP_REG(DC_DISP_SD_BL_CONTROL); 569 DUMP_REG(DC_DISP_SD_HW_K_VALUES); 570 DUMP_REG(DC_DISP_SD_MAN_K_VALUES); 571 DUMP_REG(DC_WIN_WIN_OPTIONS); 572 DUMP_REG(DC_WIN_BYTE_SWAP); 573 DUMP_REG(DC_WIN_BUFFER_CONTROL); 574 DUMP_REG(DC_WIN_COLOR_DEPTH); 575 DUMP_REG(DC_WIN_POSITION); 576 DUMP_REG(DC_WIN_SIZE); 577 DUMP_REG(DC_WIN_PRESCALED_SIZE); 578 DUMP_REG(DC_WIN_H_INITIAL_DDA); 579 DUMP_REG(DC_WIN_V_INITIAL_DDA); 580 DUMP_REG(DC_WIN_DDA_INC); 581 DUMP_REG(DC_WIN_LINE_STRIDE); 582 DUMP_REG(DC_WIN_BUF_STRIDE); 583 DUMP_REG(DC_WIN_UV_BUF_STRIDE); 584 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); 585 DUMP_REG(DC_WIN_DV_CONTROL); 586 DUMP_REG(DC_WIN_BLEND_NOKEY); 587 DUMP_REG(DC_WIN_BLEND_1WIN); 588 DUMP_REG(DC_WIN_BLEND_2WIN_X); 589 DUMP_REG(DC_WIN_BLEND_2WIN_Y); 590 DUMP_REG(DC_WIN_BLEND32WIN_XY); 591 DUMP_REG(DC_WIN_HP_FETCH_CONTROL); 592 DUMP_REG(DC_WINBUF_START_ADDR); 593 DUMP_REG(DC_WINBUF_START_ADDR_NS); 594 DUMP_REG(DC_WINBUF_START_ADDR_U); 595 DUMP_REG(DC_WINBUF_START_ADDR_U_NS); 596 DUMP_REG(DC_WINBUF_START_ADDR_V); 597 DUMP_REG(DC_WINBUF_START_ADDR_V_NS); 598 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); 599 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); 600 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); 601 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); 602 DUMP_REG(DC_WINBUF_UFLOW_STATUS); 603 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); 604 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); 605 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); 606 607 #undef DUMP_REG 608 609 return 0; 610 } 611 612 static struct drm_info_list debugfs_files[] = { 613 { "regs", tegra_dc_show_regs, 0, NULL }, 614 }; 615 616 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) 617 { 618 unsigned int i; 619 char *name; 620 int err; 621 622 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); 623 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); 624 kfree(name); 625 626 if (!dc->debugfs) 627 return -ENOMEM; 628 629 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 630 GFP_KERNEL); 631 if (!dc->debugfs_files) { 632 err = -ENOMEM; 633 goto remove; 634 } 635 636 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 637 dc->debugfs_files[i].data = dc; 638 639 err = drm_debugfs_create_files(dc->debugfs_files, 640 ARRAY_SIZE(debugfs_files), 641 dc->debugfs, minor); 642 if (err < 0) 643 goto free; 644 645 dc->minor = minor; 646 647 return 0; 648 649 free: 650 kfree(dc->debugfs_files); 651 dc->debugfs_files = NULL; 652 remove: 653 debugfs_remove(dc->debugfs); 654 dc->debugfs = NULL; 655 656 return err; 657 } 658 659 static int tegra_dc_debugfs_exit(struct tegra_dc *dc) 660 { 661 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), 662 dc->minor); 663 dc->minor = NULL; 664 665 kfree(dc->debugfs_files); 666 dc->debugfs_files = NULL; 667 668 debugfs_remove(dc->debugfs); 669 dc->debugfs = NULL; 670 671 return 0; 672 } 673 674 static int tegra_dc_drm_init(struct host1x_client *client, 675 struct drm_device *drm) 676 { 677 struct tegra_dc *dc = host1x_client_to_dc(client); 678 int err; 679 680 dc->pipe = drm->mode_config.num_crtc; 681 682 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs); 683 drm_mode_crtc_set_gamma_size(&dc->base, 256); 684 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 685 686 err = tegra_dc_rgb_init(drm, dc); 687 if (err < 0 && err != -ENODEV) { 688 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 689 return err; 690 } 691 692 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 693 err = tegra_dc_debugfs_init(dc, drm->primary); 694 if (err < 0) 695 dev_err(dc->dev, "debugfs setup failed: %d\n", err); 696 } 697 698 err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0, 699 dev_name(dc->dev), dc); 700 if (err < 0) { 701 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 702 err); 703 return err; 704 } 705 706 return 0; 707 } 708 709 static int tegra_dc_drm_exit(struct host1x_client *client) 710 { 711 struct tegra_dc *dc = host1x_client_to_dc(client); 712 int err; 713 714 devm_free_irq(dc->dev, dc->irq, dc); 715 716 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 717 err = tegra_dc_debugfs_exit(dc); 718 if (err < 0) 719 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); 720 } 721 722 err = tegra_dc_rgb_exit(dc); 723 if (err) { 724 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 725 return err; 726 } 727 728 return 0; 729 } 730 731 static const struct host1x_client_ops dc_client_ops = { 732 .drm_init = tegra_dc_drm_init, 733 .drm_exit = tegra_dc_drm_exit, 734 }; 735 736 static int tegra_dc_probe(struct platform_device *pdev) 737 { 738 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent); 739 struct resource *regs; 740 struct tegra_dc *dc; 741 int err; 742 743 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 744 if (!dc) 745 return -ENOMEM; 746 747 INIT_LIST_HEAD(&dc->list); 748 dc->dev = &pdev->dev; 749 750 dc->clk = devm_clk_get(&pdev->dev, NULL); 751 if (IS_ERR(dc->clk)) { 752 dev_err(&pdev->dev, "failed to get clock\n"); 753 return PTR_ERR(dc->clk); 754 } 755 756 err = clk_prepare_enable(dc->clk); 757 if (err < 0) 758 return err; 759 760 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 761 if (!regs) { 762 dev_err(&pdev->dev, "failed to get registers\n"); 763 return -ENXIO; 764 } 765 766 dc->regs = devm_ioremap_resource(&pdev->dev, regs); 767 if (IS_ERR(dc->regs)) 768 return PTR_ERR(dc->regs); 769 770 dc->irq = platform_get_irq(pdev, 0); 771 if (dc->irq < 0) { 772 dev_err(&pdev->dev, "failed to get IRQ\n"); 773 return -ENXIO; 774 } 775 776 INIT_LIST_HEAD(&dc->client.list); 777 dc->client.ops = &dc_client_ops; 778 dc->client.dev = &pdev->dev; 779 780 err = tegra_dc_rgb_probe(dc); 781 if (err < 0 && err != -ENODEV) { 782 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); 783 return err; 784 } 785 786 err = host1x_register_client(host1x, &dc->client); 787 if (err < 0) { 788 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 789 err); 790 return err; 791 } 792 793 platform_set_drvdata(pdev, dc); 794 795 return 0; 796 } 797 798 static int tegra_dc_remove(struct platform_device *pdev) 799 { 800 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent); 801 struct tegra_dc *dc = platform_get_drvdata(pdev); 802 int err; 803 804 err = host1x_unregister_client(host1x, &dc->client); 805 if (err < 0) { 806 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 807 err); 808 return err; 809 } 810 811 clk_disable_unprepare(dc->clk); 812 813 return 0; 814 } 815 816 static struct of_device_id tegra_dc_of_match[] = { 817 { .compatible = "nvidia,tegra30-dc", }, 818 { .compatible = "nvidia,tegra20-dc", }, 819 { }, 820 }; 821 822 struct platform_driver tegra_dc_driver = { 823 .driver = { 824 .name = "tegra-dc", 825 .owner = THIS_MODULE, 826 .of_match_table = tegra_dc_of_match, 827 }, 828 .probe = tegra_dc_probe, 829 .remove = tegra_dc_remove, 830 }; 831