1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/iommu.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_domain.h> 17 #include <linux/pm_opp.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 21 #include <soc/tegra/common.h> 22 #include <soc/tegra/pmc.h> 23 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_blend.h> 27 #include <drm/drm_debugfs.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_vblank.h> 32 33 #include "dc.h" 34 #include "drm.h" 35 #include "gem.h" 36 #include "hub.h" 37 #include "plane.h" 38 39 static const u16 default_srgb_lut[] = { 40 0x6000, 0x60CE, 0x619D, 0x626C, 0x632D, 0x63D4, 0x6469, 0x64F0, 0x656B, 0x65DF, 0x664A, 41 0x66B0, 0x6711, 0x676D, 0x67C4, 0x6819, 0x686A, 0x68B8, 0x6904, 0x694D, 0x6994, 0x69D8, 42 0x6A1B, 0x6A5D, 0x6A9C, 0x6ADA, 0x6B17, 0x6B52, 0x6B8C, 0x6BC5, 0x6BFD, 0x6C33, 0x6C69, 43 0x6C9E, 0x6CD1, 0x6D04, 0x6D36, 0x6D67, 0x6D98, 0x6DC7, 0x6DF6, 0x6E25, 0x6E52, 0x6E7F, 44 0x6EAC, 0x6ED7, 0x6F03, 0x6F2D, 0x6F58, 0x6F81, 0x6FAA, 0x6FD3, 0x6FFB, 0x7023, 0x704B, 45 0x7071, 0x7098, 0x70BE, 0x70E4, 0x7109, 0x712E, 0x7153, 0x7177, 0x719B, 0x71BF, 0x71E2, 46 0x7205, 0x7227, 0x724A, 0x726C, 0x728E, 0x72AF, 0x72D0, 0x72F1, 0x7312, 0x7333, 0x7353, 47 0x7373, 0x7392, 0x73B2, 0x73D1, 0x73F0, 0x740F, 0x742D, 0x744C, 0x746A, 0x7488, 0x74A6, 48 0x74C3, 0x74E0, 0x74FE, 0x751B, 0x7537, 0x7554, 0x7570, 0x758D, 0x75A9, 0x75C4, 0x75E0, 49 0x75FC, 0x7617, 0x7632, 0x764D, 0x7668, 0x7683, 0x769E, 0x76B8, 0x76D3, 0x76ED, 0x7707, 50 0x7721, 0x773B, 0x7754, 0x776E, 0x7787, 0x77A0, 0x77B9, 0x77D2, 0x77EB, 0x7804, 0x781D, 51 0x7835, 0x784E, 0x7866, 0x787E, 0x7896, 0x78AE, 0x78C6, 0x78DD, 0x78F5, 0x790D, 0x7924, 52 0x793B, 0x7952, 0x796A, 0x7981, 0x7997, 0x79AE, 0x79C5, 0x79DB, 0x79F2, 0x7A08, 0x7A1F, 53 0x7A35, 0x7A4B, 0x7A61, 0x7A77, 0x7A8D, 0x7AA3, 0x7AB8, 0x7ACE, 0x7AE3, 0x7AF9, 0x7B0E, 54 0x7B24, 0x7B39, 0x7B4E, 0x7B63, 0x7B78, 0x7B8D, 0x7BA2, 0x7BB6, 0x7BCB, 0x7BE0, 0x7BF4, 55 0x7C08, 0x7C1D, 0x7C31, 0x7C45, 0x7C59, 0x7C6E, 0x7C82, 0x7C96, 0x7CA9, 0x7CBD, 0x7CD1, 56 0x7CE5, 0x7CF8, 0x7D0C, 0x7D1F, 0x7D33, 0x7D46, 0x7D59, 0x7D6D, 0x7D80, 0x7D93, 0x7DA6, 57 0x7DB9, 0x7DCC, 0x7DDF, 0x7DF2, 0x7E04, 0x7E17, 0x7E2A, 0x7E3C, 0x7E4F, 0x7E61, 0x7E74, 58 0x7E86, 0x7E98, 0x7EAB, 0x7EBD, 0x7ECF, 0x7EE1, 0x7EF3, 0x7F05, 0x7F17, 0x7F29, 0x7F3B, 59 0x7F4D, 0x7F5E, 0x7F70, 0x7F82, 0x7F93, 0x7FA5, 0x7FB6, 0x7FC8, 0x7FD9, 0x7FEB, 0x7FFC, 60 0x800D, 0x801E, 0x8030, 0x8041, 0x8052, 0x8063, 0x8074, 0x8085, 0x8096, 0x80A7, 0x80B7, 61 0x80C8, 0x80D9, 0x80EA, 0x80FA, 0x810B, 0x811C, 0x812C, 0x813D, 0x814D, 0x815D, 0x816E, 62 0x817E, 0x818E, 0x819F, 0x81AF, 0x81BF, 0x81CF, 0x81DF, 0x81EF, 0x81FF, 0x820F, 0x821F, 63 0x822F, 0x823F, 0x824F, 0x825F, 0x826F, 0x827E, 0x828E, 0x829E, 0x82AD, 0x82BD, 0x82CC, 64 0x82DC, 0x82EB, 0x82FB, 0x830A, 0x831A, 0x8329, 0x8338, 0x8348, 0x8357, 0x8366, 0x8375, 65 0x8385, 0x8394, 0x83A3, 0x83B2, 0x83C1, 0x83D0, 0x83DF, 0x83EE, 0x83FD, 0x840C, 0x841A, 66 0x8429, 0x8438, 0x8447, 0x8455, 0x8464, 0x8473, 0x8481, 0x8490, 0x849F, 0x84AD, 0x84BC, 67 0x84CA, 0x84D9, 0x84E7, 0x84F5, 0x8504, 0x8512, 0x8521, 0x852F, 0x853D, 0x854B, 0x855A, 68 0x8568, 0x8576, 0x8584, 0x8592, 0x85A0, 0x85AE, 0x85BC, 0x85CA, 0x85D8, 0x85E6, 0x85F4, 69 0x8602, 0x8610, 0x861E, 0x862C, 0x8639, 0x8647, 0x8655, 0x8663, 0x8670, 0x867E, 0x868C, 70 0x8699, 0x86A7, 0x86B5, 0x86C2, 0x86D0, 0x86DD, 0x86EB, 0x86F8, 0x8705, 0x8713, 0x8720, 71 0x872E, 0x873B, 0x8748, 0x8756, 0x8763, 0x8770, 0x877D, 0x878B, 0x8798, 0x87A5, 0x87B2, 72 0x87BF, 0x87CC, 0x87D9, 0x87E6, 0x87F3, 0x8801, 0x880E, 0x881A, 0x8827, 0x8834, 0x8841, 73 0x884E, 0x885B, 0x8868, 0x8875, 0x8882, 0x888E, 0x889B, 0x88A8, 0x88B5, 0x88C1, 0x88CE, 74 0x88DB, 0x88E7, 0x88F4, 0x8900, 0x890D, 0x891A, 0x8926, 0x8933, 0x893F, 0x894C, 0x8958, 75 0x8965, 0x8971, 0x897D, 0x898A, 0x8996, 0x89A3, 0x89AF, 0x89BB, 0x89C8, 0x89D4, 0x89E0, 76 0x89EC, 0x89F9, 0x8A05, 0x8A11, 0x8A1D, 0x8A29, 0x8A36, 0x8A42, 0x8A4E, 0x8A5A, 0x8A66, 77 0x8A72, 0x8A7E, 0x8A8A, 0x8A96, 0x8AA2, 0x8AAE, 0x8ABA, 0x8AC6, 0x8AD2, 0x8ADE, 0x8AEA, 78 0x8AF5, 0x8B01, 0x8B0D, 0x8B19, 0x8B25, 0x8B31, 0x8B3C, 0x8B48, 0x8B54, 0x8B60, 0x8B6B, 79 0x8B77, 0x8B83, 0x8B8E, 0x8B9A, 0x8BA6, 0x8BB1, 0x8BBD, 0x8BC8, 0x8BD4, 0x8BDF, 0x8BEB, 80 0x8BF6, 0x8C02, 0x8C0D, 0x8C19, 0x8C24, 0x8C30, 0x8C3B, 0x8C47, 0x8C52, 0x8C5D, 0x8C69, 81 0x8C74, 0x8C80, 0x8C8B, 0x8C96, 0x8CA1, 0x8CAD, 0x8CB8, 0x8CC3, 0x8CCF, 0x8CDA, 0x8CE5, 82 0x8CF0, 0x8CFB, 0x8D06, 0x8D12, 0x8D1D, 0x8D28, 0x8D33, 0x8D3E, 0x8D49, 0x8D54, 0x8D5F, 83 0x8D6A, 0x8D75, 0x8D80, 0x8D8B, 0x8D96, 0x8DA1, 0x8DAC, 0x8DB7, 0x8DC2, 0x8DCD, 0x8DD8, 84 0x8DE3, 0x8DEE, 0x8DF9, 0x8E04, 0x8E0E, 0x8E19, 0x8E24, 0x8E2F, 0x8E3A, 0x8E44, 0x8E4F, 85 0x8E5A, 0x8E65, 0x8E6F, 0x8E7A, 0x8E85, 0x8E90, 0x8E9A, 0x8EA5, 0x8EB0, 0x8EBA, 0x8EC5, 86 0x8ECF, 0x8EDA, 0x8EE5, 0x8EEF, 0x8EFA, 0x8F04, 0x8F0F, 0x8F19, 0x8F24, 0x8F2E, 0x8F39, 87 0x8F43, 0x8F4E, 0x8F58, 0x8F63, 0x8F6D, 0x8F78, 0x8F82, 0x8F8C, 0x8F97, 0x8FA1, 0x8FAC, 88 0x8FB6, 0x8FC0, 0x8FCB, 0x8FD5, 0x8FDF, 0x8FEA, 0x8FF4, 0x8FFE, 0x9008, 0x9013, 0x901D, 89 0x9027, 0x9031, 0x903C, 0x9046, 0x9050, 0x905A, 0x9064, 0x906E, 0x9079, 0x9083, 0x908D, 90 0x9097, 0x90A1, 0x90AB, 0x90B5, 0x90BF, 0x90C9, 0x90D3, 0x90DD, 0x90E7, 0x90F1, 0x90FB, 91 0x9105, 0x910F, 0x9119, 0x9123, 0x912D, 0x9137, 0x9141, 0x914B, 0x9155, 0x915F, 0x9169, 92 0x9173, 0x917D, 0x9186, 0x9190, 0x919A, 0x91A4, 0x91AE, 0x91B8, 0x91C1, 0x91CB, 0x91D5, 93 0x91DF, 0x91E9, 0x91F2, 0x91FC, 0x9206, 0x9210, 0x9219, 0x9223, 0x922D, 0x9236, 0x9240, 94 0x924A, 0x9253, 0x925D, 0x9267, 0x9270, 0x927A, 0x9283, 0x928D, 0x9297, 0x92A0, 0x92AA, 95 0x92B3, 0x92BD, 0x92C6, 0x92D0, 0x92DA, 0x92E3, 0x92ED, 0x92F6, 0x9300, 0x9309, 0x9313, 96 0x931C, 0x9325, 0x932F, 0x9338, 0x9342, 0x934B, 0x9355, 0x935E, 0x9367, 0x9371, 0x937A, 97 0x9384, 0x938D, 0x9396, 0x93A0, 0x93A9, 0x93B2, 0x93BC, 0x93C5, 0x93CE, 0x93D7, 0x93E1, 98 0x93EA, 0x93F3, 0x93FC, 0x9406, 0x940F, 0x9418, 0x9421, 0x942B, 0x9434, 0x943D, 0x9446, 99 0x944F, 0x9459, 0x9462, 0x946B, 0x9474, 0x947D, 0x9486, 0x948F, 0x9499, 0x94A2, 0x94AB, 100 0x94B4, 0x94BD, 0x94C6, 0x94CF, 0x94D8, 0x94E1, 0x94EA, 0x94F3, 0x94FC, 0x9505, 0x950E, 101 0x9517, 0x9520, 0x9529, 0x9532, 0x953B, 0x9544, 0x954D, 0x9556, 0x955F, 0x9568, 0x9571, 102 0x957A, 0x9583, 0x958C, 0x9595, 0x959D, 0x95A6, 0x95AF, 0x95B8, 0x95C1, 0x95CA, 0x95D3, 103 0x95DB, 0x95E4, 0x95ED, 0x95F6, 0x95FF, 0x9608, 0x9610, 0x9619, 0x9622, 0x962B, 0x9633, 104 0x963C, 0x9645, 0x964E, 0x9656, 0x965F, 0x9668, 0x9671, 0x9679, 0x9682, 0x968B, 0x9693, 105 0x969C, 0x96A5, 0x96AD, 0x96B6, 0x96BF, 0x96C7, 0x96D0, 0x96D9, 0x96E1, 0x96EA, 0x96F2, 106 0x96FB, 0x9704, 0x970C, 0x9715, 0x971D, 0x9726, 0x972E, 0x9737, 0x9740, 0x9748, 0x9751, 107 0x9759, 0x9762, 0x976A, 0x9773, 0x977B, 0x9784, 0x978C, 0x9795, 0x979D, 0x97A6, 0x97AE, 108 0x97B6, 0x97BF, 0x97C7, 0x97D0, 0x97D8, 0x97E1, 0x97E9, 0x97F1, 0x97FA, 0x9802, 0x980B, 109 0x9813, 0x981B, 0x9824, 0x982C, 0x9834, 0x983D, 0x9845, 0x984D, 0x9856, 0x985E, 0x9866, 110 0x986F, 0x9877, 0x987F, 0x9888, 0x9890, 0x9898, 0x98A0, 0x98A9, 0x98B1, 0x98B9, 0x98C1, 111 0x98CA, 0x98D2, 0x98DA, 0x98E2, 0x98EB, 0x98F3, 0x98FB, 0x9903, 0x990B, 0x9914, 0x991C, 112 0x9924, 0x992C, 0x9934, 0x993C, 0x9945, 0x994D, 0x9955, 0x995D, 0x9965, 0x996D, 0x9975, 113 0x997D, 0x9986, 0x998E, 0x9996, 0x999E, 0x99A6, 0x99AE, 0x99B6, 0x99BE, 0x99C6, 0x99CE, 114 0x99D6, 0x99DE, 0x99E6, 0x99EE, 0x99F6, 0x99FE, 0x9A06, 0x9A0E, 0x9A16, 0x9A1E, 0x9A26, 115 0x9A2E, 0x9A36, 0x9A3E, 0x9A46, 0x9A4E, 0x9A56, 0x9A5E, 0x9A66, 0x9A6E, 0x9A76, 0x9A7E, 116 0x9A86, 0x9A8E, 0x9A96, 0x9A9D, 0x9AA5, 0x9AAD, 0x9AB5, 0x9ABD, 0x9AC5, 0x9ACD, 0x9AD5, 117 0x9ADC, 0x9AE4, 0x9AEC, 0x9AF4, 0x9AFC, 0x9B04, 0x9B0C, 0x9B13, 0x9B1B, 0x9B23, 0x9B2B, 118 0x9B33, 0x9B3A, 0x9B42, 0x9B4A, 0x9B52, 0x9B59, 0x9B61, 0x9B69, 0x9B71, 0x9B79, 0x9B80, 119 0x9B88, 0x9B90, 0x9B97, 0x9B9F, 0x9BA7, 0x9BAF, 0x9BB6, 0x9BBE, 0x9BC6, 0x9BCD, 0x9BD5, 120 0x9BDD, 0x9BE5, 0x9BEC, 0x9BF4, 0x9BFC, 0x9C03, 0x9C0B, 0x9C12, 0x9C1A, 0x9C22, 0x9C29, 121 0x9C31, 0x9C39, 0x9C40, 0x9C48, 0x9C50, 0x9C57, 0x9C5F, 0x9C66, 0x9C6E, 0x9C75, 0x9C7D, 122 0x9C85, 0x9C8C, 0x9C94, 0x9C9B, 0x9CA3, 0x9CAA, 0x9CB2, 0x9CBA, 0x9CC1, 0x9CC9, 0x9CD0, 123 0x9CD8, 0x9CDF, 0x9CE7, 0x9CEE, 0x9CF6, 0x9CFD, 0x9D05, 0x9D0C, 0x9D14, 0x9D1B, 0x9D23, 124 0x9D2A, 0x9D32, 0x9D39, 0x9D40, 0x9D48, 0x9D4F, 0x9D57, 0x9D5E, 0x9D66, 0x9D6D, 0x9D75, 125 0x9D7C, 0x9D83, 0x9D8B, 0x9D92, 0x9D9A, 0x9DA1, 0x9DA8, 0x9DB0, 0x9DB7, 0x9DBE, 0x9DC6, 126 0x9DCD, 0x9DD5, 0x9DDC, 0x9DE3, 0x9DEB, 0x9DF2, 0x9DF9, 0x9E01, 0x9E08, 0x9E0F, 0x9E17, 127 0x9E1E, 0x9E25, 0x9E2D, 0x9E34, 0x9E3B, 0x9E43, 0x9E4A, 0x9E51, 0x9E58, 0x9E60, 0x9E67, 128 0x9E6E, 0x9E75, 0x9E7D, 0x9E84, 0x9E8B, 0x9E92, 0x9E9A, 0x9EA1, 0x9EA8, 0x9EAF, 0x9EB7, 129 0x9EBE, 0x9EC5, 0x9ECC, 0x9ED4, 0x9EDB, 0x9EE2, 0x9EE9, 0x9EF0, 0x9EF7, 0x9EFF, 0x9F06, 130 0x9F0D, 0x9F14, 0x9F1B, 0x9F23, 0x9F2A, 0x9F31, 0x9F38, 0x9F3F, 0x9F46, 0x9F4D, 0x9F55, 131 0x9F5C, 0x9F63, 0x9F6A, 0x9F71, 0x9F78, 0x9F7F, 0x9F86, 0x9F8D, 0x9F95, 0x9F9C, 0x9FA3, 132 0x9FAA, 0x9FB1, 0x9FB8, 0x9FBF, 0x9FC6, 0x9FCD, 0x9FD4, 0x9FDB, 0x9FE2, 0x9FE9, 0x9FF0, 133 0x9FF7, 0x9FFF, 134 }; 135 136 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 137 struct drm_crtc_state *state); 138 139 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 140 { 141 stats->frames = 0; 142 stats->vblank = 0; 143 stats->underflow = 0; 144 stats->overflow = 0; 145 } 146 147 /* Reads the active copy of a register. */ 148 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 149 { 150 u32 value; 151 152 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 153 value = tegra_dc_readl(dc, offset); 154 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 155 156 return value; 157 } 158 159 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 160 unsigned int offset) 161 { 162 if (offset >= 0x500 && offset <= 0x638) { 163 offset = 0x000 + (offset - 0x500); 164 return plane->offset + offset; 165 } 166 167 if (offset >= 0x700 && offset <= 0x719) { 168 offset = 0x180 + (offset - 0x700); 169 return plane->offset + offset; 170 } 171 172 if (offset >= 0x800 && offset <= 0x839) { 173 offset = 0x1c0 + (offset - 0x800); 174 return plane->offset + offset; 175 } 176 177 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 178 179 return plane->offset + offset; 180 } 181 182 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 183 unsigned int offset) 184 { 185 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 186 } 187 188 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 189 unsigned int offset) 190 { 191 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 192 } 193 194 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 195 { 196 struct device_node *np = dc->dev->of_node; 197 struct of_phandle_iterator it; 198 int err; 199 200 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 201 if (it.node == dev->of_node) { 202 of_node_put(it.node); 203 return true; 204 } 205 206 return false; 207 } 208 209 /* 210 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 211 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 212 * Latching happens mmediately if the display controller is in STOP mode or 213 * on the next frame boundary otherwise. 214 * 215 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 216 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 217 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 218 * into the ACTIVE copy, either immediately if the display controller is in 219 * STOP mode, or at the next frame boundary otherwise. 220 */ 221 void tegra_dc_commit(struct tegra_dc *dc) 222 { 223 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 224 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 225 } 226 227 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 228 unsigned int bpp) 229 { 230 fixed20_12 outf = dfixed_init(out); 231 fixed20_12 inf = dfixed_init(in); 232 u32 dda_inc; 233 int max; 234 235 if (v) 236 max = 15; 237 else { 238 switch (bpp) { 239 case 2: 240 max = 8; 241 break; 242 243 default: 244 WARN_ON_ONCE(1); 245 fallthrough; 246 case 4: 247 max = 4; 248 break; 249 } 250 } 251 252 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 253 inf.full -= dfixed_const(1); 254 255 dda_inc = dfixed_div(inf, outf); 256 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 257 258 return dda_inc; 259 } 260 261 static inline u32 compute_initial_dda(unsigned int in) 262 { 263 fixed20_12 inf = dfixed_init(in); 264 return dfixed_frac(inf); 265 } 266 267 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 268 { 269 u32 background[3] = { 270 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 271 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 272 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 273 }; 274 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 275 BLEND_COLOR_KEY_NONE; 276 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 277 struct tegra_plane_state *state; 278 u32 blending[2]; 279 unsigned int i; 280 281 /* disable blending for non-overlapping case */ 282 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 283 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 284 285 state = to_tegra_plane_state(plane->base.state); 286 287 if (state->opaque) { 288 /* 289 * Since custom fix-weight blending isn't utilized and weight 290 * of top window is set to max, we can enforce dependent 291 * blending which in this case results in transparent bottom 292 * window if top window is opaque and if top window enables 293 * alpha blending, then bottom window is getting alpha value 294 * of 1 minus the sum of alpha components of the overlapping 295 * plane. 296 */ 297 background[0] |= BLEND_CONTROL_DEPENDENT; 298 background[1] |= BLEND_CONTROL_DEPENDENT; 299 300 /* 301 * The region where three windows overlap is the intersection 302 * of the two regions where two windows overlap. It contributes 303 * to the area if all of the windows on top of it have an alpha 304 * component. 305 */ 306 switch (state->base.normalized_zpos) { 307 case 0: 308 if (state->blending[0].alpha && 309 state->blending[1].alpha) 310 background[2] |= BLEND_CONTROL_DEPENDENT; 311 break; 312 313 case 1: 314 background[2] |= BLEND_CONTROL_DEPENDENT; 315 break; 316 } 317 } else { 318 /* 319 * Enable alpha blending if pixel format has an alpha 320 * component. 321 */ 322 foreground |= BLEND_CONTROL_ALPHA; 323 324 /* 325 * If any of the windows on top of this window is opaque, it 326 * will completely conceal this window within that area. If 327 * top window has an alpha component, it is blended over the 328 * bottom window. 329 */ 330 for (i = 0; i < 2; i++) { 331 if (state->blending[i].alpha && 332 state->blending[i].top) 333 background[i] |= BLEND_CONTROL_DEPENDENT; 334 } 335 336 switch (state->base.normalized_zpos) { 337 case 0: 338 if (state->blending[0].alpha && 339 state->blending[1].alpha) 340 background[2] |= BLEND_CONTROL_DEPENDENT; 341 break; 342 343 case 1: 344 /* 345 * When both middle and topmost windows have an alpha, 346 * these windows a mixed together and then the result 347 * is blended over the bottom window. 348 */ 349 if (state->blending[0].alpha && 350 state->blending[0].top) 351 background[2] |= BLEND_CONTROL_ALPHA; 352 353 if (state->blending[1].alpha && 354 state->blending[1].top) 355 background[2] |= BLEND_CONTROL_ALPHA; 356 break; 357 } 358 } 359 360 switch (state->base.normalized_zpos) { 361 case 0: 362 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 363 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 364 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 365 break; 366 367 case 1: 368 /* 369 * If window B / C is topmost, then X / Y registers are 370 * matching the order of blending[...] state indices, 371 * otherwise a swap is required. 372 */ 373 if (!state->blending[0].top && state->blending[1].top) { 374 blending[0] = foreground; 375 blending[1] = background[1]; 376 } else { 377 blending[0] = background[0]; 378 blending[1] = foreground; 379 } 380 381 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 382 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 383 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 384 break; 385 386 case 2: 387 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 388 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 389 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 390 break; 391 } 392 } 393 394 static void tegra_plane_setup_blending(struct tegra_plane *plane, 395 const struct tegra_dc_window *window) 396 { 397 u32 value; 398 399 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 400 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 401 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 402 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 403 404 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 405 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 406 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 407 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 408 409 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 410 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 411 } 412 413 static bool 414 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 415 const struct tegra_dc_window *window) 416 { 417 struct tegra_dc *dc = plane->dc; 418 419 if (window->src.w == window->dst.w) 420 return false; 421 422 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 423 return false; 424 425 return true; 426 } 427 428 static bool 429 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 430 const struct tegra_dc_window *window) 431 { 432 struct tegra_dc *dc = plane->dc; 433 434 if (window->src.h == window->dst.h) 435 return false; 436 437 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 438 return false; 439 440 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 441 return false; 442 443 return true; 444 } 445 446 static void tegra_dc_setup_window(struct tegra_plane *plane, 447 const struct tegra_dc_window *window) 448 { 449 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 450 struct tegra_dc *dc = plane->dc; 451 unsigned int planes; 452 u32 value; 453 bool yuv; 454 455 /* 456 * For YUV planar modes, the number of bytes per pixel takes into 457 * account only the luma component and therefore is 1. 458 */ 459 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL); 460 if (!yuv) 461 bpp = window->bits_per_pixel / 8; 462 else 463 bpp = (planes > 1) ? 1 : 2; 464 465 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 466 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 467 468 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 469 tegra_plane_writel(plane, value, DC_WIN_POSITION); 470 471 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 472 tegra_plane_writel(plane, value, DC_WIN_SIZE); 473 474 h_offset = window->src.x * bpp; 475 v_offset = window->src.y; 476 h_size = window->src.w * bpp; 477 v_size = window->src.h; 478 479 if (window->reflect_x) 480 h_offset += (window->src.w - 1) * bpp; 481 482 if (window->reflect_y) 483 v_offset += window->src.h - 1; 484 485 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 486 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 487 488 /* 489 * For DDA computations the number of bytes per pixel for YUV planar 490 * modes needs to take into account all Y, U and V components. 491 */ 492 if (yuv && planes > 1) 493 bpp = 2; 494 495 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 496 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 497 498 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 499 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 500 501 h_dda = compute_initial_dda(window->src.x); 502 v_dda = compute_initial_dda(window->src.y); 503 504 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 505 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 506 507 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 508 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 509 510 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 511 512 if (yuv && planes > 1) { 513 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 514 515 if (planes > 2) 516 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 517 518 value = window->stride[1] << 16 | window->stride[0]; 519 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 520 } else { 521 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 522 } 523 524 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 525 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 526 527 if (dc->soc->supports_block_linear) { 528 unsigned long height = window->tiling.value; 529 530 switch (window->tiling.mode) { 531 case TEGRA_BO_TILING_MODE_PITCH: 532 value = DC_WINBUF_SURFACE_KIND_PITCH; 533 break; 534 535 case TEGRA_BO_TILING_MODE_TILED: 536 value = DC_WINBUF_SURFACE_KIND_TILED; 537 break; 538 539 case TEGRA_BO_TILING_MODE_BLOCK: 540 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 541 DC_WINBUF_SURFACE_KIND_BLOCK; 542 break; 543 } 544 545 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 546 } else { 547 switch (window->tiling.mode) { 548 case TEGRA_BO_TILING_MODE_PITCH: 549 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 550 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 551 break; 552 553 case TEGRA_BO_TILING_MODE_TILED: 554 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 555 DC_WIN_BUFFER_ADDR_MODE_TILE; 556 break; 557 558 case TEGRA_BO_TILING_MODE_BLOCK: 559 /* 560 * No need to handle this here because ->atomic_check 561 * will already have filtered it out. 562 */ 563 break; 564 } 565 566 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 567 } 568 569 value = WIN_ENABLE; 570 571 if (yuv) { 572 /* setup default colorspace conversion coefficients */ 573 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 574 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 575 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 576 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 577 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 578 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 579 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 580 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 581 582 value |= CSC_ENABLE; 583 } else if (window->bits_per_pixel < 24) { 584 value |= COLOR_EXPAND; 585 } 586 587 if (window->reflect_x) 588 value |= H_DIRECTION; 589 590 if (window->reflect_y) 591 value |= V_DIRECTION; 592 593 if (tegra_plane_use_horizontal_filtering(plane, window)) { 594 /* 595 * Enable horizontal 6-tap filter and set filtering 596 * coefficients to the default values defined in TRM. 597 */ 598 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 599 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 600 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 601 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 602 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 603 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 604 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 605 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 606 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 607 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 608 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 609 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 610 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 611 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 612 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 613 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 614 615 value |= H_FILTER; 616 } 617 618 if (tegra_plane_use_vertical_filtering(plane, window)) { 619 unsigned int i, k; 620 621 /* 622 * Enable vertical 2-tap filter and set filtering 623 * coefficients to the default values defined in TRM. 624 */ 625 for (i = 0, k = 128; i < 16; i++, k -= 8) 626 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 627 628 value |= V_FILTER; 629 } 630 631 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 632 633 if (dc->soc->has_legacy_blending) 634 tegra_plane_setup_blending_legacy(plane); 635 else 636 tegra_plane_setup_blending(plane, window); 637 } 638 639 static const u32 tegra20_primary_formats[] = { 640 DRM_FORMAT_ARGB4444, 641 DRM_FORMAT_ARGB1555, 642 DRM_FORMAT_RGB565, 643 DRM_FORMAT_RGBA5551, 644 DRM_FORMAT_ABGR8888, 645 DRM_FORMAT_ARGB8888, 646 /* non-native formats */ 647 DRM_FORMAT_XRGB1555, 648 DRM_FORMAT_RGBX5551, 649 DRM_FORMAT_XBGR8888, 650 DRM_FORMAT_XRGB8888, 651 }; 652 653 static const u64 tegra20_modifiers[] = { 654 DRM_FORMAT_MOD_LINEAR, 655 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 656 DRM_FORMAT_MOD_INVALID 657 }; 658 659 static const u32 tegra114_primary_formats[] = { 660 DRM_FORMAT_ARGB4444, 661 DRM_FORMAT_ARGB1555, 662 DRM_FORMAT_RGB565, 663 DRM_FORMAT_RGBA5551, 664 DRM_FORMAT_ABGR8888, 665 DRM_FORMAT_ARGB8888, 666 /* new on Tegra114 */ 667 DRM_FORMAT_ABGR4444, 668 DRM_FORMAT_ABGR1555, 669 DRM_FORMAT_BGRA5551, 670 DRM_FORMAT_XRGB1555, 671 DRM_FORMAT_RGBX5551, 672 DRM_FORMAT_XBGR1555, 673 DRM_FORMAT_BGRX5551, 674 DRM_FORMAT_BGR565, 675 DRM_FORMAT_BGRA8888, 676 DRM_FORMAT_RGBA8888, 677 DRM_FORMAT_XRGB8888, 678 DRM_FORMAT_XBGR8888, 679 }; 680 681 static const u32 tegra124_primary_formats[] = { 682 DRM_FORMAT_ARGB4444, 683 DRM_FORMAT_ARGB1555, 684 DRM_FORMAT_RGB565, 685 DRM_FORMAT_RGBA5551, 686 DRM_FORMAT_ABGR8888, 687 DRM_FORMAT_ARGB8888, 688 /* new on Tegra114 */ 689 DRM_FORMAT_ABGR4444, 690 DRM_FORMAT_ABGR1555, 691 DRM_FORMAT_BGRA5551, 692 DRM_FORMAT_XRGB1555, 693 DRM_FORMAT_RGBX5551, 694 DRM_FORMAT_XBGR1555, 695 DRM_FORMAT_BGRX5551, 696 DRM_FORMAT_BGR565, 697 DRM_FORMAT_BGRA8888, 698 DRM_FORMAT_RGBA8888, 699 DRM_FORMAT_XRGB8888, 700 DRM_FORMAT_XBGR8888, 701 /* new on Tegra124 */ 702 DRM_FORMAT_RGBX8888, 703 DRM_FORMAT_BGRX8888, 704 }; 705 706 static const u64 tegra124_modifiers[] = { 707 DRM_FORMAT_MOD_LINEAR, 708 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 709 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 710 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 711 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 712 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 713 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 714 DRM_FORMAT_MOD_INVALID 715 }; 716 717 static int tegra_plane_atomic_check(struct drm_plane *plane, 718 struct drm_atomic_commit *state) 719 { 720 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 721 plane); 722 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 723 unsigned int supported_rotation = DRM_MODE_ROTATE_0 | 724 DRM_MODE_REFLECT_X | 725 DRM_MODE_REFLECT_Y; 726 unsigned int rotation = new_plane_state->rotation; 727 struct tegra_bo_tiling *tiling = &plane_state->tiling; 728 struct tegra_plane *tegra = to_tegra_plane(plane); 729 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); 730 int err; 731 732 plane_state->peak_memory_bandwidth = 0; 733 plane_state->avg_memory_bandwidth = 0; 734 735 /* no need for further checks if the plane is being disabled */ 736 if (!new_plane_state->crtc) { 737 plane_state->total_peak_memory_bandwidth = 0; 738 return 0; 739 } 740 741 err = tegra_plane_format(new_plane_state->fb->format->format, 742 &plane_state->format, 743 &plane_state->swap); 744 if (err < 0) 745 return err; 746 747 /* 748 * Tegra20 and Tegra30 are special cases here because they support 749 * only variants of specific formats with an alpha component, but not 750 * the corresponding opaque formats. However, the opaque formats can 751 * be emulated by disabling alpha blending for the plane. 752 */ 753 if (dc->soc->has_legacy_blending) { 754 err = tegra_plane_setup_legacy_state(tegra, plane_state); 755 if (err < 0) 756 return err; 757 } 758 759 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 760 if (err < 0) 761 return err; 762 763 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 764 !dc->soc->supports_block_linear) { 765 DRM_ERROR("hardware doesn't support block linear mode\n"); 766 return -EINVAL; 767 } 768 769 /* 770 * Older userspace used custom BO flag in order to specify the Y 771 * reflection, while modern userspace uses the generic DRM rotation 772 * property in order to achieve the same result. The legacy BO flag 773 * duplicates the DRM rotation property when both are set. 774 */ 775 if (tegra_fb_is_bottom_up(new_plane_state->fb)) 776 rotation |= DRM_MODE_REFLECT_Y; 777 778 rotation = drm_rotation_simplify(rotation, supported_rotation); 779 780 if (rotation & DRM_MODE_REFLECT_X) 781 plane_state->reflect_x = true; 782 else 783 plane_state->reflect_x = false; 784 785 if (rotation & DRM_MODE_REFLECT_Y) 786 plane_state->reflect_y = true; 787 else 788 plane_state->reflect_y = false; 789 790 /* 791 * Tegra doesn't support different strides for U and V planes so we 792 * error out if the user tries to display a framebuffer with such a 793 * configuration. 794 */ 795 if (new_plane_state->fb->format->num_planes > 2) { 796 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { 797 DRM_ERROR("unsupported UV-plane configuration\n"); 798 return -EINVAL; 799 } 800 } 801 802 err = tegra_plane_state_add(tegra, new_plane_state); 803 if (err < 0) 804 return err; 805 806 return 0; 807 } 808 809 static void tegra_plane_atomic_disable(struct drm_plane *plane, 810 struct drm_atomic_commit *state) 811 { 812 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 813 plane); 814 struct tegra_plane *p = to_tegra_plane(plane); 815 u32 value; 816 817 /* rien ne va plus */ 818 if (!old_state || !old_state->crtc) 819 return; 820 821 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 822 value &= ~WIN_ENABLE; 823 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 824 } 825 826 static void tegra_plane_atomic_update(struct drm_plane *plane, 827 struct drm_atomic_commit *state) 828 { 829 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 830 plane); 831 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 832 struct drm_framebuffer *fb = new_state->fb; 833 struct tegra_plane *p = to_tegra_plane(plane); 834 struct tegra_dc_window window; 835 unsigned int i; 836 837 /* rien ne va plus */ 838 if (!new_state->crtc || !new_state->fb) 839 return; 840 841 if (!new_state->visible) 842 return tegra_plane_atomic_disable(plane, state); 843 844 memset(&window, 0, sizeof(window)); 845 window.src.x = new_state->src.x1 >> 16; 846 window.src.y = new_state->src.y1 >> 16; 847 window.src.w = drm_rect_width(&new_state->src) >> 16; 848 window.src.h = drm_rect_height(&new_state->src) >> 16; 849 window.dst.x = new_state->dst.x1; 850 window.dst.y = new_state->dst.y1; 851 window.dst.w = drm_rect_width(&new_state->dst); 852 window.dst.h = drm_rect_height(&new_state->dst); 853 window.bits_per_pixel = fb->format->cpp[0] * 8; 854 window.reflect_x = tegra_plane_state->reflect_x; 855 window.reflect_y = tegra_plane_state->reflect_y; 856 857 /* copy from state */ 858 window.zpos = new_state->normalized_zpos; 859 window.tiling = tegra_plane_state->tiling; 860 window.format = tegra_plane_state->format; 861 window.swap = tegra_plane_state->swap; 862 863 for (i = 0; i < fb->format->num_planes; i++) { 864 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; 865 866 /* 867 * Tegra uses a shared stride for UV planes. Framebuffers are 868 * already checked for this in the tegra_plane_atomic_check() 869 * function, so it's safe to ignore the V-plane pitch here. 870 */ 871 if (i < 2) 872 window.stride[i] = fb->pitches[i]; 873 } 874 875 tegra_dc_setup_window(p, &window); 876 } 877 878 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 879 .prepare_fb = tegra_plane_prepare_fb, 880 .cleanup_fb = tegra_plane_cleanup_fb, 881 .atomic_check = tegra_plane_atomic_check, 882 .atomic_disable = tegra_plane_atomic_disable, 883 .atomic_update = tegra_plane_atomic_update, 884 }; 885 886 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 887 { 888 /* 889 * Ideally this would use drm_crtc_mask(), but that would require the 890 * CRTC to already be in the mode_config's list of CRTCs. However, it 891 * will only be added to that list in the drm_crtc_init_with_planes() 892 * (in tegra_dc_init()), which in turn requires registration of these 893 * planes. So we have ourselves a nice little chicken and egg problem 894 * here. 895 * 896 * We work around this by manually creating the mask from the number 897 * of CRTCs that have been registered, and should therefore always be 898 * the same as drm_crtc_index() after registration. 899 */ 900 return 1 << drm->mode_config.num_crtc; 901 } 902 903 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 904 struct tegra_dc *dc) 905 { 906 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 907 unsigned int blend_caps = BIT(DRM_MODE_BLEND_COVERAGE); 908 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 909 struct tegra_plane *plane; 910 unsigned int num_formats; 911 const u64 *modifiers; 912 const u32 *formats; 913 int err; 914 915 plane = kzalloc_obj(*plane); 916 if (!plane) 917 return ERR_PTR(-ENOMEM); 918 919 /* Always use window A as primary window */ 920 plane->offset = 0xa00; 921 plane->index = 0; 922 plane->dc = dc; 923 924 num_formats = dc->soc->num_primary_formats; 925 formats = dc->soc->primary_formats; 926 modifiers = dc->soc->modifiers; 927 928 err = tegra_plane_interconnect_init(plane); 929 if (err) { 930 kfree(plane); 931 return ERR_PTR(err); 932 } 933 934 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 935 &tegra_plane_funcs, formats, 936 num_formats, modifiers, type, NULL); 937 if (err < 0) { 938 kfree(plane); 939 return ERR_PTR(err); 940 } 941 942 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 943 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 944 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 945 946 err = drm_plane_create_rotation_property(&plane->base, 947 DRM_MODE_ROTATE_0, 948 DRM_MODE_ROTATE_0 | 949 DRM_MODE_ROTATE_180 | 950 DRM_MODE_REFLECT_X | 951 DRM_MODE_REFLECT_Y); 952 if (err < 0) 953 dev_err(dc->dev, "failed to create rotation property: %d\n", 954 err); 955 956 return &plane->base; 957 } 958 959 static const u32 tegra_legacy_cursor_plane_formats[] = { 960 DRM_FORMAT_RGBA8888, 961 }; 962 963 static const u32 tegra_cursor_plane_formats[] = { 964 DRM_FORMAT_ARGB8888, 965 }; 966 967 static int tegra_cursor_atomic_check(struct drm_plane *plane, 968 struct drm_atomic_commit *state) 969 { 970 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 971 plane); 972 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 973 struct tegra_plane *tegra = to_tegra_plane(plane); 974 int err; 975 976 plane_state->peak_memory_bandwidth = 0; 977 plane_state->avg_memory_bandwidth = 0; 978 979 /* no need for further checks if the plane is being disabled */ 980 if (!new_plane_state->crtc) { 981 plane_state->total_peak_memory_bandwidth = 0; 982 return 0; 983 } 984 985 /* scaling not supported for cursor */ 986 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || 987 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) 988 return -EINVAL; 989 990 /* only square cursors supported */ 991 if (new_plane_state->src_w != new_plane_state->src_h) 992 return -EINVAL; 993 994 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && 995 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) 996 return -EINVAL; 997 998 err = tegra_plane_state_add(tegra, new_plane_state); 999 if (err < 0) 1000 return err; 1001 1002 return 0; 1003 } 1004 1005 static void __tegra_cursor_atomic_update(struct drm_plane *plane, 1006 struct drm_plane_state *new_state) 1007 { 1008 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 1009 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 1010 struct tegra_drm *tegra = plane->dev->dev_private; 1011 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1012 u64 dma_mask = *dc->dev->dma_mask; 1013 #endif 1014 unsigned int x, y; 1015 u32 value = 0; 1016 1017 /* rien ne va plus */ 1018 if (!new_state->crtc || !new_state->fb) 1019 return; 1020 1021 /* 1022 * Legacy display supports hardware clipping of the cursor, but 1023 * nvdisplay relies on software to clip the cursor to the screen. 1024 */ 1025 if (!dc->soc->has_nvdisplay) 1026 value |= CURSOR_CLIP_DISPLAY; 1027 1028 switch (new_state->crtc_w) { 1029 case 32: 1030 value |= CURSOR_SIZE_32x32; 1031 break; 1032 1033 case 64: 1034 value |= CURSOR_SIZE_64x64; 1035 break; 1036 1037 case 128: 1038 value |= CURSOR_SIZE_128x128; 1039 break; 1040 1041 case 256: 1042 value |= CURSOR_SIZE_256x256; 1043 break; 1044 1045 default: 1046 WARN(1, "cursor size %ux%u not supported\n", 1047 new_state->crtc_w, new_state->crtc_h); 1048 return; 1049 } 1050 1051 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; 1052 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 1053 1054 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1055 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); 1056 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 1057 #endif 1058 1059 /* enable cursor and set blend mode */ 1060 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1061 value |= CURSOR_ENABLE; 1062 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1063 1064 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 1065 value &= ~CURSOR_DST_BLEND_MASK; 1066 value &= ~CURSOR_SRC_BLEND_MASK; 1067 1068 if (dc->soc->has_nvdisplay) 1069 value &= ~CURSOR_COMPOSITION_MODE_XOR; 1070 else 1071 value |= CURSOR_MODE_NORMAL; 1072 1073 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 1074 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 1075 value |= CURSOR_ALPHA; 1076 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 1077 1078 /* nvdisplay relies on software for clipping */ 1079 if (dc->soc->has_nvdisplay) { 1080 struct drm_rect src; 1081 1082 x = new_state->dst.x1; 1083 y = new_state->dst.y1; 1084 1085 drm_rect_fp_to_int(&src, &new_state->src); 1086 1087 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); 1088 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); 1089 1090 value = (drm_rect_height(&src) & tegra->vmask) << 16 | 1091 (drm_rect_width(&src) & tegra->hmask); 1092 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); 1093 } else { 1094 x = new_state->crtc_x; 1095 y = new_state->crtc_y; 1096 } 1097 1098 /* position the cursor */ 1099 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); 1100 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 1101 } 1102 1103 static void tegra_cursor_atomic_update(struct drm_plane *plane, 1104 struct drm_atomic_commit *state) 1105 { 1106 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1107 1108 __tegra_cursor_atomic_update(plane, new_state); 1109 } 1110 1111 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 1112 struct drm_atomic_commit *state) 1113 { 1114 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1115 plane); 1116 struct tegra_dc *dc; 1117 u32 value; 1118 1119 /* rien ne va plus */ 1120 if (!old_state || !old_state->crtc) 1121 return; 1122 1123 dc = to_tegra_dc(old_state->crtc); 1124 1125 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1126 value &= ~CURSOR_ENABLE; 1127 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1128 } 1129 1130 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_commit *state, 1131 bool flip) 1132 { 1133 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1134 struct drm_crtc_state *crtc_state; 1135 int min_scale, max_scale; 1136 int err; 1137 1138 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); 1139 if (WARN_ON(!crtc_state)) 1140 return -EINVAL; 1141 1142 if (!crtc_state->active) 1143 return -EINVAL; 1144 1145 if (plane->state->crtc != new_state->crtc || 1146 plane->state->src_w != new_state->src_w || 1147 plane->state->src_h != new_state->src_h || 1148 plane->state->crtc_w != new_state->crtc_w || 1149 plane->state->crtc_h != new_state->crtc_h || 1150 plane->state->fb != new_state->fb || 1151 plane->state->fb == NULL) 1152 return -EINVAL; 1153 1154 min_scale = (1 << 16) / 8; 1155 max_scale = (8 << 16) / 1; 1156 1157 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale, 1158 true, true); 1159 if (err < 0) 1160 return err; 1161 1162 if (new_state->visible != plane->state->visible) 1163 return -EINVAL; 1164 1165 return 0; 1166 } 1167 1168 static void tegra_cursor_atomic_async_update(struct drm_plane *plane, 1169 struct drm_atomic_commit *state) 1170 { 1171 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1172 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 1173 1174 plane->state->src_x = new_state->src_x; 1175 plane->state->src_y = new_state->src_y; 1176 plane->state->crtc_x = new_state->crtc_x; 1177 plane->state->crtc_y = new_state->crtc_y; 1178 1179 if (new_state->visible) { 1180 struct tegra_plane *p = to_tegra_plane(plane); 1181 u32 value; 1182 1183 __tegra_cursor_atomic_update(plane, new_state); 1184 1185 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; 1186 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1187 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1188 1189 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; 1190 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1191 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1192 } 1193 } 1194 1195 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 1196 .prepare_fb = tegra_plane_prepare_fb, 1197 .cleanup_fb = tegra_plane_cleanup_fb, 1198 .atomic_check = tegra_cursor_atomic_check, 1199 .atomic_update = tegra_cursor_atomic_update, 1200 .atomic_disable = tegra_cursor_atomic_disable, 1201 .atomic_async_check = tegra_cursor_atomic_async_check, 1202 .atomic_async_update = tegra_cursor_atomic_async_update, 1203 }; 1204 1205 static const uint64_t linear_modifiers[] = { 1206 DRM_FORMAT_MOD_LINEAR, 1207 DRM_FORMAT_MOD_INVALID 1208 }; 1209 1210 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 1211 struct tegra_dc *dc) 1212 { 1213 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1214 unsigned int blend_caps = BIT(DRM_MODE_BLEND_COVERAGE); 1215 struct tegra_plane *plane; 1216 unsigned int num_formats; 1217 const u32 *formats; 1218 int err; 1219 1220 plane = kzalloc_obj(*plane); 1221 if (!plane) 1222 return ERR_PTR(-ENOMEM); 1223 1224 /* 1225 * This index is kind of fake. The cursor isn't a regular plane, but 1226 * its update and activation request bits in DC_CMD_STATE_CONTROL do 1227 * use the same programming. Setting this fake index here allows the 1228 * code in tegra_add_plane_state() to do the right thing without the 1229 * need to special-casing the cursor plane. 1230 */ 1231 plane->index = 6; 1232 plane->dc = dc; 1233 1234 if (!dc->soc->has_nvdisplay) { 1235 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); 1236 formats = tegra_legacy_cursor_plane_formats; 1237 1238 err = tegra_plane_interconnect_init(plane); 1239 if (err) { 1240 kfree(plane); 1241 return ERR_PTR(err); 1242 } 1243 } else { 1244 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 1245 formats = tegra_cursor_plane_formats; 1246 } 1247 1248 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1249 &tegra_plane_funcs, formats, 1250 num_formats, linear_modifiers, 1251 DRM_PLANE_TYPE_CURSOR, NULL); 1252 if (err < 0) { 1253 kfree(plane); 1254 return ERR_PTR(err); 1255 } 1256 1257 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 1258 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 1259 drm_plane_create_zpos_immutable_property(&plane->base, 255); 1260 1261 return &plane->base; 1262 } 1263 1264 static const u32 tegra20_overlay_formats[] = { 1265 DRM_FORMAT_ARGB4444, 1266 DRM_FORMAT_ARGB1555, 1267 DRM_FORMAT_RGB565, 1268 DRM_FORMAT_RGBA5551, 1269 DRM_FORMAT_ABGR8888, 1270 DRM_FORMAT_ARGB8888, 1271 /* non-native formats */ 1272 DRM_FORMAT_XRGB1555, 1273 DRM_FORMAT_RGBX5551, 1274 DRM_FORMAT_XBGR8888, 1275 DRM_FORMAT_XRGB8888, 1276 /* planar formats */ 1277 DRM_FORMAT_UYVY, 1278 DRM_FORMAT_YUYV, 1279 DRM_FORMAT_YUV420, 1280 DRM_FORMAT_YUV422, 1281 }; 1282 1283 static const u32 tegra114_overlay_formats[] = { 1284 DRM_FORMAT_ARGB4444, 1285 DRM_FORMAT_ARGB1555, 1286 DRM_FORMAT_RGB565, 1287 DRM_FORMAT_RGBA5551, 1288 DRM_FORMAT_ABGR8888, 1289 DRM_FORMAT_ARGB8888, 1290 /* new on Tegra114 */ 1291 DRM_FORMAT_ABGR4444, 1292 DRM_FORMAT_ABGR1555, 1293 DRM_FORMAT_BGRA5551, 1294 DRM_FORMAT_XRGB1555, 1295 DRM_FORMAT_RGBX5551, 1296 DRM_FORMAT_XBGR1555, 1297 DRM_FORMAT_BGRX5551, 1298 DRM_FORMAT_BGR565, 1299 DRM_FORMAT_BGRA8888, 1300 DRM_FORMAT_RGBA8888, 1301 DRM_FORMAT_XRGB8888, 1302 DRM_FORMAT_XBGR8888, 1303 /* planar formats */ 1304 DRM_FORMAT_UYVY, 1305 DRM_FORMAT_YUYV, 1306 DRM_FORMAT_YUV420, 1307 DRM_FORMAT_YUV422, 1308 /* semi-planar formats */ 1309 DRM_FORMAT_NV12, 1310 DRM_FORMAT_NV21, 1311 DRM_FORMAT_NV16, 1312 DRM_FORMAT_NV61, 1313 DRM_FORMAT_NV24, 1314 DRM_FORMAT_NV42, 1315 }; 1316 1317 static const u32 tegra124_overlay_formats[] = { 1318 DRM_FORMAT_ARGB4444, 1319 DRM_FORMAT_ARGB1555, 1320 DRM_FORMAT_RGB565, 1321 DRM_FORMAT_RGBA5551, 1322 DRM_FORMAT_ABGR8888, 1323 DRM_FORMAT_ARGB8888, 1324 /* new on Tegra114 */ 1325 DRM_FORMAT_ABGR4444, 1326 DRM_FORMAT_ABGR1555, 1327 DRM_FORMAT_BGRA5551, 1328 DRM_FORMAT_XRGB1555, 1329 DRM_FORMAT_RGBX5551, 1330 DRM_FORMAT_XBGR1555, 1331 DRM_FORMAT_BGRX5551, 1332 DRM_FORMAT_BGR565, 1333 DRM_FORMAT_BGRA8888, 1334 DRM_FORMAT_RGBA8888, 1335 DRM_FORMAT_XRGB8888, 1336 DRM_FORMAT_XBGR8888, 1337 /* new on Tegra124 */ 1338 DRM_FORMAT_RGBX8888, 1339 DRM_FORMAT_BGRX8888, 1340 /* planar formats */ 1341 DRM_FORMAT_UYVY, 1342 DRM_FORMAT_YUYV, 1343 DRM_FORMAT_YVYU, 1344 DRM_FORMAT_VYUY, 1345 DRM_FORMAT_YUV420, /* YU12 */ 1346 DRM_FORMAT_YUV422, /* YU16 */ 1347 DRM_FORMAT_YUV444, /* YU24 */ 1348 /* semi-planar formats */ 1349 DRM_FORMAT_NV12, 1350 DRM_FORMAT_NV21, 1351 DRM_FORMAT_NV16, 1352 DRM_FORMAT_NV61, 1353 DRM_FORMAT_NV24, 1354 DRM_FORMAT_NV42, 1355 }; 1356 1357 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1358 struct tegra_dc *dc, 1359 unsigned int index, 1360 bool cursor) 1361 { 1362 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1363 unsigned int blend_caps = BIT(DRM_MODE_BLEND_COVERAGE); 1364 struct tegra_plane *plane; 1365 unsigned int num_formats; 1366 enum drm_plane_type type; 1367 const u32 *formats; 1368 int err; 1369 1370 plane = kzalloc_obj(*plane); 1371 if (!plane) 1372 return ERR_PTR(-ENOMEM); 1373 1374 plane->offset = 0xa00 + 0x200 * index; 1375 plane->index = index; 1376 plane->dc = dc; 1377 1378 num_formats = dc->soc->num_overlay_formats; 1379 formats = dc->soc->overlay_formats; 1380 1381 err = tegra_plane_interconnect_init(plane); 1382 if (err) { 1383 kfree(plane); 1384 return ERR_PTR(err); 1385 } 1386 1387 if (!cursor) 1388 type = DRM_PLANE_TYPE_OVERLAY; 1389 else 1390 type = DRM_PLANE_TYPE_CURSOR; 1391 1392 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1393 &tegra_plane_funcs, formats, 1394 num_formats, linear_modifiers, 1395 type, NULL); 1396 if (err < 0) { 1397 kfree(plane); 1398 return ERR_PTR(err); 1399 } 1400 1401 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1402 drm_plane_create_blend_mode_property(&plane->base, blend_caps); 1403 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1404 1405 err = drm_plane_create_rotation_property(&plane->base, 1406 DRM_MODE_ROTATE_0, 1407 DRM_MODE_ROTATE_0 | 1408 DRM_MODE_ROTATE_180 | 1409 DRM_MODE_REFLECT_X | 1410 DRM_MODE_REFLECT_Y); 1411 if (err < 0) 1412 dev_err(dc->dev, "failed to create rotation property: %d\n", 1413 err); 1414 1415 return &plane->base; 1416 } 1417 1418 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1419 struct tegra_dc *dc) 1420 { 1421 struct drm_plane *plane, *primary = NULL; 1422 unsigned int i, j; 1423 1424 for (i = 0; i < dc->soc->num_wgrps; i++) { 1425 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1426 1427 if (wgrp->dc == dc->pipe) { 1428 for (j = 0; j < wgrp->num_windows; j++) { 1429 unsigned int index = wgrp->windows[j]; 1430 enum drm_plane_type type; 1431 1432 if (primary) 1433 type = DRM_PLANE_TYPE_OVERLAY; 1434 else 1435 type = DRM_PLANE_TYPE_PRIMARY; 1436 1437 plane = tegra_shared_plane_create(drm, dc, 1438 wgrp->index, 1439 index, type); 1440 if (IS_ERR(plane)) 1441 return plane; 1442 1443 /* 1444 * Choose the first shared plane owned by this 1445 * head as the primary plane. 1446 */ 1447 if (!primary) 1448 primary = plane; 1449 } 1450 } 1451 } 1452 1453 return primary; 1454 } 1455 1456 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1457 struct tegra_dc *dc) 1458 { 1459 struct drm_plane *planes[2], *primary; 1460 unsigned int planes_num; 1461 unsigned int i; 1462 int err; 1463 1464 primary = tegra_primary_plane_create(drm, dc); 1465 if (IS_ERR(primary)) 1466 return primary; 1467 1468 if (dc->soc->supports_cursor) 1469 planes_num = 2; 1470 else 1471 planes_num = 1; 1472 1473 for (i = 0; i < planes_num; i++) { 1474 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1475 false); 1476 if (IS_ERR(planes[i])) { 1477 err = PTR_ERR(planes[i]); 1478 1479 while (i--) 1480 planes[i]->funcs->destroy(planes[i]); 1481 1482 primary->funcs->destroy(primary); 1483 return ERR_PTR(err); 1484 } 1485 } 1486 1487 return primary; 1488 } 1489 1490 static void tegra_dc_destroy(struct drm_crtc *crtc) 1491 { 1492 drm_crtc_cleanup(crtc); 1493 } 1494 1495 static void tegra_crtc_reset(struct drm_crtc *crtc) 1496 { 1497 struct tegra_dc_state *state = kzalloc_obj(*state); 1498 1499 if (crtc->state) 1500 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1501 1502 if (state) 1503 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1504 else 1505 __drm_atomic_helper_crtc_reset(crtc, NULL); 1506 } 1507 1508 static struct drm_crtc_state * 1509 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1510 { 1511 struct tegra_dc_state *state = to_dc_state(crtc->state); 1512 struct tegra_dc_state *copy; 1513 1514 copy = kmalloc_obj(*copy); 1515 if (!copy) 1516 return NULL; 1517 1518 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1519 copy->clk = state->clk; 1520 copy->pclk = state->pclk; 1521 copy->div = state->div; 1522 copy->planes = state->planes; 1523 1524 return ©->base; 1525 } 1526 1527 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1528 struct drm_crtc_state *state) 1529 { 1530 __drm_atomic_helper_crtc_destroy_state(state); 1531 kfree(state); 1532 } 1533 1534 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1535 1536 static const struct debugfs_reg32 tegra_dc_regs[] = { 1537 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1538 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1539 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1540 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1541 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1542 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1543 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1544 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1545 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1546 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1547 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1548 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1549 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1550 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1551 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1552 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1553 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1554 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1555 DEBUGFS_REG32(DC_CMD_INT_MASK), 1556 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1557 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1558 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1559 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1560 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1561 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1562 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1563 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1564 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1565 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1566 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1567 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1568 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1569 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1570 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1571 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1572 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1573 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1574 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1575 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1576 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1577 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1578 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1579 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1580 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1581 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1582 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1583 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1584 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1585 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1586 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1587 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1588 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1589 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1590 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1591 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1592 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1593 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1594 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1595 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1596 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1597 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1598 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1599 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1600 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1601 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1602 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1603 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1604 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1605 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1606 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1607 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1608 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1609 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1610 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1611 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1612 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1613 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1614 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1615 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1616 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1617 DEBUGFS_REG32(DC_DISP_ACTIVE), 1618 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1619 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1620 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1621 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1622 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1623 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1624 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1625 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1626 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1627 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1628 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1629 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1630 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1631 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1632 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1633 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1634 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1635 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1636 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1637 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1638 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1639 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1640 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1641 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1642 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1643 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1644 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1645 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1646 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1647 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1648 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1649 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1650 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1651 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1652 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1653 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1654 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1655 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1656 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1657 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1658 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1659 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1660 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1661 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1662 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1663 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1664 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1665 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1666 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1667 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1668 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1669 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1670 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1671 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1672 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1673 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1674 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1675 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1676 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1677 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1678 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1679 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1680 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1681 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1682 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1683 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1684 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1685 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1686 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1687 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1688 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1689 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1690 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1691 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1692 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1693 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1694 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1695 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1696 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1697 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1698 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1699 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1700 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1701 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1702 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1703 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1704 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1705 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1706 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1707 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1708 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1709 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1710 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1711 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1712 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1713 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1714 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1715 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1716 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1717 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1718 DEBUGFS_REG32(DC_WIN_POSITION), 1719 DEBUGFS_REG32(DC_WIN_SIZE), 1720 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1721 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1722 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1723 DEBUGFS_REG32(DC_WIN_DDA_INC), 1724 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1725 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1726 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1727 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1728 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1729 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1730 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1731 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1732 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1733 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1734 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1735 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1736 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1737 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1738 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1739 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1740 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1741 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1742 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1743 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1744 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1745 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1746 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1747 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1748 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1749 }; 1750 1751 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1752 { 1753 struct drm_info_node *node = s->private; 1754 struct tegra_dc *dc = node->info_ent->data; 1755 unsigned int i; 1756 int err = 0; 1757 1758 drm_modeset_lock(&dc->base.mutex, NULL); 1759 1760 if (!dc->base.state->active) { 1761 err = -EBUSY; 1762 goto unlock; 1763 } 1764 1765 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1766 unsigned int offset = tegra_dc_regs[i].offset; 1767 1768 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1769 offset, tegra_dc_readl(dc, offset)); 1770 } 1771 1772 unlock: 1773 drm_modeset_unlock(&dc->base.mutex); 1774 return err; 1775 } 1776 1777 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1778 { 1779 struct drm_info_node *node = s->private; 1780 struct tegra_dc *dc = node->info_ent->data; 1781 int err = 0; 1782 u32 value; 1783 1784 drm_modeset_lock(&dc->base.mutex, NULL); 1785 1786 if (!dc->base.state->active) { 1787 err = -EBUSY; 1788 goto unlock; 1789 } 1790 1791 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1792 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1793 tegra_dc_commit(dc); 1794 1795 drm_crtc_wait_one_vblank(&dc->base); 1796 drm_crtc_wait_one_vblank(&dc->base); 1797 1798 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1799 seq_printf(s, "%08x\n", value); 1800 1801 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1802 1803 unlock: 1804 drm_modeset_unlock(&dc->base.mutex); 1805 return err; 1806 } 1807 1808 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1809 { 1810 struct drm_info_node *node = s->private; 1811 struct tegra_dc *dc = node->info_ent->data; 1812 1813 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1814 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1815 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1816 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1817 1818 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); 1819 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); 1820 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); 1821 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); 1822 1823 return 0; 1824 } 1825 1826 static struct drm_info_list debugfs_files[] = { 1827 { "regs", tegra_dc_show_regs, 0, NULL }, 1828 { "crc", tegra_dc_show_crc, 0, NULL }, 1829 { "stats", tegra_dc_show_stats, 0, NULL }, 1830 }; 1831 1832 static int tegra_dc_late_register(struct drm_crtc *crtc) 1833 { 1834 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1835 struct drm_minor *minor = crtc->dev->primary; 1836 struct dentry *root; 1837 struct tegra_dc *dc = to_tegra_dc(crtc); 1838 1839 #ifdef CONFIG_DEBUG_FS 1840 root = crtc->debugfs_entry; 1841 #else 1842 root = NULL; 1843 #endif 1844 1845 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1846 GFP_KERNEL); 1847 if (!dc->debugfs_files) 1848 return -ENOMEM; 1849 1850 for (i = 0; i < count; i++) 1851 dc->debugfs_files[i].data = dc; 1852 1853 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1854 1855 return 0; 1856 } 1857 1858 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1859 { 1860 unsigned int count = ARRAY_SIZE(debugfs_files); 1861 struct drm_minor *minor = crtc->dev->primary; 1862 struct tegra_dc *dc = to_tegra_dc(crtc); 1863 struct dentry *root; 1864 1865 #ifdef CONFIG_DEBUG_FS 1866 root = crtc->debugfs_entry; 1867 #else 1868 root = NULL; 1869 #endif 1870 1871 drm_debugfs_remove_files(dc->debugfs_files, count, root, minor); 1872 kfree(dc->debugfs_files); 1873 dc->debugfs_files = NULL; 1874 } 1875 1876 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1877 { 1878 struct tegra_dc *dc = to_tegra_dc(crtc); 1879 1880 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1881 if (dc->syncpt && !dc->soc->has_nvdisplay) 1882 return host1x_syncpt_read(dc->syncpt); 1883 1884 /* fallback to software emulated VBLANK counter */ 1885 return (u32)drm_crtc_vblank_count(&dc->base); 1886 } 1887 1888 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1889 { 1890 struct tegra_dc *dc = to_tegra_dc(crtc); 1891 u32 value; 1892 1893 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1894 value |= VBLANK_INT; 1895 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1896 1897 return 0; 1898 } 1899 1900 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1901 { 1902 struct tegra_dc *dc = to_tegra_dc(crtc); 1903 u32 value; 1904 1905 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1906 value &= ~VBLANK_INT; 1907 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1908 } 1909 1910 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1911 .page_flip = drm_atomic_helper_page_flip, 1912 .set_config = drm_atomic_helper_set_config, 1913 .destroy = tegra_dc_destroy, 1914 .reset = tegra_crtc_reset, 1915 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1916 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1917 .late_register = tegra_dc_late_register, 1918 .early_unregister = tegra_dc_early_unregister, 1919 .get_vblank_counter = tegra_dc_get_vblank_counter, 1920 .enable_vblank = tegra_dc_enable_vblank, 1921 .disable_vblank = tegra_dc_disable_vblank, 1922 }; 1923 1924 static int tegra_dc_set_timings(struct tegra_dc *dc, 1925 struct drm_display_mode *mode) 1926 { 1927 unsigned int h_ref_to_sync = 1; 1928 unsigned int v_ref_to_sync = 1; 1929 unsigned long value; 1930 1931 if (!dc->soc->has_nvdisplay) { 1932 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1933 1934 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1935 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1936 } 1937 1938 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1939 ((mode->hsync_end - mode->hsync_start) << 0); 1940 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1941 1942 value = ((mode->vtotal - mode->vsync_end) << 16) | 1943 ((mode->htotal - mode->hsync_end) << 0); 1944 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1945 1946 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1947 ((mode->hsync_start - mode->hdisplay) << 0); 1948 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1949 1950 value = (mode->vdisplay << 16) | mode->hdisplay; 1951 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1952 1953 return 0; 1954 } 1955 1956 /** 1957 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1958 * state 1959 * @dc: display controller 1960 * @crtc_state: CRTC atomic state 1961 * @clk: parent clock for display controller 1962 * @pclk: pixel clock 1963 * @div: shift clock divider 1964 * 1965 * Returns: 1966 * 0 on success or a negative error-code on failure. 1967 */ 1968 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1969 struct drm_crtc_state *crtc_state, 1970 struct clk *clk, unsigned long pclk, 1971 unsigned int div) 1972 { 1973 struct tegra_dc_state *state = to_dc_state(crtc_state); 1974 1975 if (!clk_has_parent(dc->clk, clk)) 1976 return -EINVAL; 1977 1978 state->clk = clk; 1979 state->pclk = pclk; 1980 state->div = div; 1981 1982 return 0; 1983 } 1984 1985 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, 1986 struct tegra_dc_state *state) 1987 { 1988 unsigned long rate, pstate; 1989 struct dev_pm_opp *opp; 1990 int err; 1991 1992 if (!dc->has_opp_table) 1993 return; 1994 1995 /* calculate actual pixel clock rate which depends on internal divider */ 1996 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); 1997 1998 /* find suitable OPP for the rate */ 1999 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); 2000 2001 /* 2002 * Very high resolution modes may results in a clock rate that is 2003 * above the characterized maximum. In this case it's okay to fall 2004 * back to the characterized maximum. 2005 */ 2006 if (opp == ERR_PTR(-ERANGE)) 2007 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); 2008 2009 if (IS_ERR(opp)) { 2010 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", 2011 rate, opp); 2012 return; 2013 } 2014 2015 pstate = dev_pm_opp_get_required_pstate(opp, 0); 2016 dev_pm_opp_put(opp); 2017 2018 /* 2019 * The minimum core voltage depends on the pixel clock rate (which 2020 * depends on internal clock divider of the CRTC) and not on the 2021 * rate of the display controller clock. This is why we're not using 2022 * dev_pm_opp_set_rate() API and instead controlling the power domain 2023 * directly. 2024 */ 2025 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); 2026 if (err) 2027 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", 2028 pstate, err); 2029 } 2030 2031 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, 2032 struct tegra_dc_state *state) 2033 { 2034 int err; 2035 2036 err = clk_set_parent(dc->clk, state->clk); 2037 if (err < 0) 2038 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 2039 2040 /* 2041 * Outputs may not want to change the parent clock rate. This is only 2042 * relevant to Tegra20 where only a single display PLL is available. 2043 * Since that PLL would typically be used for HDMI, an internal LVDS 2044 * panel would need to be driven by some other clock such as PLL_P 2045 * which is shared with other peripherals. Changing the clock rate 2046 * should therefore be avoided. 2047 */ 2048 if (state->pclk > 0) { 2049 err = clk_set_rate(state->clk, state->pclk); 2050 if (err < 0) 2051 dev_err(dc->dev, 2052 "failed to set clock rate to %lu Hz\n", 2053 state->pclk); 2054 2055 err = clk_set_rate(dc->clk, state->pclk); 2056 if (err < 0) 2057 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 2058 dc->clk, state->pclk, err); 2059 } 2060 2061 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 2062 state->div); 2063 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 2064 2065 tegra_dc_update_voltage_state(dc, state); 2066 } 2067 2068 static void tegra_dc_stop(struct tegra_dc *dc) 2069 { 2070 u32 value; 2071 2072 /* stop the display controller */ 2073 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 2074 value &= ~DISP_CTRL_MODE_MASK; 2075 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 2076 2077 tegra_dc_commit(dc); 2078 } 2079 2080 static bool tegra_dc_idle(struct tegra_dc *dc) 2081 { 2082 u32 value; 2083 2084 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 2085 2086 return (value & DISP_CTRL_MODE_MASK) == 0; 2087 } 2088 2089 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 2090 { 2091 timeout = jiffies + msecs_to_jiffies(timeout); 2092 2093 while (time_before(jiffies, timeout)) { 2094 if (tegra_dc_idle(dc)) 2095 return 0; 2096 2097 usleep_range(1000, 2000); 2098 } 2099 2100 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 2101 return -ETIMEDOUT; 2102 } 2103 2104 static void 2105 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, 2106 struct drm_atomic_commit *state, 2107 bool prepare_bandwidth_transition) 2108 { 2109 const struct tegra_plane_state *old_tegra_state, *new_tegra_state; 2110 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw; 2111 const struct drm_plane_state *old_plane_state; 2112 const struct drm_crtc_state *old_crtc_state; 2113 struct tegra_dc_window window, old_window; 2114 struct tegra_dc *dc = to_tegra_dc(crtc); 2115 struct tegra_plane *tegra; 2116 struct drm_plane *plane; 2117 2118 if (dc->soc->has_nvdisplay) 2119 return; 2120 2121 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 2122 2123 if (!crtc->state->active) { 2124 if (!old_crtc_state->active) 2125 return; 2126 2127 /* 2128 * When CRTC is disabled on DPMS, the state of attached planes 2129 * is kept unchanged. Hence we need to enforce removal of the 2130 * bandwidths from the ICC paths. 2131 */ 2132 drm_atomic_crtc_for_each_plane(plane, crtc) { 2133 tegra = to_tegra_plane(plane); 2134 2135 icc_set_bw(tegra->icc_mem, 0, 0); 2136 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2137 } 2138 2139 return; 2140 } 2141 2142 for_each_old_plane_in_state(old_crtc_state->state, plane, 2143 old_plane_state, i) { 2144 old_tegra_state = to_const_tegra_plane_state(old_plane_state); 2145 new_tegra_state = to_const_tegra_plane_state(plane->state); 2146 tegra = to_tegra_plane(plane); 2147 2148 /* 2149 * We're iterating over the global atomic state and it contains 2150 * planes from another CRTC, hence we need to filter out the 2151 * planes unrelated to this CRTC. 2152 */ 2153 if (tegra->dc != dc) 2154 continue; 2155 2156 new_avg_bw = new_tegra_state->avg_memory_bandwidth; 2157 old_avg_bw = old_tegra_state->avg_memory_bandwidth; 2158 2159 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; 2160 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; 2161 2162 /* 2163 * See the comment related to !crtc->state->active above, 2164 * which explains why bandwidths need to be updated when 2165 * CRTC is turning ON. 2166 */ 2167 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw && 2168 old_crtc_state->active) 2169 continue; 2170 2171 window.src.h = drm_rect_height(&plane->state->src) >> 16; 2172 window.dst.h = drm_rect_height(&plane->state->dst); 2173 2174 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; 2175 old_window.dst.h = drm_rect_height(&old_plane_state->dst); 2176 2177 /* 2178 * During the preparation phase (atomic_begin), the memory 2179 * freq should go high before the DC changes are committed 2180 * if bandwidth requirement goes up, otherwise memory freq 2181 * should to stay high if BW requirement goes down. The 2182 * opposite applies to the completion phase (post_commit). 2183 */ 2184 if (prepare_bandwidth_transition) { 2185 new_avg_bw = max(old_avg_bw, new_avg_bw); 2186 new_peak_bw = max(old_peak_bw, new_peak_bw); 2187 2188 if (tegra_plane_use_vertical_filtering(tegra, &old_window)) 2189 window = old_window; 2190 } 2191 2192 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); 2193 2194 if (tegra_plane_use_vertical_filtering(tegra, &window)) 2195 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); 2196 else 2197 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2198 } 2199 } 2200 2201 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 2202 struct drm_atomic_commit *state) 2203 { 2204 struct tegra_dc *dc = to_tegra_dc(crtc); 2205 u32 value; 2206 int err; 2207 2208 if (!tegra_dc_idle(dc)) { 2209 tegra_dc_stop(dc); 2210 2211 /* 2212 * Ignore the return value, there isn't anything useful to do 2213 * in case this fails. 2214 */ 2215 tegra_dc_wait_idle(dc, 100); 2216 } 2217 2218 /* 2219 * This should really be part of the RGB encoder driver, but clearing 2220 * these bits has the side-effect of stopping the display controller. 2221 * When that happens no VBLANK interrupts will be raised. At the same 2222 * time the encoder is disabled before the display controller, so the 2223 * above code is always going to timeout waiting for the controller 2224 * to go idle. 2225 * 2226 * Given the close coupling between the RGB encoder and the display 2227 * controller doing it here is still kind of okay. None of the other 2228 * encoder drivers require these bits to be cleared. 2229 * 2230 * XXX: Perhaps given that the display controller is switched off at 2231 * this point anyway maybe clearing these bits isn't even useful for 2232 * the RGB encoder? 2233 */ 2234 if (dc->rgb) { 2235 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2236 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2237 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 2238 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2239 } 2240 2241 tegra_dc_stats_reset(&dc->stats); 2242 drm_crtc_vblank_off(crtc); 2243 2244 spin_lock_irq(&crtc->dev->event_lock); 2245 2246 if (crtc->state->event) { 2247 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2248 crtc->state->event = NULL; 2249 } 2250 2251 spin_unlock_irq(&crtc->dev->event_lock); 2252 2253 err = host1x_client_suspend(&dc->client); 2254 if (err < 0) 2255 dev_err(dc->dev, "failed to suspend: %d\n", err); 2256 2257 if (dc->has_opp_table) { 2258 err = dev_pm_genpd_set_performance_state(dc->dev, 0); 2259 if (err) 2260 dev_err(dc->dev, 2261 "failed to clear power domain state: %d\n", err); 2262 } 2263 } 2264 2265 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 2266 struct drm_atomic_commit *state) 2267 { 2268 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 2269 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); 2270 struct tegra_dc *dc = to_tegra_dc(crtc); 2271 u32 value; 2272 int err; 2273 2274 /* apply PLL changes */ 2275 tegra_dc_set_clock_rate(dc, crtc_state); 2276 2277 err = host1x_client_resume(&dc->client); 2278 if (err < 0) { 2279 dev_err(dc->dev, "failed to resume: %d\n", err); 2280 return; 2281 } 2282 2283 /* initialize display controller */ 2284 if (dc->syncpt) { 2285 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 2286 2287 if (dc->soc->has_nvdisplay) 2288 enable = 1 << 31; 2289 else 2290 enable = 1 << 8; 2291 2292 value = SYNCPT_CNTRL_NO_STALL; 2293 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 2294 2295 value = enable | syncpt; 2296 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 2297 } 2298 2299 if (dc->soc->has_nvdisplay) { 2300 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2301 DSC_OBUF_UF_INT; 2302 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2303 2304 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2305 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 2306 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 2307 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 2308 VBLANK_INT | FRAME_END_INT; 2309 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2310 2311 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 2312 FRAME_END_INT; 2313 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2314 2315 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 2316 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2317 2318 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 2319 } else { 2320 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2321 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2322 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2323 2324 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2325 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2326 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2327 2328 /* initialize timer */ 2329 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 2330 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 2331 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 2332 2333 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 2334 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 2335 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 2336 2337 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2338 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2339 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2340 2341 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2342 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2343 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2344 } 2345 2346 if (dc->soc->supports_background_color) 2347 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 2348 else 2349 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 2350 2351 /* apply pixel clock changes */ 2352 if (!dc->soc->has_nvdisplay) { 2353 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1; 2354 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 2355 } 2356 2357 /* program display mode */ 2358 tegra_dc_set_timings(dc, mode); 2359 2360 /* interlacing isn't supported yet, so disable it */ 2361 if (dc->soc->supports_interlacing) { 2362 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 2363 value &= ~INTERLACE_ENABLE; 2364 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 2365 } 2366 2367 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 2368 value &= ~DISP_CTRL_MODE_MASK; 2369 value |= DISP_CTRL_MODE_C_DISPLAY; 2370 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 2371 2372 if (!dc->soc->has_nvdisplay) { 2373 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2374 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2375 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 2376 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2377 } 2378 2379 /* enable underflow reporting and display red for missing pixels */ 2380 if (dc->soc->has_nvdisplay) { 2381 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 2382 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 2383 } 2384 2385 if (dc->rgb) { 2386 /* XXX: parameterize? */ 2387 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; 2388 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); 2389 } 2390 2391 tegra_dc_commit(dc); 2392 2393 drm_crtc_vblank_on(crtc); 2394 } 2395 2396 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 2397 struct drm_atomic_commit *state) 2398 { 2399 unsigned long flags; 2400 2401 tegra_crtc_update_memory_bandwidth(crtc, state, true); 2402 2403 if (crtc->state->event) { 2404 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2405 2406 if (drm_crtc_vblank_get(crtc) != 0) 2407 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2408 else 2409 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 2410 2411 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2412 2413 crtc->state->event = NULL; 2414 } 2415 } 2416 2417 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 2418 struct drm_atomic_commit *state) 2419 { 2420 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 2421 crtc); 2422 struct tegra_dc_state *dc_state = to_dc_state(crtc_state); 2423 struct tegra_dc *dc = to_tegra_dc(crtc); 2424 u32 value; 2425 2426 value = dc_state->planes << 8 | GENERAL_UPDATE; 2427 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2428 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2429 2430 value = dc_state->planes | GENERAL_ACT_REQ; 2431 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2432 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2433 } 2434 2435 static bool tegra_plane_is_cursor(const struct drm_plane_state *state) 2436 { 2437 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; 2438 const struct drm_format_info *fmt = state->fb->format; 2439 unsigned int src_w = drm_rect_width(&state->src) >> 16; 2440 unsigned int dst_w = drm_rect_width(&state->dst); 2441 2442 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) 2443 return false; 2444 2445 if (soc->supports_cursor) 2446 return true; 2447 2448 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) 2449 return false; 2450 2451 return true; 2452 } 2453 2454 static unsigned long 2455 tegra_plane_overlap_mask(struct drm_crtc_state *state, 2456 const struct drm_plane_state *plane_state) 2457 { 2458 const struct drm_plane_state *other_state; 2459 const struct tegra_plane *tegra; 2460 unsigned long overlap_mask = 0; 2461 struct drm_plane *plane; 2462 struct drm_rect rect; 2463 2464 if (!plane_state->visible || !plane_state->fb) 2465 return 0; 2466 2467 /* 2468 * Data-prefetch FIFO will easily help to overcome temporal memory 2469 * pressure if other plane overlaps with the cursor plane. 2470 */ 2471 if (tegra_plane_is_cursor(plane_state)) 2472 return 0; 2473 2474 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { 2475 rect = plane_state->dst; 2476 2477 tegra = to_tegra_plane(other_state->plane); 2478 2479 if (!other_state->visible || !other_state->fb) 2480 continue; 2481 2482 /* 2483 * Ignore cursor plane overlaps because it's not practical to 2484 * assume that it contributes to the bandwidth in overlapping 2485 * area if window width is small. 2486 */ 2487 if (tegra_plane_is_cursor(other_state)) 2488 continue; 2489 2490 if (drm_rect_intersect(&rect, &other_state->dst)) 2491 overlap_mask |= BIT(tegra->index); 2492 } 2493 2494 return overlap_mask; 2495 } 2496 2497 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, 2498 struct drm_atomic_commit *state) 2499 { 2500 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; 2501 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; 2502 bool all_planes_overlap_simultaneously = true; 2503 const struct tegra_plane_state *tegra_state; 2504 const struct drm_plane_state *plane_state; 2505 struct tegra_dc *dc = to_tegra_dc(crtc); 2506 struct drm_crtc_state *new_state; 2507 struct tegra_plane *tegra; 2508 struct drm_plane *plane; 2509 2510 /* 2511 * The nv-display uses shared planes. The algorithm below assumes 2512 * maximum 3 planes per-CRTC, this assumption isn't applicable to 2513 * the nv-display. Note that T124 support has additional windows, 2514 * but currently they aren't supported by the driver. 2515 */ 2516 if (dc->soc->has_nvdisplay) 2517 return 0; 2518 2519 new_state = drm_atomic_get_new_crtc_state(state, crtc); 2520 2521 /* 2522 * For overlapping planes pixel's data is fetched for each plane at 2523 * the same time, hence bandwidths are accumulated in this case. 2524 * This needs to be taken into account for calculating total bandwidth 2525 * consumed by all planes. 2526 * 2527 * Here we get the overlapping state of each plane, which is a 2528 * bitmask of plane indices telling with what planes there is an 2529 * overlap. Note that bitmask[plane] includes BIT(plane) in order 2530 * to make further code nicer and simpler. 2531 */ 2532 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2533 tegra_state = to_const_tegra_plane_state(plane_state); 2534 tegra = to_tegra_plane(plane); 2535 2536 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) 2537 return -EINVAL; 2538 2539 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; 2540 mask = tegra_plane_overlap_mask(new_state, plane_state); 2541 overlap_mask[tegra->index] = mask; 2542 2543 if (hweight_long(mask) != 3) 2544 all_planes_overlap_simultaneously = false; 2545 } 2546 2547 /* 2548 * Then we calculate maximum bandwidth of each plane state. 2549 * The bandwidth includes the plane BW + BW of the "simultaneously" 2550 * overlapping planes, where "simultaneously" means areas where DC 2551 * fetches from the planes simultaneously during of scan-out process. 2552 * 2553 * For example, if plane A overlaps with planes B and C, but B and C 2554 * don't overlap, then the peak bandwidth will be either in area where 2555 * A-and-B or A-and-C planes overlap. 2556 * 2557 * The plane_peak_bw[] contains peak memory bandwidth values of 2558 * each plane, this information is needed by interconnect provider 2559 * in order to set up latency allowance based on the peak BW, see 2560 * tegra_crtc_update_memory_bandwidth(). 2561 */ 2562 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2563 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0; 2564 2565 /* 2566 * Note that plane's atomic check doesn't touch the 2567 * total_peak_memory_bandwidth of enabled plane, hence the 2568 * current state contains the old bandwidth state from the 2569 * previous CRTC commit. 2570 */ 2571 tegra_state = to_const_tegra_plane_state(plane_state); 2572 tegra = to_tegra_plane(plane); 2573 2574 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { 2575 if (i == tegra->index) 2576 continue; 2577 2578 if (all_planes_overlap_simultaneously) 2579 overlap_bw += plane_peak_bw[i]; 2580 else 2581 overlap_bw = max(overlap_bw, plane_peak_bw[i]); 2582 } 2583 2584 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; 2585 old_peak_bw = tegra_state->total_peak_memory_bandwidth; 2586 2587 /* 2588 * If plane's peak bandwidth changed (for example plane isn't 2589 * overlapped anymore) and plane isn't in the atomic state, 2590 * then add plane to the state in order to have the bandwidth 2591 * updated. 2592 */ 2593 if (old_peak_bw != new_peak_bw) { 2594 struct tegra_plane_state *new_tegra_state; 2595 struct drm_plane_state *new_plane_state; 2596 2597 new_plane_state = drm_atomic_get_plane_state(state, plane); 2598 if (IS_ERR(new_plane_state)) 2599 return PTR_ERR(new_plane_state); 2600 2601 new_tegra_state = to_tegra_plane_state(new_plane_state); 2602 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; 2603 } 2604 } 2605 2606 return 0; 2607 } 2608 2609 static int tegra_crtc_atomic_check(struct drm_crtc *crtc, 2610 struct drm_atomic_commit *state) 2611 { 2612 int err; 2613 2614 err = tegra_crtc_calculate_memory_bandwidth(crtc, state); 2615 if (err) 2616 return err; 2617 2618 return 0; 2619 } 2620 2621 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 2622 struct drm_atomic_commit *state) 2623 { 2624 /* 2625 * Display bandwidth is allowed to go down only once hardware state 2626 * is known to be armed, i.e. state was committed and VBLANK event 2627 * received. 2628 */ 2629 tegra_crtc_update_memory_bandwidth(crtc, state, false); 2630 } 2631 2632 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 2633 .atomic_check = tegra_crtc_atomic_check, 2634 .atomic_begin = tegra_crtc_atomic_begin, 2635 .atomic_flush = tegra_crtc_atomic_flush, 2636 .atomic_enable = tegra_crtc_atomic_enable, 2637 .atomic_disable = tegra_crtc_atomic_disable, 2638 }; 2639 2640 static irqreturn_t tegra_dc_irq(int irq, void *data) 2641 { 2642 struct tegra_dc *dc = data; 2643 unsigned long status; 2644 2645 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 2646 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 2647 2648 if (status & FRAME_END_INT) { 2649 /* 2650 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 2651 */ 2652 dc->stats.frames_total++; 2653 dc->stats.frames++; 2654 } 2655 2656 if (status & VBLANK_INT) { 2657 /* 2658 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 2659 */ 2660 drm_crtc_handle_vblank(&dc->base); 2661 dc->stats.vblank_total++; 2662 dc->stats.vblank++; 2663 } 2664 2665 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 2666 /* 2667 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 2668 */ 2669 dc->stats.underflow_total++; 2670 dc->stats.underflow++; 2671 } 2672 2673 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 2674 /* 2675 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 2676 */ 2677 dc->stats.overflow_total++; 2678 dc->stats.overflow++; 2679 } 2680 2681 if (status & HEAD_UF_INT) { 2682 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 2683 dc->stats.underflow_total++; 2684 dc->stats.underflow++; 2685 } 2686 2687 return IRQ_HANDLED; 2688 } 2689 2690 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 2691 { 2692 unsigned int i; 2693 2694 if (!dc->soc->wgrps) 2695 return true; 2696 2697 for (i = 0; i < dc->soc->num_wgrps; i++) { 2698 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 2699 2700 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 2701 return true; 2702 } 2703 2704 return false; 2705 } 2706 2707 static int tegra_dc_early_init(struct host1x_client *client) 2708 { 2709 struct drm_device *drm = dev_get_drvdata(client->host); 2710 struct tegra_drm *tegra = drm->dev_private; 2711 2712 tegra->num_crtcs++; 2713 2714 return 0; 2715 } 2716 2717 static int tegra_dc_init(struct host1x_client *client) 2718 { 2719 struct drm_device *drm = dev_get_drvdata(client->host); 2720 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 2721 struct tegra_dc *dc = host1x_client_to_dc(client); 2722 struct tegra_drm *tegra = drm->dev_private; 2723 struct drm_plane *primary = NULL; 2724 struct drm_plane *cursor = NULL; 2725 int err; 2726 2727 /* 2728 * DC has been reset by now, so VBLANK syncpoint can be released 2729 * for general use. 2730 */ 2731 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); 2732 2733 /* 2734 * XXX do not register DCs with no window groups because we cannot 2735 * assign a primary plane to them, which in turn will cause KMS to 2736 * crash. 2737 */ 2738 if (!tegra_dc_has_window_groups(dc)) 2739 return 0; 2740 2741 /* 2742 * Set the display hub as the host1x client parent for the display 2743 * controller. This is needed for the runtime reference counting that 2744 * ensures the display hub is always powered when any of the display 2745 * controllers are. 2746 */ 2747 if (dc->soc->has_nvdisplay) 2748 client->parent = &tegra->hub->client; 2749 2750 dc->syncpt = host1x_syncpt_request(client, flags); 2751 if (!dc->syncpt) 2752 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2753 2754 err = host1x_client_iommu_attach(client); 2755 if (err < 0 && err != -ENODEV) { 2756 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2757 return err; 2758 } 2759 2760 if (dc->soc->wgrps) 2761 primary = tegra_dc_add_shared_planes(drm, dc); 2762 else 2763 primary = tegra_dc_add_planes(drm, dc); 2764 2765 if (IS_ERR(primary)) { 2766 err = PTR_ERR(primary); 2767 goto cleanup; 2768 } 2769 2770 if (dc->soc->supports_cursor) { 2771 cursor = tegra_dc_cursor_plane_create(drm, dc); 2772 if (IS_ERR(cursor)) { 2773 err = PTR_ERR(cursor); 2774 goto cleanup; 2775 } 2776 } else { 2777 /* dedicate one overlay to mouse cursor */ 2778 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2779 if (IS_ERR(cursor)) { 2780 err = PTR_ERR(cursor); 2781 goto cleanup; 2782 } 2783 } 2784 2785 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2786 &tegra_crtc_funcs, NULL); 2787 if (err < 0) 2788 goto cleanup; 2789 2790 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2791 2792 /* 2793 * Keep track of the minimum pitch alignment across all display 2794 * controllers. 2795 */ 2796 if (dc->soc->pitch_align > tegra->pitch_align) 2797 tegra->pitch_align = dc->soc->pitch_align; 2798 2799 /* track maximum resolution */ 2800 if (dc->soc->has_nvdisplay) 2801 drm->mode_config.max_width = drm->mode_config.max_height = 16384; 2802 else 2803 drm->mode_config.max_width = drm->mode_config.max_height = 4096; 2804 2805 err = tegra_dc_rgb_init(drm, dc); 2806 if (err < 0 && err != -ENODEV) { 2807 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2808 goto cleanup; 2809 } 2810 2811 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2812 dev_name(dc->dev), dc); 2813 if (err < 0) { 2814 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2815 err); 2816 goto cleanup; 2817 } 2818 2819 /* 2820 * Inherit the DMA parameters (such as maximum segment size) from the 2821 * parent host1x device. 2822 */ 2823 client->dev->dma_parms = client->host->dma_parms; 2824 2825 return 0; 2826 2827 cleanup: 2828 if (!IS_ERR_OR_NULL(cursor)) 2829 drm_plane_cleanup(cursor); 2830 2831 if (!IS_ERR(primary)) 2832 drm_plane_cleanup(primary); 2833 2834 host1x_client_iommu_detach(client); 2835 host1x_syncpt_put(dc->syncpt); 2836 2837 return err; 2838 } 2839 2840 static int tegra_dc_exit(struct host1x_client *client) 2841 { 2842 struct tegra_dc *dc = host1x_client_to_dc(client); 2843 int err; 2844 2845 if (!tegra_dc_has_window_groups(dc)) 2846 return 0; 2847 2848 /* avoid a dangling pointer just in case this disappears */ 2849 client->dev->dma_parms = NULL; 2850 2851 devm_free_irq(dc->dev, dc->irq, dc); 2852 2853 err = tegra_dc_rgb_exit(dc); 2854 if (err) { 2855 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2856 return err; 2857 } 2858 2859 host1x_client_iommu_detach(client); 2860 host1x_syncpt_put(dc->syncpt); 2861 2862 return 0; 2863 } 2864 2865 static int tegra_dc_late_exit(struct host1x_client *client) 2866 { 2867 struct drm_device *drm = dev_get_drvdata(client->host); 2868 struct tegra_drm *tegra = drm->dev_private; 2869 2870 tegra->num_crtcs--; 2871 2872 return 0; 2873 } 2874 2875 static int tegra_dc_runtime_suspend(struct host1x_client *client) 2876 { 2877 struct tegra_dc *dc = host1x_client_to_dc(client); 2878 struct device *dev = client->dev; 2879 int err; 2880 2881 err = reset_control_assert(dc->rst); 2882 if (err < 0) { 2883 dev_err(dev, "failed to assert reset: %d\n", err); 2884 return err; 2885 } 2886 2887 if (dc->soc->has_powergate) 2888 tegra_pmc_powergate_power_off(dc->pmc, dc->powergate); 2889 2890 clk_disable_unprepare(dc->clk); 2891 pm_runtime_put_sync(dev); 2892 2893 return 0; 2894 } 2895 2896 static int tegra_dc_runtime_resume(struct host1x_client *client) 2897 { 2898 struct tegra_dc *dc = host1x_client_to_dc(client); 2899 struct device *dev = client->dev; 2900 int err; 2901 2902 err = pm_runtime_resume_and_get(dev); 2903 if (err < 0) { 2904 dev_err(dev, "failed to get runtime PM: %d\n", err); 2905 return err; 2906 } 2907 2908 if (dc->soc->has_powergate) { 2909 err = tegra_pmc_powergate_sequence_power_up(dc->pmc, 2910 dc->powergate, 2911 dc->clk, dc->rst); 2912 if (err < 0) { 2913 dev_err(dev, "failed to power partition: %d\n", err); 2914 goto put_rpm; 2915 } 2916 } else { 2917 err = clk_prepare_enable(dc->clk); 2918 if (err < 0) { 2919 dev_err(dev, "failed to enable clock: %d\n", err); 2920 goto put_rpm; 2921 } 2922 2923 err = reset_control_deassert(dc->rst); 2924 if (err < 0) { 2925 dev_err(dev, "failed to deassert reset: %d\n", err); 2926 goto disable_clk; 2927 } 2928 } 2929 2930 return 0; 2931 2932 disable_clk: 2933 clk_disable_unprepare(dc->clk); 2934 put_rpm: 2935 pm_runtime_put_sync(dev); 2936 return err; 2937 } 2938 2939 static const struct host1x_client_ops dc_client_ops = { 2940 .early_init = tegra_dc_early_init, 2941 .init = tegra_dc_init, 2942 .exit = tegra_dc_exit, 2943 .late_exit = tegra_dc_late_exit, 2944 .suspend = tegra_dc_runtime_suspend, 2945 .resume = tegra_dc_runtime_resume, 2946 }; 2947 2948 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2949 .supports_background_color = false, 2950 .supports_interlacing = false, 2951 .supports_cursor = false, 2952 .supports_block_linear = false, 2953 .supports_sector_layout = false, 2954 .has_legacy_blending = true, 2955 .pitch_align = 8, 2956 .has_powergate = false, 2957 .coupled_pm = true, 2958 .has_nvdisplay = false, 2959 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2960 .primary_formats = tegra20_primary_formats, 2961 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2962 .overlay_formats = tegra20_overlay_formats, 2963 .modifiers = tegra20_modifiers, 2964 .has_win_a_without_filters = true, 2965 .has_win_b_vfilter_mem_client = true, 2966 .has_win_c_without_vert_filter = true, 2967 .plane_tiled_memory_bandwidth_x2 = false, 2968 .has_pll_d2_out0 = false, 2969 }; 2970 2971 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2972 .supports_background_color = false, 2973 .supports_interlacing = false, 2974 .supports_cursor = false, 2975 .supports_block_linear = false, 2976 .supports_sector_layout = false, 2977 .has_legacy_blending = true, 2978 .pitch_align = 8, 2979 .has_powergate = false, 2980 .coupled_pm = false, 2981 .has_nvdisplay = false, 2982 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2983 .primary_formats = tegra20_primary_formats, 2984 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2985 .overlay_formats = tegra20_overlay_formats, 2986 .modifiers = tegra20_modifiers, 2987 .has_win_a_without_filters = false, 2988 .has_win_b_vfilter_mem_client = true, 2989 .has_win_c_without_vert_filter = false, 2990 .plane_tiled_memory_bandwidth_x2 = true, 2991 .has_pll_d2_out0 = true, 2992 }; 2993 2994 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2995 .supports_background_color = false, 2996 .supports_interlacing = false, 2997 .supports_cursor = false, 2998 .supports_block_linear = false, 2999 .supports_sector_layout = false, 3000 .has_legacy_blending = true, 3001 .pitch_align = 64, 3002 .has_powergate = true, 3003 .coupled_pm = false, 3004 .has_nvdisplay = false, 3005 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 3006 .primary_formats = tegra114_primary_formats, 3007 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 3008 .overlay_formats = tegra114_overlay_formats, 3009 .modifiers = tegra20_modifiers, 3010 .has_win_a_without_filters = false, 3011 .has_win_b_vfilter_mem_client = false, 3012 .has_win_c_without_vert_filter = false, 3013 .plane_tiled_memory_bandwidth_x2 = true, 3014 .has_pll_d2_out0 = true, 3015 }; 3016 3017 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 3018 .supports_background_color = true, 3019 .supports_interlacing = true, 3020 .supports_cursor = true, 3021 .supports_block_linear = true, 3022 .supports_sector_layout = false, 3023 .has_legacy_blending = false, 3024 .pitch_align = 64, 3025 .has_powergate = true, 3026 .coupled_pm = false, 3027 .has_nvdisplay = false, 3028 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 3029 .primary_formats = tegra124_primary_formats, 3030 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 3031 .overlay_formats = tegra124_overlay_formats, 3032 .modifiers = tegra124_modifiers, 3033 .has_win_a_without_filters = false, 3034 .has_win_b_vfilter_mem_client = false, 3035 .has_win_c_without_vert_filter = false, 3036 .plane_tiled_memory_bandwidth_x2 = false, 3037 .has_pll_d2_out0 = true, 3038 }; 3039 3040 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 3041 .supports_background_color = true, 3042 .supports_interlacing = true, 3043 .supports_cursor = true, 3044 .supports_block_linear = true, 3045 .supports_sector_layout = false, 3046 .has_legacy_blending = false, 3047 .pitch_align = 64, 3048 .has_powergate = true, 3049 .coupled_pm = false, 3050 .has_nvdisplay = false, 3051 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 3052 .primary_formats = tegra114_primary_formats, 3053 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 3054 .overlay_formats = tegra114_overlay_formats, 3055 .modifiers = tegra124_modifiers, 3056 .has_win_a_without_filters = false, 3057 .has_win_b_vfilter_mem_client = false, 3058 .has_win_c_without_vert_filter = false, 3059 .plane_tiled_memory_bandwidth_x2 = false, 3060 .has_pll_d2_out0 = true, 3061 }; 3062 3063 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 3064 { 3065 .index = 0, 3066 .dc = 0, 3067 .windows = (const unsigned int[]) { 0 }, 3068 .num_windows = 1, 3069 }, { 3070 .index = 1, 3071 .dc = 1, 3072 .windows = (const unsigned int[]) { 1 }, 3073 .num_windows = 1, 3074 }, { 3075 .index = 2, 3076 .dc = 1, 3077 .windows = (const unsigned int[]) { 2 }, 3078 .num_windows = 1, 3079 }, { 3080 .index = 3, 3081 .dc = 2, 3082 .windows = (const unsigned int[]) { 3 }, 3083 .num_windows = 1, 3084 }, { 3085 .index = 4, 3086 .dc = 2, 3087 .windows = (const unsigned int[]) { 4 }, 3088 .num_windows = 1, 3089 }, { 3090 .index = 5, 3091 .dc = 2, 3092 .windows = (const unsigned int[]) { 5 }, 3093 .num_windows = 1, 3094 }, 3095 }; 3096 3097 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 3098 .supports_background_color = true, 3099 .supports_interlacing = true, 3100 .supports_cursor = true, 3101 .supports_block_linear = true, 3102 .supports_sector_layout = false, 3103 .has_legacy_blending = false, 3104 .pitch_align = 64, 3105 .has_powergate = false, 3106 .coupled_pm = false, 3107 .has_nvdisplay = true, 3108 .wgrps = tegra186_dc_wgrps, 3109 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 3110 .plane_tiled_memory_bandwidth_x2 = false, 3111 .has_pll_d2_out0 = false, 3112 }; 3113 3114 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 3115 { 3116 .index = 0, 3117 .dc = 0, 3118 .windows = (const unsigned int[]) { 0 }, 3119 .num_windows = 1, 3120 }, { 3121 .index = 1, 3122 .dc = 1, 3123 .windows = (const unsigned int[]) { 1 }, 3124 .num_windows = 1, 3125 }, { 3126 .index = 2, 3127 .dc = 1, 3128 .windows = (const unsigned int[]) { 2 }, 3129 .num_windows = 1, 3130 }, { 3131 .index = 3, 3132 .dc = 2, 3133 .windows = (const unsigned int[]) { 3 }, 3134 .num_windows = 1, 3135 }, { 3136 .index = 4, 3137 .dc = 2, 3138 .windows = (const unsigned int[]) { 4 }, 3139 .num_windows = 1, 3140 }, { 3141 .index = 5, 3142 .dc = 2, 3143 .windows = (const unsigned int[]) { 5 }, 3144 .num_windows = 1, 3145 }, 3146 }; 3147 3148 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 3149 .supports_background_color = true, 3150 .supports_interlacing = true, 3151 .supports_cursor = true, 3152 .supports_block_linear = true, 3153 .supports_sector_layout = true, 3154 .has_legacy_blending = false, 3155 .pitch_align = 64, 3156 .has_powergate = false, 3157 .coupled_pm = false, 3158 .has_nvdisplay = true, 3159 .wgrps = tegra194_dc_wgrps, 3160 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 3161 .plane_tiled_memory_bandwidth_x2 = false, 3162 .has_pll_d2_out0 = false, 3163 }; 3164 3165 static const struct of_device_id tegra_dc_of_match[] = { 3166 { 3167 .compatible = "nvidia,tegra194-dc", 3168 .data = &tegra194_dc_soc_info, 3169 }, { 3170 .compatible = "nvidia,tegra186-dc", 3171 .data = &tegra186_dc_soc_info, 3172 }, { 3173 .compatible = "nvidia,tegra210-dc", 3174 .data = &tegra210_dc_soc_info, 3175 }, { 3176 .compatible = "nvidia,tegra124-dc", 3177 .data = &tegra124_dc_soc_info, 3178 }, { 3179 .compatible = "nvidia,tegra114-dc", 3180 .data = &tegra114_dc_soc_info, 3181 }, { 3182 .compatible = "nvidia,tegra30-dc", 3183 .data = &tegra30_dc_soc_info, 3184 }, { 3185 .compatible = "nvidia,tegra20-dc", 3186 .data = &tegra20_dc_soc_info, 3187 }, { 3188 /* sentinel */ 3189 } 3190 }; 3191 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 3192 3193 static int tegra_dc_parse_dt(struct tegra_dc *dc) 3194 { 3195 struct device_node *np; 3196 u32 value = 0; 3197 int err; 3198 3199 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 3200 if (err < 0) { 3201 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 3202 3203 /* 3204 * If the nvidia,head property isn't present, try to find the 3205 * correct head number by looking up the position of this 3206 * display controller's node within the device tree. Assuming 3207 * that the nodes are ordered properly in the DTS file and 3208 * that the translation into a flattened device tree blob 3209 * preserves that ordering this will actually yield the right 3210 * head number. 3211 * 3212 * If those assumptions don't hold, this will still work for 3213 * cases where only a single display controller is used. 3214 */ 3215 for_each_matching_node(np, tegra_dc_of_match) { 3216 if (np == dc->dev->of_node) { 3217 of_node_put(np); 3218 break; 3219 } 3220 3221 value++; 3222 } 3223 } 3224 3225 dc->pipe = value; 3226 3227 return 0; 3228 } 3229 3230 static int tegra_dc_match_by_pipe(struct device *dev, const void *data) 3231 { 3232 struct tegra_dc *dc = dev_get_drvdata(dev); 3233 unsigned int pipe = (unsigned long)(void *)data; 3234 3235 return dc->pipe == pipe; 3236 } 3237 3238 static int tegra_dc_couple(struct tegra_dc *dc) 3239 { 3240 /* 3241 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 3242 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 3243 * POWER_CONTROL registers during CRTC enabling. 3244 */ 3245 if (dc->soc->coupled_pm && dc->pipe == 1) { 3246 struct device *companion; 3247 struct tegra_dc *parent; 3248 3249 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, 3250 tegra_dc_match_by_pipe); 3251 if (!companion) 3252 return -EPROBE_DEFER; 3253 3254 parent = dev_get_drvdata(companion); 3255 dc->client.parent = &parent->client; 3256 3257 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 3258 put_device(companion); 3259 } 3260 3261 return 0; 3262 } 3263 3264 static int tegra_dc_init_opp_table(struct tegra_dc *dc) 3265 { 3266 struct tegra_core_opp_params opp_params = {}; 3267 int err; 3268 3269 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); 3270 if (err && err != -ENODEV) 3271 return err; 3272 3273 if (err) 3274 dc->has_opp_table = false; 3275 else 3276 dc->has_opp_table = true; 3277 3278 return 0; 3279 } 3280 3281 static int tegra_dc_probe(struct platform_device *pdev) 3282 { 3283 u64 dma_mask = dma_get_mask(pdev->dev.parent); 3284 struct tegra_dc *dc; 3285 int err; 3286 3287 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); 3288 if (err < 0) { 3289 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 3290 return err; 3291 } 3292 3293 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 3294 if (!dc) 3295 return -ENOMEM; 3296 3297 dc->soc = of_device_get_match_data(&pdev->dev); 3298 3299 INIT_LIST_HEAD(&dc->list); 3300 dc->dev = &pdev->dev; 3301 3302 err = tegra_dc_parse_dt(dc); 3303 if (err < 0) 3304 return err; 3305 3306 err = tegra_dc_couple(dc); 3307 if (err < 0) 3308 return err; 3309 3310 dc->clk = devm_clk_get(&pdev->dev, NULL); 3311 if (IS_ERR(dc->clk)) { 3312 dev_err(&pdev->dev, "failed to get clock\n"); 3313 return PTR_ERR(dc->clk); 3314 } 3315 3316 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 3317 if (IS_ERR(dc->rst)) { 3318 dev_err(&pdev->dev, "failed to get reset\n"); 3319 return PTR_ERR(dc->rst); 3320 } 3321 3322 /* assert reset and disable clock */ 3323 err = clk_prepare_enable(dc->clk); 3324 if (err < 0) 3325 return err; 3326 3327 usleep_range(2000, 4000); 3328 3329 err = reset_control_assert(dc->rst); 3330 if (err < 0) { 3331 clk_disable_unprepare(dc->clk); 3332 return err; 3333 } 3334 3335 usleep_range(2000, 4000); 3336 3337 clk_disable_unprepare(dc->clk); 3338 3339 if (dc->soc->has_powergate) { 3340 dc->pmc = devm_tegra_pmc_get(dc->dev); 3341 if (IS_ERR(dc->pmc)) 3342 return dev_err_probe(dc->dev, PTR_ERR(dc->pmc), 3343 "failed to get PMC\n"); 3344 3345 if (dc->pipe == 0) 3346 dc->powergate = TEGRA_POWERGATE_DIS; 3347 else 3348 dc->powergate = TEGRA_POWERGATE_DISB; 3349 3350 tegra_pmc_powergate_power_off(dc->pmc, dc->powergate); 3351 } 3352 3353 err = tegra_dc_init_opp_table(dc); 3354 if (err < 0) 3355 return err; 3356 3357 dc->regs = devm_platform_ioremap_resource(pdev, 0); 3358 if (IS_ERR(dc->regs)) 3359 return PTR_ERR(dc->regs); 3360 3361 dc->irq = platform_get_irq(pdev, 0); 3362 if (dc->irq < 0) 3363 return -ENXIO; 3364 3365 if (dc->soc->has_nvdisplay) { 3366 unsigned int i; 3367 u64 r; 3368 3369 dc->cmu_output_lut = 3370 dmam_alloc_coherent(dc->dev, ARRAY_SIZE(default_srgb_lut) * sizeof(u64), 3371 &dc->cmu_output_lut_phys, GFP_KERNEL); 3372 3373 if (!dc->cmu_output_lut) { 3374 dev_err(dc->dev, "failed to allocate lut for cmu\n"); 3375 return -ENOMEM; 3376 } 3377 3378 for (i = 0; i < ARRAY_SIZE(default_srgb_lut); i++) { 3379 r = default_srgb_lut[i]; 3380 dc->cmu_output_lut[i] = (r << 32) | (r << 16) | r; 3381 } 3382 } 3383 3384 err = tegra_dc_rgb_probe(dc); 3385 if (err < 0 && err != -ENODEV) 3386 return dev_err_probe(&pdev->dev, err, 3387 "failed to probe RGB output\n"); 3388 3389 platform_set_drvdata(pdev, dc); 3390 pm_runtime_enable(&pdev->dev); 3391 3392 INIT_LIST_HEAD(&dc->client.list); 3393 dc->client.ops = &dc_client_ops; 3394 dc->client.dev = &pdev->dev; 3395 3396 err = host1x_client_register(&dc->client); 3397 if (err < 0) { 3398 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3399 err); 3400 goto disable_pm; 3401 } 3402 3403 return 0; 3404 3405 disable_pm: 3406 pm_runtime_disable(&pdev->dev); 3407 tegra_dc_rgb_remove(dc); 3408 3409 return err; 3410 } 3411 3412 static void tegra_dc_remove(struct platform_device *pdev) 3413 { 3414 struct tegra_dc *dc = platform_get_drvdata(pdev); 3415 3416 host1x_client_unregister(&dc->client); 3417 3418 tegra_dc_rgb_remove(dc); 3419 3420 pm_runtime_disable(&pdev->dev); 3421 } 3422 3423 struct platform_driver tegra_dc_driver = { 3424 .driver = { 3425 .name = "tegra-dc", 3426 .of_match_table = tegra_dc_of_match, 3427 }, 3428 .probe = tegra_dc_probe, 3429 .remove = tegra_dc_remove, 3430 }; 3431