1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/aperture.h> 4 #include <linux/of_address.h> 5 #include <linux/pci.h> 6 #include <linux/platform_device.h> 7 8 #include <drm/clients/drm_client_setup.h> 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_state_helper.h> 11 #include <drm/drm_color_mgmt.h> 12 #include <drm/drm_connector.h> 13 #include <drm/drm_damage_helper.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_drv.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_fbdev_shmem.h> 18 #include <drm/drm_framebuffer.h> 19 #include <drm/drm_gem_atomic_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_gem_shmem_helper.h> 22 #include <drm/drm_managed.h> 23 #include <drm/drm_modeset_helper_vtables.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 27 #include "drm_sysfb_helper.h" 28 29 #define DRIVER_NAME "ofdrm" 30 #define DRIVER_DESC "DRM driver for OF platform devices" 31 #define DRIVER_MAJOR 1 32 #define DRIVER_MINOR 0 33 34 #define PCI_VENDOR_ID_ATI_R520 0x7100 35 #define PCI_VENDOR_ID_ATI_R600 0x9400 36 37 #define OFDRM_GAMMA_LUT_SIZE 256 38 39 /* Definitions used by the Avivo palette */ 40 #define AVIVO_DC_LUT_RW_SELECT 0x6480 41 #define AVIVO_DC_LUT_RW_MODE 0x6484 42 #define AVIVO_DC_LUT_RW_INDEX 0x6488 43 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 44 #define AVIVO_DC_LUT_PWL_DATA 0x6490 45 #define AVIVO_DC_LUT_30_COLOR 0x6494 46 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 47 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 48 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 49 #define AVIVO_DC_LUTA_CONTROL 0x64c0 50 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 51 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 52 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 53 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 54 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 55 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 56 #define AVIVO_DC_LUTB_CONTROL 0x6cc0 57 #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4 58 #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8 59 #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc 60 #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0 61 #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4 62 #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8 63 64 enum ofdrm_model { 65 OFDRM_MODEL_UNKNOWN, 66 OFDRM_MODEL_MACH64, /* ATI Mach64 */ 67 OFDRM_MODEL_RAGE128, /* ATI Rage128 */ 68 OFDRM_MODEL_RAGE_M3A, /* ATI Rage Mobility M3 Head A */ 69 OFDRM_MODEL_RAGE_M3B, /* ATI Rage Mobility M3 Head B */ 70 OFDRM_MODEL_RADEON, /* ATI Radeon */ 71 OFDRM_MODEL_GXT2000, /* IBM GXT2000 */ 72 OFDRM_MODEL_AVIVO, /* ATI R5xx */ 73 OFDRM_MODEL_QEMU, /* QEMU VGA */ 74 }; 75 76 /* 77 * Helpers for display nodes 78 */ 79 80 static int display_get_validated_int(struct drm_device *dev, const char *name, uint32_t value) 81 { 82 return drm_sysfb_get_validated_int(dev, name, value, INT_MAX); 83 } 84 85 static int display_get_validated_int0(struct drm_device *dev, const char *name, uint32_t value) 86 { 87 return drm_sysfb_get_validated_int0(dev, name, value, INT_MAX); 88 } 89 90 static const struct drm_format_info *display_get_validated_format(struct drm_device *dev, 91 u32 depth, bool big_endian) 92 { 93 const struct drm_format_info *info; 94 u32 format; 95 96 switch (depth) { 97 case 8: 98 format = drm_mode_legacy_fb_format(8, 8); 99 break; 100 case 15: 101 case 16: 102 format = drm_mode_legacy_fb_format(16, depth); 103 break; 104 case 32: 105 format = drm_mode_legacy_fb_format(32, 24); 106 break; 107 default: 108 drm_err(dev, "unsupported framebuffer depth %u\n", depth); 109 return ERR_PTR(-EINVAL); 110 } 111 112 /* 113 * DRM formats assume little-endian byte order. Update the format 114 * if the scanout buffer uses big-endian ordering. 115 */ 116 if (big_endian) { 117 switch (format) { 118 case DRM_FORMAT_XRGB8888: 119 format = DRM_FORMAT_BGRX8888; 120 break; 121 case DRM_FORMAT_ARGB8888: 122 format = DRM_FORMAT_BGRA8888; 123 break; 124 case DRM_FORMAT_RGB565: 125 format = DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN; 126 break; 127 case DRM_FORMAT_XRGB1555: 128 format = DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN; 129 break; 130 default: 131 break; 132 } 133 } 134 135 info = drm_format_info(format); 136 if (!info) { 137 drm_err(dev, "cannot find framebuffer format for depth %u\n", depth); 138 return ERR_PTR(-EINVAL); 139 } 140 141 return info; 142 } 143 144 static int display_read_u32_of(struct drm_device *dev, struct device_node *of_node, 145 const char *name, u32 *value) 146 { 147 int ret = of_property_read_u32(of_node, name, value); 148 149 if (ret) 150 drm_err(dev, "cannot parse framebuffer %s: error %d\n", name, ret); 151 return ret; 152 } 153 154 static bool display_get_big_endian_of(struct drm_device *dev, struct device_node *of_node) 155 { 156 bool big_endian; 157 158 #ifdef __BIG_ENDIAN 159 big_endian = !of_property_read_bool(of_node, "little-endian"); 160 #else 161 big_endian = of_property_read_bool(of_node, "big-endian"); 162 #endif 163 164 return big_endian; 165 } 166 167 static int display_get_width_of(struct drm_device *dev, struct device_node *of_node) 168 { 169 u32 width; 170 int ret = display_read_u32_of(dev, of_node, "width", &width); 171 172 if (ret) 173 return ret; 174 return display_get_validated_int0(dev, "width", width); 175 } 176 177 static int display_get_height_of(struct drm_device *dev, struct device_node *of_node) 178 { 179 u32 height; 180 int ret = display_read_u32_of(dev, of_node, "height", &height); 181 182 if (ret) 183 return ret; 184 return display_get_validated_int0(dev, "height", height); 185 } 186 187 static int display_get_depth_of(struct drm_device *dev, struct device_node *of_node) 188 { 189 u32 depth; 190 int ret = display_read_u32_of(dev, of_node, "depth", &depth); 191 192 if (ret) 193 return ret; 194 return display_get_validated_int0(dev, "depth", depth); 195 } 196 197 static int display_get_linebytes_of(struct drm_device *dev, struct device_node *of_node) 198 { 199 u32 linebytes; 200 int ret = display_read_u32_of(dev, of_node, "linebytes", &linebytes); 201 202 if (ret) 203 return ret; 204 return display_get_validated_int(dev, "linebytes", linebytes); 205 } 206 207 static u64 display_get_address_of(struct drm_device *dev, struct device_node *of_node) 208 { 209 u32 address; 210 int ret; 211 212 /* 213 * Not all devices provide an address property, it's not 214 * a bug if this fails. The driver will try to find the 215 * framebuffer base address from the device's memory regions. 216 */ 217 ret = of_property_read_u32(of_node, "address", &address); 218 if (ret) 219 return OF_BAD_ADDR; 220 221 return address; 222 } 223 224 static const u8 *display_get_edid_of(struct drm_device *dev, struct device_node *of_node, 225 u8 buf[EDID_LENGTH]) 226 { 227 int ret = of_property_read_u8_array(of_node, "EDID", buf, EDID_LENGTH); 228 229 if (ret) 230 return NULL; 231 return buf; 232 } 233 234 static bool is_avivo(u32 vendor, u32 device) 235 { 236 /* This will match most R5xx */ 237 return (vendor == PCI_VENDOR_ID_ATI) && 238 ((device >= PCI_VENDOR_ID_ATI_R520 && device < 0x7800) || 239 (PCI_VENDOR_ID_ATI_R600 >= 0x9400)); 240 } 241 242 static enum ofdrm_model display_get_model_of(struct drm_device *dev, struct device_node *of_node) 243 { 244 enum ofdrm_model model = OFDRM_MODEL_UNKNOWN; 245 246 if (of_node_name_prefix(of_node, "ATY,Rage128")) { 247 model = OFDRM_MODEL_RAGE128; 248 } else if (of_node_name_prefix(of_node, "ATY,RageM3pA") || 249 of_node_name_prefix(of_node, "ATY,RageM3p12A")) { 250 model = OFDRM_MODEL_RAGE_M3A; 251 } else if (of_node_name_prefix(of_node, "ATY,RageM3pB")) { 252 model = OFDRM_MODEL_RAGE_M3B; 253 } else if (of_node_name_prefix(of_node, "ATY,Rage6")) { 254 model = OFDRM_MODEL_RADEON; 255 } else if (of_node_name_prefix(of_node, "ATY,")) { 256 return OFDRM_MODEL_MACH64; 257 } else if (of_device_is_compatible(of_node, "pci1014,b7") || 258 of_device_is_compatible(of_node, "pci1014,21c")) { 259 model = OFDRM_MODEL_GXT2000; 260 } else if (of_node_name_prefix(of_node, "vga,Display-")) { 261 struct device_node *of_parent; 262 const __be32 *vendor_p, *device_p; 263 264 /* Look for AVIVO initialized by SLOF */ 265 of_parent = of_get_parent(of_node); 266 vendor_p = of_get_property(of_parent, "vendor-id", NULL); 267 device_p = of_get_property(of_parent, "device-id", NULL); 268 if (vendor_p && device_p) { 269 u32 vendor = be32_to_cpup(vendor_p); 270 u32 device = be32_to_cpup(device_p); 271 272 if (is_avivo(vendor, device)) 273 model = OFDRM_MODEL_AVIVO; 274 } 275 of_node_put(of_parent); 276 } else if (of_device_is_compatible(of_node, "qemu,std-vga")) { 277 model = OFDRM_MODEL_QEMU; 278 } 279 280 return model; 281 } 282 283 /* 284 * Open Firmware display device 285 */ 286 287 struct ofdrm_device; 288 289 struct ofdrm_device_funcs { 290 void __iomem *(*cmap_ioremap)(struct ofdrm_device *odev, 291 struct device_node *of_node, 292 u64 fb_bas); 293 void (*cmap_write)(struct ofdrm_device *odev, unsigned char index, 294 unsigned char r, unsigned char g, unsigned char b); 295 }; 296 297 struct ofdrm_device { 298 struct drm_sysfb_device sysfb; 299 300 const struct ofdrm_device_funcs *funcs; 301 302 /* colormap */ 303 void __iomem *cmap_base; 304 305 u8 edid[EDID_LENGTH]; 306 307 /* modesetting */ 308 u32 formats[DRM_SYSFB_PLANE_NFORMATS(1)]; 309 struct drm_plane primary_plane; 310 struct drm_crtc crtc; 311 struct drm_encoder encoder; 312 struct drm_connector connector; 313 }; 314 315 static struct ofdrm_device *ofdrm_device_of_dev(struct drm_device *dev) 316 { 317 return container_of(to_drm_sysfb_device(dev), struct ofdrm_device, sysfb); 318 } 319 320 /* 321 * Hardware 322 */ 323 324 #if defined(CONFIG_PCI) 325 static struct pci_dev *display_get_pci_dev_of(struct drm_device *dev, struct device_node *of_node) 326 { 327 const __be32 *vendor_p, *device_p; 328 u32 vendor, device; 329 struct pci_dev *pcidev; 330 331 vendor_p = of_get_property(of_node, "vendor-id", NULL); 332 if (!vendor_p) 333 return ERR_PTR(-ENODEV); 334 vendor = be32_to_cpup(vendor_p); 335 336 device_p = of_get_property(of_node, "device-id", NULL); 337 if (!device_p) 338 return ERR_PTR(-ENODEV); 339 device = be32_to_cpup(device_p); 340 341 pcidev = pci_get_device(vendor, device, NULL); 342 if (!pcidev) 343 return ERR_PTR(-ENODEV); 344 345 return pcidev; 346 } 347 348 static void ofdrm_pci_release(void *data) 349 { 350 struct pci_dev *pcidev = data; 351 352 pci_disable_device(pcidev); 353 pci_dev_put(pcidev); 354 } 355 356 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 357 { 358 struct drm_device *dev = &odev->sysfb.dev; 359 struct platform_device *pdev = to_platform_device(dev->dev); 360 struct device_node *of_node = pdev->dev.of_node; 361 struct pci_dev *pcidev; 362 int ret; 363 364 /* 365 * Never use pcim_ or other managed helpers on the returned PCI 366 * device. Otherwise, probing the native driver will fail for 367 * resource conflicts. PCI-device management has to be tied to 368 * the lifetime of the platform device until the native driver 369 * takes over. 370 */ 371 pcidev = display_get_pci_dev_of(dev, of_node); 372 if (IS_ERR(pcidev)) 373 return 0; /* no PCI device found; ignore the error */ 374 375 ret = pci_enable_device(pcidev); 376 if (ret) { 377 drm_err(dev, "pci_enable_device(%s) failed: %d\n", 378 dev_name(&pcidev->dev), ret); 379 pci_dev_put(pcidev); 380 return ret; 381 } 382 ret = devm_add_action_or_reset(&pdev->dev, ofdrm_pci_release, pcidev); 383 if (ret) 384 return ret; 385 386 return 0; 387 } 388 #else 389 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 390 { 391 return 0; 392 } 393 #endif 394 395 /* 396 * OF display settings 397 */ 398 399 static struct resource *ofdrm_find_fb_resource(struct ofdrm_device *odev, 400 struct resource *fb_res) 401 { 402 struct platform_device *pdev = to_platform_device(odev->sysfb.dev.dev); 403 struct resource *res, *max_res = NULL; 404 u32 i; 405 406 for (i = 0; pdev->num_resources; ++i) { 407 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 408 if (!res) 409 break; /* all resources processed */ 410 if (resource_size(res) < resource_size(fb_res)) 411 continue; /* resource too small */ 412 if (fb_res->start && resource_contains(res, fb_res)) 413 return res; /* resource contains framebuffer */ 414 if (!max_res || resource_size(res) > resource_size(max_res)) 415 max_res = res; /* store largest resource as fallback */ 416 } 417 418 return max_res; 419 } 420 421 /* 422 * Colormap / Palette 423 */ 424 425 static void __iomem *get_cmap_address_of(struct ofdrm_device *odev, struct device_node *of_node, 426 int bar_no, unsigned long offset, unsigned long size) 427 { 428 struct drm_device *dev = &odev->sysfb.dev; 429 const __be32 *addr_p; 430 u64 max_size, address; 431 unsigned int flags; 432 void __iomem *mem; 433 434 addr_p = of_get_pci_address(of_node, bar_no, &max_size, &flags); 435 if (!addr_p) 436 addr_p = of_get_address(of_node, bar_no, &max_size, &flags); 437 if (!addr_p) 438 return IOMEM_ERR_PTR(-ENODEV); 439 440 if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 441 return IOMEM_ERR_PTR(-ENODEV); 442 443 if ((offset + size) >= max_size) 444 return IOMEM_ERR_PTR(-ENODEV); 445 446 address = of_translate_address(of_node, addr_p); 447 if (address == OF_BAD_ADDR) 448 return IOMEM_ERR_PTR(-ENODEV); 449 450 mem = devm_ioremap(dev->dev, address + offset, size); 451 if (!mem) 452 return IOMEM_ERR_PTR(-ENOMEM); 453 454 return mem; 455 } 456 457 static void __iomem *ofdrm_mach64_cmap_ioremap(struct ofdrm_device *odev, 458 struct device_node *of_node, 459 u64 fb_base) 460 { 461 struct drm_device *dev = &odev->sysfb.dev; 462 u64 address; 463 void __iomem *cmap_base; 464 465 address = fb_base & 0xff000000ul; 466 address += 0x7ff000; 467 468 cmap_base = devm_ioremap(dev->dev, address, 0x1000); 469 if (!cmap_base) 470 return IOMEM_ERR_PTR(-ENOMEM); 471 472 return cmap_base; 473 } 474 475 static void ofdrm_mach64_cmap_write(struct ofdrm_device *odev, unsigned char index, 476 unsigned char r, unsigned char g, unsigned char b) 477 { 478 void __iomem *addr = odev->cmap_base + 0xcc0; 479 void __iomem *data = odev->cmap_base + 0xcc0 + 1; 480 481 writeb(index, addr); 482 writeb(r, data); 483 writeb(g, data); 484 writeb(b, data); 485 } 486 487 static void __iomem *ofdrm_rage128_cmap_ioremap(struct ofdrm_device *odev, 488 struct device_node *of_node, 489 u64 fb_base) 490 { 491 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 492 } 493 494 static void ofdrm_rage128_cmap_write(struct ofdrm_device *odev, unsigned char index, 495 unsigned char r, unsigned char g, unsigned char b) 496 { 497 void __iomem *addr = odev->cmap_base + 0xb0; 498 void __iomem *data = odev->cmap_base + 0xb4; 499 u32 color = (r << 16) | (g << 8) | b; 500 501 writeb(index, addr); 502 writel(color, data); 503 } 504 505 static void __iomem *ofdrm_rage_m3a_cmap_ioremap(struct ofdrm_device *odev, 506 struct device_node *of_node, 507 u64 fb_base) 508 { 509 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 510 } 511 512 static void ofdrm_rage_m3a_cmap_write(struct ofdrm_device *odev, unsigned char index, 513 unsigned char r, unsigned char g, unsigned char b) 514 { 515 void __iomem *dac_ctl = odev->cmap_base + 0x58; 516 void __iomem *addr = odev->cmap_base + 0xb0; 517 void __iomem *data = odev->cmap_base + 0xb4; 518 u32 color = (r << 16) | (g << 8) | b; 519 u32 val; 520 521 /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */ 522 val = readl(dac_ctl); 523 val &= ~0x20; 524 writel(val, dac_ctl); 525 526 /* Set color at palette index */ 527 writeb(index, addr); 528 writel(color, data); 529 } 530 531 static void __iomem *ofdrm_rage_m3b_cmap_ioremap(struct ofdrm_device *odev, 532 struct device_node *of_node, 533 u64 fb_base) 534 { 535 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 536 } 537 538 static void ofdrm_rage_m3b_cmap_write(struct ofdrm_device *odev, unsigned char index, 539 unsigned char r, unsigned char g, unsigned char b) 540 { 541 void __iomem *dac_ctl = odev->cmap_base + 0x58; 542 void __iomem *addr = odev->cmap_base + 0xb0; 543 void __iomem *data = odev->cmap_base + 0xb4; 544 u32 color = (r << 16) | (g << 8) | b; 545 u32 val; 546 547 /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */ 548 val = readl(dac_ctl); 549 val |= 0x20; 550 writel(val, dac_ctl); 551 552 /* Set color at palette index */ 553 writeb(index, addr); 554 writel(color, data); 555 } 556 557 static void __iomem *ofdrm_radeon_cmap_ioremap(struct ofdrm_device *odev, 558 struct device_node *of_node, 559 u64 fb_base) 560 { 561 return get_cmap_address_of(odev, of_node, 1, 0, 0x1fff); 562 } 563 564 static void __iomem *ofdrm_gxt2000_cmap_ioremap(struct ofdrm_device *odev, 565 struct device_node *of_node, 566 u64 fb_base) 567 { 568 return get_cmap_address_of(odev, of_node, 0, 0x6000, 0x1000); 569 } 570 571 static void ofdrm_gxt2000_cmap_write(struct ofdrm_device *odev, unsigned char index, 572 unsigned char r, unsigned char g, unsigned char b) 573 { 574 void __iomem *data = ((unsigned int __iomem *)odev->cmap_base) + index; 575 u32 color = (r << 16) | (g << 8) | b; 576 577 writel(color, data); 578 } 579 580 static void __iomem *ofdrm_avivo_cmap_ioremap(struct ofdrm_device *odev, 581 struct device_node *of_node, 582 u64 fb_base) 583 { 584 struct device_node *of_parent; 585 void __iomem *cmap_base; 586 587 of_parent = of_get_parent(of_node); 588 cmap_base = get_cmap_address_of(odev, of_parent, 0, 0, 0x10000); 589 of_node_put(of_parent); 590 591 return cmap_base; 592 } 593 594 static void ofdrm_avivo_cmap_write(struct ofdrm_device *odev, unsigned char index, 595 unsigned char r, unsigned char g, unsigned char b) 596 { 597 void __iomem *lutsel = odev->cmap_base + AVIVO_DC_LUT_RW_SELECT; 598 void __iomem *addr = odev->cmap_base + AVIVO_DC_LUT_RW_INDEX; 599 void __iomem *data = odev->cmap_base + AVIVO_DC_LUT_30_COLOR; 600 u32 color = (r << 22) | (g << 12) | (b << 2); 601 602 /* Write to both LUTs for now */ 603 604 writel(1, lutsel); 605 writeb(index, addr); 606 writel(color, data); 607 608 writel(0, lutsel); 609 writeb(index, addr); 610 writel(color, data); 611 } 612 613 static void __iomem *ofdrm_qemu_cmap_ioremap(struct ofdrm_device *odev, 614 struct device_node *of_node, 615 u64 fb_base) 616 { 617 static const __be32 io_of_addr[3] = { 618 cpu_to_be32(0x01000000), 619 cpu_to_be32(0x00), 620 cpu_to_be32(0x00), 621 }; 622 623 struct drm_device *dev = &odev->sysfb.dev; 624 u64 address; 625 void __iomem *cmap_base; 626 627 address = of_translate_address(of_node, io_of_addr); 628 if (address == OF_BAD_ADDR) 629 return IOMEM_ERR_PTR(-ENODEV); 630 631 cmap_base = devm_ioremap(dev->dev, address + 0x3c8, 2); 632 if (!cmap_base) 633 return IOMEM_ERR_PTR(-ENOMEM); 634 635 return cmap_base; 636 } 637 638 static void ofdrm_qemu_cmap_write(struct ofdrm_device *odev, unsigned char index, 639 unsigned char r, unsigned char g, unsigned char b) 640 { 641 void __iomem *addr = odev->cmap_base; 642 void __iomem *data = odev->cmap_base + 1; 643 644 writeb(index, addr); 645 writeb(r, data); 646 writeb(g, data); 647 writeb(b, data); 648 } 649 650 static void ofdrm_set_gamma_lut(struct drm_crtc *crtc, unsigned int index, 651 u16 red, u16 green, u16 blue) 652 { 653 struct drm_device *dev = crtc->dev; 654 struct ofdrm_device *odev = ofdrm_device_of_dev(dev); 655 u8 i8 = index & 0xff; 656 u8 r8 = red >> 8; 657 u8 g8 = green >> 8; 658 u8 b8 = blue >> 8; 659 660 if (drm_WARN_ON_ONCE(dev, index != i8)) 661 return; /* driver bug */ 662 663 odev->funcs->cmap_write(odev, i8, r8, g8, b8); 664 } 665 666 static void ofdrm_device_fill_gamma(struct ofdrm_device *odev, 667 const struct drm_format_info *format) 668 { 669 struct drm_device *dev = &odev->sysfb.dev; 670 struct drm_crtc *crtc = &odev->crtc; 671 672 switch (format->format) { 673 case DRM_FORMAT_RGB565: 674 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 675 drm_crtc_fill_gamma_565(crtc, ofdrm_set_gamma_lut); 676 break; 677 case DRM_FORMAT_XRGB8888: 678 case DRM_FORMAT_BGRX8888: 679 drm_crtc_fill_gamma_888(crtc, ofdrm_set_gamma_lut); 680 break; 681 default: 682 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 683 &format->format); 684 break; 685 } 686 } 687 688 static void ofdrm_device_load_gamma(struct ofdrm_device *odev, 689 const struct drm_format_info *format, 690 struct drm_color_lut *lut) 691 { 692 struct drm_device *dev = &odev->sysfb.dev; 693 struct drm_crtc *crtc = &odev->crtc; 694 695 switch (format->format) { 696 case DRM_FORMAT_RGB565: 697 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 698 drm_crtc_load_gamma_565_from_888(crtc, lut, ofdrm_set_gamma_lut); 699 break; 700 case DRM_FORMAT_XRGB8888: 701 case DRM_FORMAT_BGRX8888: 702 drm_crtc_load_gamma_888(crtc, lut, ofdrm_set_gamma_lut); 703 break; 704 default: 705 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 706 &format->format); 707 break; 708 } 709 } 710 711 /* 712 * Modesetting 713 */ 714 715 static const u64 ofdrm_primary_plane_format_modifiers[] = { 716 DRM_SYSFB_PLANE_FORMAT_MODIFIERS, 717 }; 718 719 static const struct drm_plane_helper_funcs ofdrm_primary_plane_helper_funcs = { 720 DRM_SYSFB_PLANE_HELPER_FUNCS, 721 }; 722 723 static const struct drm_plane_funcs ofdrm_primary_plane_funcs = { 724 DRM_SYSFB_PLANE_FUNCS, 725 .destroy = drm_plane_cleanup, 726 }; 727 728 static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) 729 { 730 struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); 731 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 732 struct drm_sysfb_crtc_state *sysfb_crtc_state = to_drm_sysfb_crtc_state(crtc_state); 733 734 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 735 const struct drm_format_info *format = sysfb_crtc_state->format; 736 737 if (crtc_state->gamma_lut) 738 ofdrm_device_load_gamma(odev, format, crtc_state->gamma_lut->data); 739 else 740 ofdrm_device_fill_gamma(odev, format); 741 } 742 } 743 744 static const struct drm_crtc_helper_funcs ofdrm_crtc_helper_funcs = { 745 DRM_SYSFB_CRTC_HELPER_FUNCS, 746 .atomic_flush = ofdrm_crtc_helper_atomic_flush, 747 }; 748 749 static const struct drm_crtc_funcs ofdrm_crtc_funcs = { 750 DRM_SYSFB_CRTC_FUNCS, 751 .destroy = drm_crtc_cleanup, 752 }; 753 754 static const struct drm_encoder_funcs ofdrm_encoder_funcs = { 755 .destroy = drm_encoder_cleanup, 756 }; 757 758 static const struct drm_connector_helper_funcs ofdrm_connector_helper_funcs = { 759 DRM_SYSFB_CONNECTOR_HELPER_FUNCS, 760 }; 761 762 static const struct drm_connector_funcs ofdrm_connector_funcs = { 763 DRM_SYSFB_CONNECTOR_FUNCS, 764 .destroy = drm_connector_cleanup, 765 }; 766 767 static const struct drm_mode_config_funcs ofdrm_mode_config_funcs = { 768 DRM_SYSFB_MODE_CONFIG_FUNCS, 769 }; 770 771 /* 772 * Init / Cleanup 773 */ 774 775 static const struct ofdrm_device_funcs ofdrm_unknown_device_funcs = { 776 }; 777 778 static const struct ofdrm_device_funcs ofdrm_mach64_device_funcs = { 779 .cmap_ioremap = ofdrm_mach64_cmap_ioremap, 780 .cmap_write = ofdrm_mach64_cmap_write, 781 }; 782 783 static const struct ofdrm_device_funcs ofdrm_rage128_device_funcs = { 784 .cmap_ioremap = ofdrm_rage128_cmap_ioremap, 785 .cmap_write = ofdrm_rage128_cmap_write, 786 }; 787 788 static const struct ofdrm_device_funcs ofdrm_rage_m3a_device_funcs = { 789 .cmap_ioremap = ofdrm_rage_m3a_cmap_ioremap, 790 .cmap_write = ofdrm_rage_m3a_cmap_write, 791 }; 792 793 static const struct ofdrm_device_funcs ofdrm_rage_m3b_device_funcs = { 794 .cmap_ioremap = ofdrm_rage_m3b_cmap_ioremap, 795 .cmap_write = ofdrm_rage_m3b_cmap_write, 796 }; 797 798 static const struct ofdrm_device_funcs ofdrm_radeon_device_funcs = { 799 .cmap_ioremap = ofdrm_radeon_cmap_ioremap, 800 .cmap_write = ofdrm_rage128_cmap_write, /* same as Rage128 */ 801 }; 802 803 static const struct ofdrm_device_funcs ofdrm_gxt2000_device_funcs = { 804 .cmap_ioremap = ofdrm_gxt2000_cmap_ioremap, 805 .cmap_write = ofdrm_gxt2000_cmap_write, 806 }; 807 808 static const struct ofdrm_device_funcs ofdrm_avivo_device_funcs = { 809 .cmap_ioremap = ofdrm_avivo_cmap_ioremap, 810 .cmap_write = ofdrm_avivo_cmap_write, 811 }; 812 813 static const struct ofdrm_device_funcs ofdrm_qemu_device_funcs = { 814 .cmap_ioremap = ofdrm_qemu_cmap_ioremap, 815 .cmap_write = ofdrm_qemu_cmap_write, 816 }; 817 818 static struct ofdrm_device *ofdrm_device_create(struct drm_driver *drv, 819 struct platform_device *pdev) 820 { 821 struct device_node *of_node = pdev->dev.of_node; 822 struct ofdrm_device *odev; 823 struct drm_sysfb_device *sysfb; 824 struct drm_device *dev; 825 enum ofdrm_model model; 826 bool big_endian; 827 int width, height, depth, linebytes; 828 const struct drm_format_info *format; 829 u64 address; 830 const u8 *edid; 831 resource_size_t fb_size, fb_base, fb_pgbase, fb_pgsize; 832 struct resource *res, *mem; 833 void __iomem *screen_base; 834 struct drm_plane *primary_plane; 835 struct drm_crtc *crtc; 836 struct drm_encoder *encoder; 837 struct drm_connector *connector; 838 unsigned long max_width, max_height; 839 size_t nformats; 840 int ret; 841 842 odev = devm_drm_dev_alloc(&pdev->dev, drv, struct ofdrm_device, sysfb.dev); 843 if (IS_ERR(odev)) 844 return ERR_CAST(odev); 845 sysfb = &odev->sysfb; 846 dev = &sysfb->dev; 847 platform_set_drvdata(pdev, dev); 848 849 ret = ofdrm_device_init_pci(odev); 850 if (ret) 851 return ERR_PTR(ret); 852 853 /* 854 * OF display-node settings 855 */ 856 857 model = display_get_model_of(dev, of_node); 858 drm_dbg(dev, "detected model %d\n", model); 859 860 switch (model) { 861 case OFDRM_MODEL_UNKNOWN: 862 odev->funcs = &ofdrm_unknown_device_funcs; 863 break; 864 case OFDRM_MODEL_MACH64: 865 odev->funcs = &ofdrm_mach64_device_funcs; 866 break; 867 case OFDRM_MODEL_RAGE128: 868 odev->funcs = &ofdrm_rage128_device_funcs; 869 break; 870 case OFDRM_MODEL_RAGE_M3A: 871 odev->funcs = &ofdrm_rage_m3a_device_funcs; 872 break; 873 case OFDRM_MODEL_RAGE_M3B: 874 odev->funcs = &ofdrm_rage_m3b_device_funcs; 875 break; 876 case OFDRM_MODEL_RADEON: 877 odev->funcs = &ofdrm_radeon_device_funcs; 878 break; 879 case OFDRM_MODEL_GXT2000: 880 odev->funcs = &ofdrm_gxt2000_device_funcs; 881 break; 882 case OFDRM_MODEL_AVIVO: 883 odev->funcs = &ofdrm_avivo_device_funcs; 884 break; 885 case OFDRM_MODEL_QEMU: 886 odev->funcs = &ofdrm_qemu_device_funcs; 887 break; 888 } 889 890 big_endian = display_get_big_endian_of(dev, of_node); 891 892 width = display_get_width_of(dev, of_node); 893 if (width < 0) 894 return ERR_PTR(width); 895 height = display_get_height_of(dev, of_node); 896 if (height < 0) 897 return ERR_PTR(height); 898 depth = display_get_depth_of(dev, of_node); 899 if (depth < 0) 900 return ERR_PTR(depth); 901 linebytes = display_get_linebytes_of(dev, of_node); 902 if (linebytes < 0) 903 return ERR_PTR(linebytes); 904 905 format = display_get_validated_format(dev, depth, big_endian); 906 if (IS_ERR(format)) 907 return ERR_CAST(format); 908 if (!linebytes) { 909 linebytes = drm_format_info_min_pitch(format, 0, width); 910 if (drm_WARN_ON(dev, !linebytes)) 911 return ERR_PTR(-EINVAL); 912 } 913 914 fb_size = linebytes * height; 915 916 /* 917 * Try to figure out the address of the framebuffer. Unfortunately, Open 918 * Firmware doesn't provide a standard way to do so. All we can do is a 919 * dodgy heuristic that happens to work in practice. 920 * 921 * On most machines, the "address" property contains what we need, though 922 * not on Matrox cards found in IBM machines. What appears to give good 923 * results is to go through the PCI ranges and pick one that encloses the 924 * "address" property. If none match, we pick the largest. 925 */ 926 address = display_get_address_of(dev, of_node); 927 if (address != OF_BAD_ADDR) { 928 struct resource fb_res = DEFINE_RES_MEM(address, fb_size); 929 930 res = ofdrm_find_fb_resource(odev, &fb_res); 931 if (!res) 932 return ERR_PTR(-EINVAL); 933 if (resource_contains(res, &fb_res)) 934 fb_base = address; 935 else 936 fb_base = res->start; 937 } else { 938 struct resource fb_res = DEFINE_RES_MEM(0u, fb_size); 939 940 res = ofdrm_find_fb_resource(odev, &fb_res); 941 if (!res) 942 return ERR_PTR(-EINVAL); 943 fb_base = res->start; 944 } 945 946 /* 947 * I/O resources 948 */ 949 950 fb_pgbase = round_down(fb_base, PAGE_SIZE); 951 fb_pgsize = fb_base - fb_pgbase + round_up(fb_size, PAGE_SIZE); 952 953 ret = devm_aperture_acquire_for_platform_device(pdev, fb_pgbase, fb_pgsize); 954 if (ret) { 955 drm_err(dev, "could not acquire memory range %pr: error %d\n", &res, ret); 956 return ERR_PTR(ret); 957 } 958 959 mem = devm_request_mem_region(&pdev->dev, fb_pgbase, fb_pgsize, drv->name); 960 if (!mem) { 961 drm_warn(dev, "could not acquire memory region %pr\n", &res); 962 return ERR_PTR(-ENOMEM); 963 } 964 965 screen_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 966 if (!screen_base) 967 return ERR_PTR(-ENOMEM); 968 969 if (odev->funcs->cmap_ioremap) { 970 void __iomem *cmap_base = odev->funcs->cmap_ioremap(odev, of_node, fb_base); 971 972 if (IS_ERR(cmap_base)) { 973 /* Don't fail; continue without colormap */ 974 drm_warn(dev, "could not find colormap: error %ld\n", PTR_ERR(cmap_base)); 975 } else { 976 odev->cmap_base = cmap_base; 977 } 978 } 979 980 /* EDID is optional */ 981 edid = display_get_edid_of(dev, of_node, odev->edid); 982 983 /* 984 * Firmware framebuffer 985 */ 986 987 iosys_map_set_vaddr_iomem(&sysfb->fb_addr, screen_base); 988 sysfb->fb_mode = drm_sysfb_mode(width, height, 0, 0); 989 sysfb->fb_format = format; 990 sysfb->fb_pitch = linebytes; 991 if (odev->cmap_base) 992 sysfb->fb_gamma_lut_size = OFDRM_GAMMA_LUT_SIZE; 993 sysfb->edid = edid; 994 995 drm_dbg(dev, "display mode={" DRM_MODE_FMT "}\n", DRM_MODE_ARG(&sysfb->fb_mode)); 996 drm_dbg(dev, "framebuffer format=%p4cc, size=%dx%d, linebytes=%d byte\n", 997 &format->format, width, height, linebytes); 998 999 /* 1000 * Mode-setting pipeline 1001 */ 1002 1003 ret = drmm_mode_config_init(dev); 1004 if (ret) 1005 return ERR_PTR(ret); 1006 1007 max_width = max_t(unsigned long, width, DRM_SHADOW_PLANE_MAX_WIDTH); 1008 max_height = max_t(unsigned long, height, DRM_SHADOW_PLANE_MAX_HEIGHT); 1009 1010 dev->mode_config.min_width = width; 1011 dev->mode_config.max_width = max_width; 1012 dev->mode_config.min_height = height; 1013 dev->mode_config.max_height = max_height; 1014 dev->mode_config.funcs = &ofdrm_mode_config_funcs; 1015 dev->mode_config.preferred_depth = format->depth; 1016 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 1017 1018 /* Primary plane */ 1019 1020 nformats = drm_sysfb_build_fourcc_list(dev, &format->format, 1, 1021 odev->formats, ARRAY_SIZE(odev->formats)); 1022 1023 primary_plane = &odev->primary_plane; 1024 ret = drm_universal_plane_init(dev, primary_plane, 0, &ofdrm_primary_plane_funcs, 1025 odev->formats, nformats, 1026 ofdrm_primary_plane_format_modifiers, 1027 DRM_PLANE_TYPE_PRIMARY, NULL); 1028 if (ret) 1029 return ERR_PTR(ret); 1030 drm_plane_helper_add(primary_plane, &ofdrm_primary_plane_helper_funcs); 1031 drm_plane_enable_fb_damage_clips(primary_plane); 1032 1033 /* CRTC */ 1034 1035 crtc = &odev->crtc; 1036 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 1037 &ofdrm_crtc_funcs, NULL); 1038 if (ret) 1039 return ERR_PTR(ret); 1040 drm_crtc_helper_add(crtc, &ofdrm_crtc_helper_funcs); 1041 1042 if (sysfb->fb_gamma_lut_size) { 1043 ret = drm_mode_crtc_set_gamma_size(crtc, sysfb->fb_gamma_lut_size); 1044 if (!ret) 1045 drm_crtc_enable_color_mgmt(crtc, 0, false, sysfb->fb_gamma_lut_size); 1046 } 1047 1048 /* Encoder */ 1049 1050 encoder = &odev->encoder; 1051 ret = drm_encoder_init(dev, encoder, &ofdrm_encoder_funcs, DRM_MODE_ENCODER_NONE, NULL); 1052 if (ret) 1053 return ERR_PTR(ret); 1054 encoder->possible_crtcs = drm_crtc_mask(crtc); 1055 1056 /* Connector */ 1057 1058 connector = &odev->connector; 1059 ret = drm_connector_init(dev, connector, &ofdrm_connector_funcs, 1060 DRM_MODE_CONNECTOR_Unknown); 1061 if (ret) 1062 return ERR_PTR(ret); 1063 drm_connector_helper_add(connector, &ofdrm_connector_helper_funcs); 1064 drm_connector_set_panel_orientation_with_quirk(connector, 1065 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 1066 width, height); 1067 if (edid) 1068 drm_connector_attach_edid_property(connector); 1069 1070 ret = drm_connector_attach_encoder(connector, encoder); 1071 if (ret) 1072 return ERR_PTR(ret); 1073 1074 drm_mode_config_reset(dev); 1075 1076 return odev; 1077 } 1078 1079 /* 1080 * DRM driver 1081 */ 1082 1083 DEFINE_DRM_GEM_FOPS(ofdrm_fops); 1084 1085 static struct drm_driver ofdrm_driver = { 1086 DRM_GEM_SHMEM_DRIVER_OPS, 1087 DRM_FBDEV_SHMEM_DRIVER_OPS, 1088 .name = DRIVER_NAME, 1089 .desc = DRIVER_DESC, 1090 .major = DRIVER_MAJOR, 1091 .minor = DRIVER_MINOR, 1092 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1093 .fops = &ofdrm_fops, 1094 }; 1095 1096 /* 1097 * Platform driver 1098 */ 1099 1100 static int ofdrm_probe(struct platform_device *pdev) 1101 { 1102 struct ofdrm_device *odev; 1103 struct drm_sysfb_device *sysfb; 1104 struct drm_device *dev; 1105 int ret; 1106 1107 odev = ofdrm_device_create(&ofdrm_driver, pdev); 1108 if (IS_ERR(odev)) 1109 return PTR_ERR(odev); 1110 sysfb = &odev->sysfb; 1111 dev = &sysfb->dev; 1112 1113 ret = drm_dev_register(dev, 0); 1114 if (ret) 1115 return ret; 1116 1117 drm_client_setup(dev, sysfb->fb_format); 1118 1119 return 0; 1120 } 1121 1122 static void ofdrm_remove(struct platform_device *pdev) 1123 { 1124 struct drm_device *dev = platform_get_drvdata(pdev); 1125 1126 drm_dev_unplug(dev); 1127 } 1128 1129 static const struct of_device_id ofdrm_of_match_display[] = { 1130 { .compatible = "display", }, 1131 { }, 1132 }; 1133 MODULE_DEVICE_TABLE(of, ofdrm_of_match_display); 1134 1135 static struct platform_driver ofdrm_platform_driver = { 1136 .driver = { 1137 .name = "of-display", 1138 .of_match_table = ofdrm_of_match_display, 1139 }, 1140 .probe = ofdrm_probe, 1141 .remove = ofdrm_remove, 1142 }; 1143 1144 module_platform_driver(ofdrm_platform_driver); 1145 1146 MODULE_DESCRIPTION(DRIVER_DESC); 1147 MODULE_LICENSE("GPL"); 1148