1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #ifndef _SUN8I_MIXER_H_ 7 #define _SUN8I_MIXER_H_ 8 9 #include <linux/clk.h> 10 #include <linux/regmap.h> 11 #include <linux/reset.h> 12 13 #include "sunxi_engine.h" 14 15 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1)) 16 #define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x)) 17 18 #define SUN8I_MIXER_GLOBAL_CTL 0x0 19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4 20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8 21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc 22 23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) 24 25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) 26 27 #define DE2_MIXER_UNIT_SIZE 0x6000 28 #define DE3_MIXER_UNIT_SIZE 0x3000 29 30 #define DE2_BLD_BASE 0x1000 31 #define DE2_CH_BASE 0x2000 32 #define DE2_CH_SIZE 0x1000 33 34 #define DE3_BLD_BASE 0x0800 35 #define DE3_CH_BASE 0x1000 36 #define DE3_CH_SIZE 0x0800 37 38 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) 39 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) 40 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) 41 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) 42 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) 43 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) 44 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) 45 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) 46 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) 47 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) 48 #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4) 49 #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x)) 50 #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) 51 #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) 52 #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) 53 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \ 54 ((base) + 0x110 + (layer) * 0x30 + (x) * 4) 55 56 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8) 57 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe) 58 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe) 59 60 /* colors are always in AARRGGBB format */ 61 #define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000 62 /* The following numbers are some still unknown magic numbers */ 63 #define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301 64 65 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) 66 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) 67 68 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) 69 70 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) 71 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff)) 72 73 #define SUN8I_MIXER_FBFMT_ARGB8888 0 74 #define SUN8I_MIXER_FBFMT_ABGR8888 1 75 #define SUN8I_MIXER_FBFMT_RGBA8888 2 76 #define SUN8I_MIXER_FBFMT_BGRA8888 3 77 #define SUN8I_MIXER_FBFMT_XRGB8888 4 78 #define SUN8I_MIXER_FBFMT_XBGR8888 5 79 #define SUN8I_MIXER_FBFMT_RGBX8888 6 80 #define SUN8I_MIXER_FBFMT_BGRX8888 7 81 #define SUN8I_MIXER_FBFMT_RGB888 8 82 #define SUN8I_MIXER_FBFMT_BGR888 9 83 #define SUN8I_MIXER_FBFMT_RGB565 10 84 #define SUN8I_MIXER_FBFMT_BGR565 11 85 #define SUN8I_MIXER_FBFMT_ARGB4444 12 86 #define SUN8I_MIXER_FBFMT_ABGR4444 13 87 #define SUN8I_MIXER_FBFMT_RGBA4444 14 88 #define SUN8I_MIXER_FBFMT_BGRA4444 15 89 #define SUN8I_MIXER_FBFMT_ARGB1555 16 90 #define SUN8I_MIXER_FBFMT_ABGR1555 17 91 #define SUN8I_MIXER_FBFMT_RGBA5551 18 92 #define SUN8I_MIXER_FBFMT_BGRA5551 19 93 #define SUN8I_MIXER_FBFMT_ARGB2101010 20 94 #define SUN8I_MIXER_FBFMT_ABGR2101010 21 95 #define SUN8I_MIXER_FBFMT_RGBA1010102 22 96 #define SUN8I_MIXER_FBFMT_BGRA1010102 23 97 98 #define SUN8I_MIXER_FBFMT_YUYV 0 99 #define SUN8I_MIXER_FBFMT_UYVY 1 100 #define SUN8I_MIXER_FBFMT_YVYU 2 101 #define SUN8I_MIXER_FBFMT_VYUY 3 102 #define SUN8I_MIXER_FBFMT_NV16 4 103 #define SUN8I_MIXER_FBFMT_NV61 5 104 #define SUN8I_MIXER_FBFMT_YUV422 6 105 /* format 7 doesn't exist */ 106 #define SUN8I_MIXER_FBFMT_NV12 8 107 #define SUN8I_MIXER_FBFMT_NV21 9 108 #define SUN8I_MIXER_FBFMT_YUV420 10 109 /* format 11 doesn't exist */ 110 /* format 12 is semi-planar YUV411 UVUV */ 111 /* format 13 is semi-planar YUV411 VUVU */ 112 #define SUN8I_MIXER_FBFMT_YUV411 14 113 /* format 15 doesn't exist */ 114 #define SUN8I_MIXER_FBFMT_P010_YUV 16 115 /* format 17 is P010 YVU */ 116 #define SUN8I_MIXER_FBFMT_P210_YUV 18 117 /* format 19 is P210 YVU */ 118 /* format 20 is packed YVU444 10-bit */ 119 /* format 21 is packed YUV444 10-bit */ 120 121 /* 122 * Sub-engines listed bellow are unused for now. The EN registers are here only 123 * to be used to disable these sub-engines. 124 */ 125 #define SUN8I_MIXER_FCE_EN 0xa0000 126 #define SUN8I_MIXER_BWS_EN 0xa2000 127 #define SUN8I_MIXER_LTI_EN 0xa4000 128 #define SUN8I_MIXER_PEAK_EN 0xa6000 129 #define SUN8I_MIXER_ASE_EN 0xa8000 130 #define SUN8I_MIXER_FCC_EN 0xaa000 131 #define SUN8I_MIXER_DCSC_EN 0xb0000 132 133 #define SUN50I_MIXER_FCE_EN 0x70000 134 #define SUN50I_MIXER_PEAK_EN 0x70800 135 #define SUN50I_MIXER_LCTI_EN 0x71000 136 #define SUN50I_MIXER_BLS_EN 0x71800 137 #define SUN50I_MIXER_FCC_EN 0x72000 138 #define SUN50I_MIXER_DNS_EN 0x80000 139 #define SUN50I_MIXER_DRC_EN 0xa0000 140 #define SUN50I_MIXER_FMT_EN 0xa8000 141 #define SUN50I_MIXER_CDC0_EN 0xd0000 142 #define SUN50I_MIXER_CDC1_EN 0xd8000 143 144 enum { 145 /* First mixer or second mixer with VEP support. */ 146 CCSC_MIXER0_LAYOUT, 147 /* Second mixer without VEP support. */ 148 CCSC_MIXER1_LAYOUT, 149 /* First mixer with the MMIO layout found in the D1 SoC. */ 150 CCSC_D1_MIXER0_LAYOUT, 151 }; 152 153 /** 154 * struct sun8i_mixer_cfg - mixer HW configuration 155 * @vi_num: number of VI channels 156 * @ui_num: number of UI channels 157 * @scaler_mask: bitmask which tells which channel supports scaling 158 * First, scaler supports for VI channels is defined and after that, scaler 159 * support for UI channels. For example, if mixer has 2 VI channels without 160 * scaler and 2 UI channels with scaler, bitmask would be 0xC. 161 * @ccsc: select set of CCSC base addresses from the enumeration above. 162 * @mod_rate: module clock rate that needs to be set in order to have 163 * a functional block. 164 * @is_de3: true, if this is next gen display engine 3.0, false otherwise. 165 * @scaline_yuv: size of a scanline for VI scaler for YUV formats. 166 */ 167 struct sun8i_mixer_cfg { 168 int vi_num; 169 int ui_num; 170 int scaler_mask; 171 int ccsc; 172 unsigned long mod_rate; 173 unsigned int is_de3 : 1; 174 unsigned int scanline_yuv; 175 }; 176 177 struct sun8i_mixer { 178 struct sunxi_engine engine; 179 180 const struct sun8i_mixer_cfg *cfg; 181 182 struct reset_control *reset; 183 184 struct clk *bus_clk; 185 struct clk *mod_clk; 186 }; 187 188 static inline struct sun8i_mixer * 189 engine_to_sun8i_mixer(struct sunxi_engine *engine) 190 { 191 return container_of(engine, struct sun8i_mixer, engine); 192 } 193 194 static inline u32 195 sun8i_blender_base(struct sun8i_mixer *mixer) 196 { 197 return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; 198 } 199 200 static inline u32 201 sun8i_channel_base(struct sun8i_mixer *mixer, int channel) 202 { 203 if (mixer->cfg->is_de3) 204 return DE3_CH_BASE + channel * DE3_CH_SIZE; 205 else 206 return DE2_CH_BASE + channel * DE2_CH_SIZE; 207 } 208 209 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format); 210 #endif /* _SUN8I_MIXER_H_ */ 211