1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #ifndef _SUN8I_MIXER_H_ 7 #define _SUN8I_MIXER_H_ 8 9 #include <linux/clk.h> 10 #include <linux/regmap.h> 11 #include <linux/reset.h> 12 #include <drm/drm_plane.h> 13 14 #include "sunxi_engine.h" 15 16 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1)) 17 #define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x)) 18 19 #define SUN8I_MIXER_GLOBAL_CTL 0x0 20 #define SUN8I_MIXER_GLOBAL_STATUS 0x4 21 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8 22 #define SUN8I_MIXER_GLOBAL_SIZE 0xc 23 24 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) 25 26 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) 27 28 #define DE2_MIXER_UNIT_SIZE 0x6000 29 #define DE3_MIXER_UNIT_SIZE 0x3000 30 31 #define DE2_BLD_BASE 0x1000 32 #define DE2_CH_BASE 0x2000 33 #define DE2_CH_SIZE 0x1000 34 35 #define DE3_BLD_BASE 0x0800 36 #define DE3_CH_BASE 0x1000 37 #define DE3_CH_SIZE 0x0800 38 39 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) 40 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) 41 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) 42 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) 43 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) 44 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) 45 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) 46 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) 47 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) 48 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) 49 #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4) 50 #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x)) 51 #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) 52 #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) 53 #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) 54 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \ 55 ((base) + 0x110 + (layer) * 0x30 + (x) * 4) 56 57 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8) 58 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe) 59 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe) 60 61 /* colors are always in AARRGGBB format */ 62 #define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000 63 /* The following numbers are some still unknown magic numbers */ 64 #define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301 65 66 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) 67 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) 68 69 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) 70 71 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) 72 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff)) 73 74 #define SUN8I_MIXER_FBFMT_ARGB8888 0 75 #define SUN8I_MIXER_FBFMT_ABGR8888 1 76 #define SUN8I_MIXER_FBFMT_RGBA8888 2 77 #define SUN8I_MIXER_FBFMT_BGRA8888 3 78 #define SUN8I_MIXER_FBFMT_XRGB8888 4 79 #define SUN8I_MIXER_FBFMT_XBGR8888 5 80 #define SUN8I_MIXER_FBFMT_RGBX8888 6 81 #define SUN8I_MIXER_FBFMT_BGRX8888 7 82 #define SUN8I_MIXER_FBFMT_RGB888 8 83 #define SUN8I_MIXER_FBFMT_BGR888 9 84 #define SUN8I_MIXER_FBFMT_RGB565 10 85 #define SUN8I_MIXER_FBFMT_BGR565 11 86 #define SUN8I_MIXER_FBFMT_ARGB4444 12 87 #define SUN8I_MIXER_FBFMT_ABGR4444 13 88 #define SUN8I_MIXER_FBFMT_RGBA4444 14 89 #define SUN8I_MIXER_FBFMT_BGRA4444 15 90 #define SUN8I_MIXER_FBFMT_ARGB1555 16 91 #define SUN8I_MIXER_FBFMT_ABGR1555 17 92 #define SUN8I_MIXER_FBFMT_RGBA5551 18 93 #define SUN8I_MIXER_FBFMT_BGRA5551 19 94 #define SUN8I_MIXER_FBFMT_ARGB2101010 20 95 #define SUN8I_MIXER_FBFMT_ABGR2101010 21 96 #define SUN8I_MIXER_FBFMT_RGBA1010102 22 97 #define SUN8I_MIXER_FBFMT_BGRA1010102 23 98 99 #define SUN8I_MIXER_FBFMT_YUYV 0 100 #define SUN8I_MIXER_FBFMT_UYVY 1 101 #define SUN8I_MIXER_FBFMT_YVYU 2 102 #define SUN8I_MIXER_FBFMT_VYUY 3 103 #define SUN8I_MIXER_FBFMT_NV16 4 104 #define SUN8I_MIXER_FBFMT_NV61 5 105 #define SUN8I_MIXER_FBFMT_YUV422 6 106 /* format 7 doesn't exist */ 107 #define SUN8I_MIXER_FBFMT_NV12 8 108 #define SUN8I_MIXER_FBFMT_NV21 9 109 #define SUN8I_MIXER_FBFMT_YUV420 10 110 /* format 11 doesn't exist */ 111 /* format 12 is semi-planar YUV411 UVUV */ 112 /* format 13 is semi-planar YUV411 VUVU */ 113 #define SUN8I_MIXER_FBFMT_YUV411 14 114 /* format 15 doesn't exist */ 115 #define SUN8I_MIXER_FBFMT_P010_YUV 16 116 /* format 17 is P010 YVU */ 117 #define SUN8I_MIXER_FBFMT_P210_YUV 18 118 /* format 19 is P210 YVU */ 119 /* format 20 is packed YVU444 10-bit */ 120 /* format 21 is packed YUV444 10-bit */ 121 122 /* 123 * Sub-engines listed bellow are unused for now. The EN registers are here only 124 * to be used to disable these sub-engines. 125 */ 126 #define SUN8I_MIXER_FCE_EN 0xa0000 127 #define SUN8I_MIXER_BWS_EN 0xa2000 128 #define SUN8I_MIXER_LTI_EN 0xa4000 129 #define SUN8I_MIXER_PEAK_EN 0xa6000 130 #define SUN8I_MIXER_ASE_EN 0xa8000 131 #define SUN8I_MIXER_FCC_EN 0xaa000 132 #define SUN8I_MIXER_DCSC_EN 0xb0000 133 134 #define SUN50I_MIXER_FCE_EN 0x70000 135 #define SUN50I_MIXER_PEAK_EN 0x70800 136 #define SUN50I_MIXER_LCTI_EN 0x71000 137 #define SUN50I_MIXER_BLS_EN 0x71800 138 #define SUN50I_MIXER_FCC_EN 0x72000 139 #define SUN50I_MIXER_DNS_EN 0x80000 140 #define SUN50I_MIXER_DRC_EN 0xa0000 141 #define SUN50I_MIXER_FMT_EN 0xa8000 142 #define SUN50I_MIXER_CDC0_EN 0xd0000 143 #define SUN50I_MIXER_CDC1_EN 0xd8000 144 145 enum { 146 /* First mixer or second mixer with VEP support. */ 147 CCSC_MIXER0_LAYOUT, 148 /* Second mixer without VEP support. */ 149 CCSC_MIXER1_LAYOUT, 150 /* First mixer with the MMIO layout found in the D1 SoC. */ 151 CCSC_D1_MIXER0_LAYOUT, 152 }; 153 154 /** 155 * struct sun8i_mixer_cfg - mixer HW configuration 156 * @vi_num: number of VI channels 157 * @ui_num: number of UI channels 158 * @scaler_mask: bitmask which tells which channel supports scaling 159 * First, scaler supports for VI channels is defined and after that, scaler 160 * support for UI channels. For example, if mixer has 2 VI channels without 161 * scaler and 2 UI channels with scaler, bitmask would be 0xC. 162 * @ccsc: select set of CCSC base addresses from the enumeration above. 163 * @mod_rate: module clock rate that needs to be set in order to have 164 * a functional block. 165 * @is_de3: true, if this is next gen display engine 3.0, false otherwise. 166 * @scaline_yuv: size of a scanline for VI scaler for YUV formats. 167 */ 168 struct sun8i_mixer_cfg { 169 int vi_num; 170 int ui_num; 171 int scaler_mask; 172 int ccsc; 173 unsigned long mod_rate; 174 unsigned int is_de3 : 1; 175 unsigned int scanline_yuv; 176 }; 177 178 struct sun8i_mixer { 179 struct sunxi_engine engine; 180 181 const struct sun8i_mixer_cfg *cfg; 182 183 struct reset_control *reset; 184 185 struct clk *bus_clk; 186 struct clk *mod_clk; 187 }; 188 189 enum { 190 SUN8I_LAYER_TYPE_UI, 191 SUN8I_LAYER_TYPE_VI, 192 }; 193 194 struct sun8i_layer { 195 struct drm_plane plane; 196 struct sun8i_mixer *mixer; 197 int type; 198 int channel; 199 int overlay; 200 }; 201 202 static inline struct sun8i_layer * 203 plane_to_sun8i_layer(struct drm_plane *plane) 204 { 205 return container_of(plane, struct sun8i_layer, plane); 206 } 207 208 static inline struct sun8i_mixer * 209 engine_to_sun8i_mixer(struct sunxi_engine *engine) 210 { 211 return container_of(engine, struct sun8i_mixer, engine); 212 } 213 214 static inline u32 215 sun8i_blender_base(struct sun8i_mixer *mixer) 216 { 217 return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; 218 } 219 220 static inline u32 221 sun8i_channel_base(struct sun8i_mixer *mixer, int channel) 222 { 223 if (mixer->cfg->is_de3) 224 return DE3_CH_BASE + channel * DE3_CH_SIZE; 225 else 226 return DE2_CH_BASE + channel * DE2_CH_SIZE; 227 } 228 229 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format); 230 #endif /* _SUN8I_MIXER_H_ */ 231