1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #ifndef _SUN8I_MIXER_H_ 7 #define _SUN8I_MIXER_H_ 8 9 #include <linux/clk.h> 10 #include <linux/regmap.h> 11 #include <linux/reset.h> 12 #include <drm/drm_plane.h> 13 14 #include "sunxi_engine.h" 15 16 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1)) 17 #define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x)) 18 19 #define SUN8I_MIXER_GLOBAL_CTL 0x0 20 #define SUN8I_MIXER_GLOBAL_STATUS 0x4 21 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8 22 #define SUN8I_MIXER_GLOBAL_SIZE 0xc 23 24 #define SUN50I_MIXER_GLOBAL_SIZE 0x8 25 #define SUN50I_MIXER_GLOBAL_CLK 0xc 26 27 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) 28 29 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) 30 31 #define DE2_MIXER_UNIT_SIZE 0x6000 32 #define DE3_MIXER_UNIT_SIZE 0x3000 33 34 #define DE2_BLD_BASE 0x1000 35 #define DE2_CH_BASE 0x2000 36 #define DE2_CH_SIZE 0x1000 37 38 #define DE3_BLD_BASE 0x0800 39 #define DE3_CH_BASE 0x1000 40 #define DE3_CH_SIZE 0x0800 41 42 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) 43 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) 44 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) 45 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) 46 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) 47 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) 48 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) 49 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) 50 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) 51 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) 52 #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4) 53 #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x)) 54 #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) 55 #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) 56 #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) 57 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \ 58 ((base) + 0x110 + (layer) * 0x30 + (x) * 4) 59 60 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8) 61 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe) 62 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe) 63 64 /* colors are always in AARRGGBB format */ 65 #define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000 66 /* The following numbers are some still unknown magic numbers */ 67 #define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301 68 69 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) 70 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) 71 72 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) 73 74 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) 75 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff)) 76 77 #define SUN8I_MIXER_FBFMT_ARGB8888 0 78 #define SUN8I_MIXER_FBFMT_ABGR8888 1 79 #define SUN8I_MIXER_FBFMT_RGBA8888 2 80 #define SUN8I_MIXER_FBFMT_BGRA8888 3 81 #define SUN8I_MIXER_FBFMT_XRGB8888 4 82 #define SUN8I_MIXER_FBFMT_XBGR8888 5 83 #define SUN8I_MIXER_FBFMT_RGBX8888 6 84 #define SUN8I_MIXER_FBFMT_BGRX8888 7 85 #define SUN8I_MIXER_FBFMT_RGB888 8 86 #define SUN8I_MIXER_FBFMT_BGR888 9 87 #define SUN8I_MIXER_FBFMT_RGB565 10 88 #define SUN8I_MIXER_FBFMT_BGR565 11 89 #define SUN8I_MIXER_FBFMT_ARGB4444 12 90 #define SUN8I_MIXER_FBFMT_ABGR4444 13 91 #define SUN8I_MIXER_FBFMT_RGBA4444 14 92 #define SUN8I_MIXER_FBFMT_BGRA4444 15 93 #define SUN8I_MIXER_FBFMT_ARGB1555 16 94 #define SUN8I_MIXER_FBFMT_ABGR1555 17 95 #define SUN8I_MIXER_FBFMT_RGBA5551 18 96 #define SUN8I_MIXER_FBFMT_BGRA5551 19 97 #define SUN8I_MIXER_FBFMT_ARGB2101010 20 98 #define SUN8I_MIXER_FBFMT_ABGR2101010 21 99 #define SUN8I_MIXER_FBFMT_RGBA1010102 22 100 #define SUN8I_MIXER_FBFMT_BGRA1010102 23 101 102 #define SUN8I_MIXER_FBFMT_YUYV 0 103 #define SUN8I_MIXER_FBFMT_UYVY 1 104 #define SUN8I_MIXER_FBFMT_YVYU 2 105 #define SUN8I_MIXER_FBFMT_VYUY 3 106 #define SUN8I_MIXER_FBFMT_NV16 4 107 #define SUN8I_MIXER_FBFMT_NV61 5 108 #define SUN8I_MIXER_FBFMT_YUV422 6 109 /* format 7 doesn't exist */ 110 #define SUN8I_MIXER_FBFMT_NV12 8 111 #define SUN8I_MIXER_FBFMT_NV21 9 112 #define SUN8I_MIXER_FBFMT_YUV420 10 113 /* format 11 doesn't exist */ 114 /* format 12 is semi-planar YUV411 UVUV */ 115 /* format 13 is semi-planar YUV411 VUVU */ 116 #define SUN8I_MIXER_FBFMT_YUV411 14 117 /* format 15 doesn't exist */ 118 #define SUN8I_MIXER_FBFMT_P010_YUV 16 119 /* format 17 is P010 YVU */ 120 #define SUN8I_MIXER_FBFMT_P210_YUV 18 121 /* format 19 is P210 YVU */ 122 /* format 20 is packed YVU444 10-bit */ 123 /* format 21 is packed YUV444 10-bit */ 124 125 /* 126 * Sub-engines listed bellow are unused for now. The EN registers are here only 127 * to be used to disable these sub-engines. 128 */ 129 #define SUN8I_MIXER_FCE_EN 0xa0000 130 #define SUN8I_MIXER_BWS_EN 0xa2000 131 #define SUN8I_MIXER_LTI_EN 0xa4000 132 #define SUN8I_MIXER_PEAK_EN 0xa6000 133 #define SUN8I_MIXER_ASE_EN 0xa8000 134 #define SUN8I_MIXER_FCC_EN 0xaa000 135 #define SUN8I_MIXER_DCSC_EN 0xb0000 136 137 #define SUN50I_MIXER_FCE_EN 0x70000 138 #define SUN50I_MIXER_PEAK_EN 0x70800 139 #define SUN50I_MIXER_LCTI_EN 0x71000 140 #define SUN50I_MIXER_BLS_EN 0x71800 141 #define SUN50I_MIXER_FCC_EN 0x72000 142 #define SUN50I_MIXER_DNS_EN 0x80000 143 #define SUN50I_MIXER_DRC_EN 0xa0000 144 #define SUN50I_MIXER_FMT_EN 0xa8000 145 #define SUN50I_MIXER_CDC0_EN 0xd0000 146 #define SUN50I_MIXER_CDC1_EN 0xd8000 147 148 enum { 149 /* First mixer or second mixer with VEP support. */ 150 CCSC_MIXER0_LAYOUT, 151 /* Second mixer without VEP support. */ 152 CCSC_MIXER1_LAYOUT, 153 /* First mixer with the MMIO layout found in the D1 SoC. */ 154 CCSC_D1_MIXER0_LAYOUT, 155 }; 156 157 enum sun8i_mixer_type { 158 SUN8I_MIXER_DE2, 159 SUN8I_MIXER_DE3, 160 SUN8I_MIXER_DE33, 161 }; 162 163 /** 164 * struct sun8i_mixer_cfg - mixer HW configuration 165 * @vi_num: number of VI channels 166 * @ui_num: number of UI channels 167 * @scaler_mask: bitmask which tells which channel supports scaling 168 * First, scaler supports for VI channels is defined and after that, scaler 169 * support for UI channels. For example, if mixer has 2 VI channels without 170 * scaler and 2 UI channels with scaler, bitmask would be 0xC. 171 * @ccsc: select set of CCSC base addresses from the enumeration above. 172 * @mod_rate: module clock rate that needs to be set in order to have 173 * a functional block. 174 * @de_type: sun8i_mixer_type enum representing the display engine generation. 175 * @scaline_yuv: size of a scanline for VI scaler for YUV formats. 176 * @map: channel map for DE variants processing YUV separately (DE33) 177 */ 178 struct sun8i_mixer_cfg { 179 int vi_num; 180 int ui_num; 181 int scaler_mask; 182 int ccsc; 183 unsigned long mod_rate; 184 unsigned int de_type; 185 unsigned int scanline_yuv; 186 unsigned int map[6]; 187 }; 188 189 struct sun8i_mixer { 190 struct sunxi_engine engine; 191 192 const struct sun8i_mixer_cfg *cfg; 193 194 struct reset_control *reset; 195 196 struct clk *bus_clk; 197 struct clk *mod_clk; 198 199 struct regmap *top_regs; 200 struct regmap *disp_regs; 201 }; 202 203 enum { 204 SUN8I_LAYER_TYPE_UI, 205 SUN8I_LAYER_TYPE_VI, 206 }; 207 208 struct sun8i_layer { 209 struct drm_plane plane; 210 struct sun8i_mixer *mixer; 211 int type; 212 int channel; 213 int overlay; 214 }; 215 216 static inline struct sun8i_layer * 217 plane_to_sun8i_layer(struct drm_plane *plane) 218 { 219 return container_of(plane, struct sun8i_layer, plane); 220 } 221 222 static inline struct sun8i_mixer * 223 engine_to_sun8i_mixer(struct sunxi_engine *engine) 224 { 225 return container_of(engine, struct sun8i_mixer, engine); 226 } 227 228 static inline u32 229 sun8i_blender_base(struct sun8i_mixer *mixer) 230 { 231 return mixer->cfg->de_type == SUN8I_MIXER_DE3 ? DE3_BLD_BASE : DE2_BLD_BASE; 232 } 233 234 static inline struct regmap * 235 sun8i_blender_regmap(struct sun8i_mixer *mixer) 236 { 237 return mixer->cfg->de_type == SUN8I_MIXER_DE33 ? 238 mixer->disp_regs : mixer->engine.regs; 239 } 240 241 static inline u32 242 sun8i_channel_base(struct sun8i_mixer *mixer, int channel) 243 { 244 if (mixer->cfg->de_type == SUN8I_MIXER_DE33) 245 return mixer->cfg->map[channel] * 0x20000 + DE2_CH_SIZE; 246 else if (mixer->cfg->de_type == SUN8I_MIXER_DE3) 247 return DE3_CH_BASE + channel * DE3_CH_SIZE; 248 else 249 return DE2_CH_BASE + channel * DE2_CH_SIZE; 250 } 251 252 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format); 253 #endif /* _SUN8I_MIXER_H_ */ 254