1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * Based on sun4i_backend.c, which is: 6 * Copyright (C) 2015 Free Electrons 7 * Copyright (C) 2015 NextThing Co 8 */ 9 10 #include <linux/component.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_graph.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_gem_dma_helper.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 27 #include "sun4i_drv.h" 28 #include "sun8i_mixer.h" 29 #include "sun8i_ui_layer.h" 30 #include "sun8i_vi_layer.h" 31 #include "sunxi_engine.h" 32 33 struct de2_fmt_info { 34 u32 drm_fmt; 35 u32 de2_fmt; 36 }; 37 38 static const struct de2_fmt_info de2_formats[] = { 39 { 40 .drm_fmt = DRM_FORMAT_ARGB8888, 41 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888, 42 }, 43 { 44 .drm_fmt = DRM_FORMAT_ABGR8888, 45 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888, 46 }, 47 { 48 .drm_fmt = DRM_FORMAT_RGBA8888, 49 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888, 50 }, 51 { 52 .drm_fmt = DRM_FORMAT_BGRA8888, 53 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888, 54 }, 55 { 56 .drm_fmt = DRM_FORMAT_XRGB8888, 57 .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888, 58 }, 59 { 60 .drm_fmt = DRM_FORMAT_XBGR8888, 61 .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888, 62 }, 63 { 64 .drm_fmt = DRM_FORMAT_RGBX8888, 65 .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888, 66 }, 67 { 68 .drm_fmt = DRM_FORMAT_BGRX8888, 69 .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888, 70 }, 71 { 72 .drm_fmt = DRM_FORMAT_RGB888, 73 .de2_fmt = SUN8I_MIXER_FBFMT_RGB888, 74 }, 75 { 76 .drm_fmt = DRM_FORMAT_BGR888, 77 .de2_fmt = SUN8I_MIXER_FBFMT_BGR888, 78 }, 79 { 80 .drm_fmt = DRM_FORMAT_RGB565, 81 .de2_fmt = SUN8I_MIXER_FBFMT_RGB565, 82 }, 83 { 84 .drm_fmt = DRM_FORMAT_BGR565, 85 .de2_fmt = SUN8I_MIXER_FBFMT_BGR565, 86 }, 87 { 88 .drm_fmt = DRM_FORMAT_ARGB4444, 89 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444, 90 }, 91 { 92 /* for DE2 VI layer which ignores alpha */ 93 .drm_fmt = DRM_FORMAT_XRGB4444, 94 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444, 95 }, 96 { 97 .drm_fmt = DRM_FORMAT_ABGR4444, 98 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444, 99 }, 100 { 101 /* for DE2 VI layer which ignores alpha */ 102 .drm_fmt = DRM_FORMAT_XBGR4444, 103 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444, 104 }, 105 { 106 .drm_fmt = DRM_FORMAT_RGBA4444, 107 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444, 108 }, 109 { 110 /* for DE2 VI layer which ignores alpha */ 111 .drm_fmt = DRM_FORMAT_RGBX4444, 112 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444, 113 }, 114 { 115 .drm_fmt = DRM_FORMAT_BGRA4444, 116 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444, 117 }, 118 { 119 /* for DE2 VI layer which ignores alpha */ 120 .drm_fmt = DRM_FORMAT_BGRX4444, 121 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444, 122 }, 123 { 124 .drm_fmt = DRM_FORMAT_ARGB1555, 125 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555, 126 }, 127 { 128 /* for DE2 VI layer which ignores alpha */ 129 .drm_fmt = DRM_FORMAT_XRGB1555, 130 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555, 131 }, 132 { 133 .drm_fmt = DRM_FORMAT_ABGR1555, 134 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555, 135 }, 136 { 137 /* for DE2 VI layer which ignores alpha */ 138 .drm_fmt = DRM_FORMAT_XBGR1555, 139 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555, 140 }, 141 { 142 .drm_fmt = DRM_FORMAT_RGBA5551, 143 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551, 144 }, 145 { 146 /* for DE2 VI layer which ignores alpha */ 147 .drm_fmt = DRM_FORMAT_RGBX5551, 148 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551, 149 }, 150 { 151 .drm_fmt = DRM_FORMAT_BGRA5551, 152 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551, 153 }, 154 { 155 /* for DE2 VI layer which ignores alpha */ 156 .drm_fmt = DRM_FORMAT_BGRX5551, 157 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551, 158 }, 159 { 160 .drm_fmt = DRM_FORMAT_ARGB2101010, 161 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010, 162 }, 163 { 164 .drm_fmt = DRM_FORMAT_ABGR2101010, 165 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010, 166 }, 167 { 168 .drm_fmt = DRM_FORMAT_RGBA1010102, 169 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102, 170 }, 171 { 172 .drm_fmt = DRM_FORMAT_BGRA1010102, 173 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102, 174 }, 175 { 176 .drm_fmt = DRM_FORMAT_UYVY, 177 .de2_fmt = SUN8I_MIXER_FBFMT_UYVY, 178 }, 179 { 180 .drm_fmt = DRM_FORMAT_VYUY, 181 .de2_fmt = SUN8I_MIXER_FBFMT_VYUY, 182 }, 183 { 184 .drm_fmt = DRM_FORMAT_YUYV, 185 .de2_fmt = SUN8I_MIXER_FBFMT_YUYV, 186 }, 187 { 188 .drm_fmt = DRM_FORMAT_YVYU, 189 .de2_fmt = SUN8I_MIXER_FBFMT_YVYU, 190 }, 191 { 192 .drm_fmt = DRM_FORMAT_NV16, 193 .de2_fmt = SUN8I_MIXER_FBFMT_NV16, 194 }, 195 { 196 .drm_fmt = DRM_FORMAT_NV61, 197 .de2_fmt = SUN8I_MIXER_FBFMT_NV61, 198 }, 199 { 200 .drm_fmt = DRM_FORMAT_NV12, 201 .de2_fmt = SUN8I_MIXER_FBFMT_NV12, 202 }, 203 { 204 .drm_fmt = DRM_FORMAT_NV21, 205 .de2_fmt = SUN8I_MIXER_FBFMT_NV21, 206 }, 207 { 208 .drm_fmt = DRM_FORMAT_YUV422, 209 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422, 210 }, 211 { 212 .drm_fmt = DRM_FORMAT_YUV420, 213 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420, 214 }, 215 { 216 .drm_fmt = DRM_FORMAT_YUV411, 217 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411, 218 }, 219 { 220 .drm_fmt = DRM_FORMAT_YVU422, 221 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422, 222 }, 223 { 224 .drm_fmt = DRM_FORMAT_YVU420, 225 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420, 226 }, 227 { 228 .drm_fmt = DRM_FORMAT_YVU411, 229 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411, 230 }, 231 { 232 .drm_fmt = DRM_FORMAT_P010, 233 .de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV, 234 }, 235 { 236 .drm_fmt = DRM_FORMAT_P210, 237 .de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV, 238 }, 239 }; 240 241 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format) 242 { 243 unsigned int i; 244 245 for (i = 0; i < ARRAY_SIZE(de2_formats); ++i) 246 if (de2_formats[i].drm_fmt == format) { 247 *hw_format = de2_formats[i].de2_fmt; 248 return 0; 249 } 250 251 return -EINVAL; 252 } 253 254 static void sun8i_layer_enable(struct sun8i_layer *layer, bool enable) 255 { 256 u32 ch_base = sun8i_channel_base(layer->mixer, layer->channel); 257 u32 val, reg, mask; 258 259 if (layer->type == SUN8I_LAYER_TYPE_UI) { 260 val = enable ? SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN : 0; 261 mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; 262 reg = SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay); 263 } else { 264 val = enable ? SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN : 0; 265 mask = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN; 266 reg = SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay); 267 } 268 269 regmap_update_bits(layer->mixer->engine.regs, reg, mask, val); 270 } 271 272 static void sun8i_mixer_commit(struct sunxi_engine *engine, 273 struct drm_crtc *crtc, 274 struct drm_atomic_state *state) 275 { 276 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); 277 u32 bld_base = sun8i_blender_base(mixer); 278 struct regmap *bld_regs = sun8i_blender_regmap(mixer); 279 struct drm_plane_state *plane_state; 280 struct drm_plane *plane; 281 u32 route = 0, pipe_en = 0; 282 283 DRM_DEBUG_DRIVER("Committing changes\n"); 284 285 drm_for_each_plane(plane, state->dev) { 286 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); 287 bool enable; 288 int zpos; 289 290 if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer != mixer) 291 continue; 292 293 plane_state = drm_atomic_get_new_plane_state(state, plane); 294 if (!plane_state) 295 plane_state = plane->state; 296 297 enable = plane_state->crtc && plane_state->visible; 298 zpos = plane_state->normalized_zpos; 299 300 DRM_DEBUG_DRIVER(" plane %d: chan=%d ovl=%d en=%d zpos=%d\n", 301 plane->base.id, layer->channel, layer->overlay, 302 enable, zpos); 303 304 /* 305 * We always update the layer enable bit, because it can clear 306 * spontaneously for unknown reasons. 307 */ 308 sun8i_layer_enable(layer, enable); 309 310 if (!enable) 311 continue; 312 313 /* Route layer to pipe based on zpos */ 314 route |= layer->channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); 315 pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); 316 } 317 318 regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); 319 regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), 320 pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); 321 322 if (mixer->cfg->de_type != SUN8I_MIXER_DE33) 323 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, 324 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); 325 } 326 327 static struct drm_plane **sun8i_layers_init(struct drm_device *drm, 328 struct sunxi_engine *engine) 329 { 330 struct drm_plane **planes; 331 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); 332 int i; 333 334 planes = devm_kcalloc(drm->dev, 335 mixer->cfg->vi_num + mixer->cfg->ui_num + 1, 336 sizeof(*planes), GFP_KERNEL); 337 if (!planes) 338 return ERR_PTR(-ENOMEM); 339 340 for (i = 0; i < mixer->cfg->vi_num; i++) { 341 struct sun8i_layer *layer; 342 343 layer = sun8i_vi_layer_init_one(drm, mixer, i); 344 if (IS_ERR(layer)) { 345 dev_err(drm->dev, 346 "Couldn't initialize overlay plane\n"); 347 return ERR_CAST(layer); 348 } 349 350 planes[i] = &layer->plane; 351 } 352 353 for (i = 0; i < mixer->cfg->ui_num; i++) { 354 struct sun8i_layer *layer; 355 356 layer = sun8i_ui_layer_init_one(drm, mixer, i); 357 if (IS_ERR(layer)) { 358 dev_err(drm->dev, "Couldn't initialize %s plane\n", 359 i ? "overlay" : "primary"); 360 return ERR_CAST(layer); 361 } 362 363 planes[mixer->cfg->vi_num + i] = &layer->plane; 364 } 365 366 return planes; 367 } 368 369 static void sun8i_mixer_mode_set(struct sunxi_engine *engine, 370 const struct drm_display_mode *mode) 371 { 372 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); 373 struct regmap *bld_regs; 374 u32 bld_base, size, val; 375 bool interlaced; 376 377 bld_base = sun8i_blender_base(mixer); 378 bld_regs = sun8i_blender_regmap(mixer); 379 interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 380 size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); 381 382 DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", 383 mode->hdisplay, mode->vdisplay); 384 385 if (mixer->cfg->de_type == SUN8I_MIXER_DE33) 386 regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_SIZE, size); 387 else 388 regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size); 389 390 regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); 391 392 if (interlaced) 393 val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; 394 else 395 val = 0; 396 397 regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), 398 SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); 399 400 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", 401 interlaced ? "on" : "off"); 402 } 403 404 static const struct sunxi_engine_ops sun8i_engine_ops = { 405 .commit = sun8i_mixer_commit, 406 .layers_init = sun8i_layers_init, 407 .mode_set = sun8i_mixer_mode_set, 408 }; 409 410 static const struct regmap_config sun8i_mixer_regmap_config = { 411 .name = "layers", 412 .reg_bits = 32, 413 .val_bits = 32, 414 .reg_stride = 4, 415 .max_register = 0xffffc, /* guessed */ 416 }; 417 418 static const struct regmap_config sun8i_top_regmap_config = { 419 .name = "top", 420 .reg_bits = 32, 421 .val_bits = 32, 422 .reg_stride = 4, 423 .max_register = 0x3c, 424 }; 425 426 static const struct regmap_config sun8i_disp_regmap_config = { 427 .name = "display", 428 .reg_bits = 32, 429 .val_bits = 32, 430 .reg_stride = 4, 431 .max_register = 0x20000, 432 }; 433 434 static int sun8i_mixer_of_get_id(struct device_node *node) 435 { 436 struct device_node *ep, *remote; 437 struct of_endpoint of_ep; 438 439 /* Output port is 1, and we want the first endpoint. */ 440 ep = of_graph_get_endpoint_by_regs(node, 1, -1); 441 if (!ep) 442 return -EINVAL; 443 444 remote = of_graph_get_remote_endpoint(ep); 445 of_node_put(ep); 446 if (!remote) 447 return -EINVAL; 448 449 of_graph_parse_endpoint(remote, &of_ep); 450 of_node_put(remote); 451 return of_ep.id; 452 } 453 454 static void sun8i_mixer_init(struct sun8i_mixer *mixer) 455 { 456 struct regmap *top_regs, *disp_regs; 457 unsigned int base = sun8i_blender_base(mixer); 458 int plane_cnt, i; 459 460 if (mixer->cfg->de_type == SUN8I_MIXER_DE33) { 461 top_regs = mixer->top_regs; 462 disp_regs = mixer->disp_regs; 463 } else { 464 top_regs = mixer->engine.regs; 465 disp_regs = mixer->engine.regs; 466 } 467 468 /* Enable the mixer */ 469 regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL, 470 SUN8I_MIXER_GLOBAL_CTL_RT_EN); 471 472 if (mixer->cfg->de_type == SUN8I_MIXER_DE33) 473 regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1); 474 475 /* Set background color to black */ 476 regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base), 477 SUN8I_MIXER_BLEND_COLOR_BLACK); 478 479 /* 480 * Set fill color of bottom plane to black. Generally not needed 481 * except when VI plane is at bottom (zpos = 0) and enabled. 482 */ 483 regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), 484 SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); 485 regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), 486 SUN8I_MIXER_BLEND_COLOR_BLACK); 487 488 plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; 489 for (i = 0; i < plane_cnt; i++) 490 regmap_write(disp_regs, 491 SUN8I_MIXER_BLEND_MODE(base, i), 492 SUN8I_MIXER_BLEND_MODE_DEF); 493 494 regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), 495 SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); 496 } 497 498 static int sun8i_mixer_bind(struct device *dev, struct device *master, 499 void *data) 500 { 501 struct platform_device *pdev = to_platform_device(dev); 502 struct drm_device *drm = data; 503 struct sun4i_drv *drv = drm->dev_private; 504 struct sun8i_mixer *mixer; 505 void __iomem *regs; 506 int i, ret; 507 508 /* 509 * The mixer uses single 32-bit register to store memory 510 * addresses, so that it cannot deal with 64-bit memory 511 * addresses. 512 * Restrict the DMA mask so that the mixer won't be 513 * allocated some memory that is too high. 514 */ 515 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 516 if (ret) { 517 dev_err(dev, "Cannot do 32-bit DMA.\n"); 518 return ret; 519 } 520 521 mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); 522 if (!mixer) 523 return -ENOMEM; 524 dev_set_drvdata(dev, mixer); 525 mixer->engine.ops = &sun8i_engine_ops; 526 mixer->engine.node = dev->of_node; 527 528 if (of_property_present(dev->of_node, "iommus")) { 529 /* 530 * This assume we have the same DMA constraints for 531 * all our the mixers in our pipeline. This sounds 532 * bad, but it has always been the case for us, and 533 * DRM doesn't do per-device allocation either, so we 534 * would need to fix DRM first... 535 */ 536 ret = of_dma_configure(drm->dev, dev->of_node, true); 537 if (ret) 538 return ret; 539 } 540 541 /* 542 * While this function can fail, we shouldn't do anything 543 * if this happens. Some early DE2 DT entries don't provide 544 * mixer id but work nevertheless because matching between 545 * TCON and mixer is done by comparing node pointers (old 546 * way) instead comparing ids. If this function fails and 547 * id is needed, it will fail during id matching anyway. 548 */ 549 mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node); 550 551 mixer->cfg = of_device_get_match_data(dev); 552 if (!mixer->cfg) 553 return -EINVAL; 554 555 regs = devm_platform_ioremap_resource(pdev, 0); 556 if (IS_ERR(regs)) 557 return PTR_ERR(regs); 558 559 mixer->engine.regs = devm_regmap_init_mmio(dev, regs, 560 &sun8i_mixer_regmap_config); 561 if (IS_ERR(mixer->engine.regs)) { 562 dev_err(dev, "Couldn't create the mixer regmap\n"); 563 return PTR_ERR(mixer->engine.regs); 564 } 565 566 if (mixer->cfg->de_type == SUN8I_MIXER_DE33) { 567 regs = devm_platform_ioremap_resource_byname(pdev, "top"); 568 if (IS_ERR(regs)) 569 return PTR_ERR(regs); 570 571 mixer->top_regs = devm_regmap_init_mmio(dev, regs, 572 &sun8i_top_regmap_config); 573 if (IS_ERR(mixer->top_regs)) { 574 dev_err(dev, "Couldn't create the top regmap\n"); 575 return PTR_ERR(mixer->top_regs); 576 } 577 578 regs = devm_platform_ioremap_resource_byname(pdev, "display"); 579 if (IS_ERR(regs)) 580 return PTR_ERR(regs); 581 582 mixer->disp_regs = devm_regmap_init_mmio(dev, regs, 583 &sun8i_disp_regmap_config); 584 if (IS_ERR(mixer->disp_regs)) { 585 dev_err(dev, "Couldn't create the disp regmap\n"); 586 return PTR_ERR(mixer->disp_regs); 587 } 588 } 589 590 mixer->reset = devm_reset_control_get(dev, NULL); 591 if (IS_ERR(mixer->reset)) { 592 dev_err(dev, "Couldn't get our reset line\n"); 593 return PTR_ERR(mixer->reset); 594 } 595 596 ret = reset_control_deassert(mixer->reset); 597 if (ret) { 598 dev_err(dev, "Couldn't deassert our reset line\n"); 599 return ret; 600 } 601 602 mixer->bus_clk = devm_clk_get(dev, "bus"); 603 if (IS_ERR(mixer->bus_clk)) { 604 dev_err(dev, "Couldn't get the mixer bus clock\n"); 605 ret = PTR_ERR(mixer->bus_clk); 606 goto err_assert_reset; 607 } 608 clk_prepare_enable(mixer->bus_clk); 609 610 mixer->mod_clk = devm_clk_get(dev, "mod"); 611 if (IS_ERR(mixer->mod_clk)) { 612 dev_err(dev, "Couldn't get the mixer module clock\n"); 613 ret = PTR_ERR(mixer->mod_clk); 614 goto err_disable_bus_clk; 615 } 616 617 /* 618 * It seems that we need to enforce that rate for whatever 619 * reason for the mixer to be functional. Make sure it's the 620 * case. 621 */ 622 if (mixer->cfg->mod_rate) 623 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate); 624 625 clk_prepare_enable(mixer->mod_clk); 626 627 list_add_tail(&mixer->engine.list, &drv->engine_list); 628 629 /* Reset registers and disable unused sub-engines */ 630 if (mixer->cfg->de_type == SUN8I_MIXER_DE3) { 631 for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) 632 regmap_write(mixer->engine.regs, i, 0); 633 634 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0); 635 regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0); 636 regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0); 637 regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0); 638 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0); 639 regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0); 640 regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0); 641 regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); 642 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); 643 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); 644 } else if (mixer->cfg->de_type == SUN8I_MIXER_DE2) { 645 for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) 646 regmap_write(mixer->engine.regs, i, 0); 647 648 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0); 649 regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0); 650 regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0); 651 regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0); 652 regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0); 653 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0); 654 regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); 655 } 656 657 sun8i_mixer_init(mixer); 658 659 return 0; 660 661 err_disable_bus_clk: 662 clk_disable_unprepare(mixer->bus_clk); 663 err_assert_reset: 664 reset_control_assert(mixer->reset); 665 return ret; 666 } 667 668 static void sun8i_mixer_unbind(struct device *dev, struct device *master, 669 void *data) 670 { 671 struct sun8i_mixer *mixer = dev_get_drvdata(dev); 672 673 list_del(&mixer->engine.list); 674 675 clk_disable_unprepare(mixer->mod_clk); 676 clk_disable_unprepare(mixer->bus_clk); 677 reset_control_assert(mixer->reset); 678 } 679 680 static const struct component_ops sun8i_mixer_ops = { 681 .bind = sun8i_mixer_bind, 682 .unbind = sun8i_mixer_unbind, 683 }; 684 685 static int sun8i_mixer_probe(struct platform_device *pdev) 686 { 687 return component_add(&pdev->dev, &sun8i_mixer_ops); 688 } 689 690 static void sun8i_mixer_remove(struct platform_device *pdev) 691 { 692 component_del(&pdev->dev, &sun8i_mixer_ops); 693 } 694 695 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { 696 .ccsc = CCSC_MIXER0_LAYOUT, 697 .de_type = SUN8I_MIXER_DE2, 698 .scaler_mask = 0xf, 699 .scanline_yuv = 2048, 700 .ui_num = 3, 701 .vi_num = 1, 702 }; 703 704 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { 705 .ccsc = CCSC_MIXER1_LAYOUT, 706 .de_type = SUN8I_MIXER_DE2, 707 .scaler_mask = 0x3, 708 .scanline_yuv = 2048, 709 .ui_num = 1, 710 .vi_num = 1, 711 }; 712 713 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { 714 .ccsc = CCSC_MIXER0_LAYOUT, 715 .de_type = SUN8I_MIXER_DE2, 716 .mod_rate = 432000000, 717 .scaler_mask = 0xf, 718 .scanline_yuv = 2048, 719 .ui_num = 3, 720 .vi_num = 1, 721 }; 722 723 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { 724 .ccsc = CCSC_MIXER0_LAYOUT, 725 .de_type = SUN8I_MIXER_DE2, 726 .mod_rate = 297000000, 727 .scaler_mask = 0xf, 728 .scanline_yuv = 2048, 729 .ui_num = 3, 730 .vi_num = 1, 731 }; 732 733 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { 734 .ccsc = CCSC_MIXER1_LAYOUT, 735 .de_type = SUN8I_MIXER_DE2, 736 .mod_rate = 297000000, 737 .scaler_mask = 0x3, 738 .scanline_yuv = 2048, 739 .ui_num = 1, 740 .vi_num = 1, 741 }; 742 743 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { 744 .de_type = SUN8I_MIXER_DE2, 745 .vi_num = 2, 746 .ui_num = 1, 747 .scaler_mask = 0x3, 748 .scanline_yuv = 2048, 749 .ccsc = CCSC_MIXER0_LAYOUT, 750 .mod_rate = 150000000, 751 }; 752 753 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { 754 .ccsc = CCSC_D1_MIXER0_LAYOUT, 755 .de_type = SUN8I_MIXER_DE2, 756 .mod_rate = 297000000, 757 .scaler_mask = 0x3, 758 .scanline_yuv = 2048, 759 .ui_num = 1, 760 .vi_num = 1, 761 }; 762 763 static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { 764 .ccsc = CCSC_MIXER1_LAYOUT, 765 .de_type = SUN8I_MIXER_DE2, 766 .mod_rate = 297000000, 767 .scaler_mask = 0x1, 768 .scanline_yuv = 1024, 769 .ui_num = 0, 770 .vi_num = 1, 771 }; 772 773 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { 774 .ccsc = CCSC_MIXER0_LAYOUT, 775 .de_type = SUN8I_MIXER_DE2, 776 .mod_rate = 297000000, 777 .scaler_mask = 0xf, 778 .scanline_yuv = 4096, 779 .ui_num = 3, 780 .vi_num = 1, 781 }; 782 783 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { 784 .ccsc = CCSC_MIXER1_LAYOUT, 785 .de_type = SUN8I_MIXER_DE2, 786 .mod_rate = 297000000, 787 .scaler_mask = 0x3, 788 .scanline_yuv = 2048, 789 .ui_num = 1, 790 .vi_num = 1, 791 }; 792 793 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { 794 .ccsc = CCSC_MIXER0_LAYOUT, 795 .de_type = SUN8I_MIXER_DE3, 796 .mod_rate = 600000000, 797 .scaler_mask = 0xf, 798 .scanline_yuv = 4096, 799 .ui_num = 3, 800 .vi_num = 1, 801 }; 802 803 static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = { 804 .ccsc = CCSC_MIXER0_LAYOUT, 805 .de_type = SUN8I_MIXER_DE33, 806 .mod_rate = 600000000, 807 .scaler_mask = 0xf, 808 .scanline_yuv = 4096, 809 .ui_num = 3, 810 .vi_num = 1, 811 .map = {0, 6, 7, 8}, 812 }; 813 814 static const struct of_device_id sun8i_mixer_of_table[] = { 815 { 816 .compatible = "allwinner,sun8i-a83t-de2-mixer-0", 817 .data = &sun8i_a83t_mixer0_cfg, 818 }, 819 { 820 .compatible = "allwinner,sun8i-a83t-de2-mixer-1", 821 .data = &sun8i_a83t_mixer1_cfg, 822 }, 823 { 824 .compatible = "allwinner,sun8i-h3-de2-mixer-0", 825 .data = &sun8i_h3_mixer0_cfg, 826 }, 827 { 828 .compatible = "allwinner,sun8i-r40-de2-mixer-0", 829 .data = &sun8i_r40_mixer0_cfg, 830 }, 831 { 832 .compatible = "allwinner,sun8i-r40-de2-mixer-1", 833 .data = &sun8i_r40_mixer1_cfg, 834 }, 835 { 836 .compatible = "allwinner,sun8i-v3s-de2-mixer", 837 .data = &sun8i_v3s_mixer_cfg, 838 }, 839 { 840 .compatible = "allwinner,sun20i-d1-de2-mixer-0", 841 .data = &sun20i_d1_mixer0_cfg, 842 }, 843 { 844 .compatible = "allwinner,sun20i-d1-de2-mixer-1", 845 .data = &sun20i_d1_mixer1_cfg, 846 }, 847 { 848 .compatible = "allwinner,sun50i-a64-de2-mixer-0", 849 .data = &sun50i_a64_mixer0_cfg, 850 }, 851 { 852 .compatible = "allwinner,sun50i-a64-de2-mixer-1", 853 .data = &sun50i_a64_mixer1_cfg, 854 }, 855 { 856 .compatible = "allwinner,sun50i-h6-de3-mixer-0", 857 .data = &sun50i_h6_mixer0_cfg, 858 }, 859 { 860 .compatible = "allwinner,sun50i-h616-de33-mixer-0", 861 .data = &sun50i_h616_mixer0_cfg, 862 }, 863 { } 864 }; 865 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table); 866 867 static struct platform_driver sun8i_mixer_platform_driver = { 868 .probe = sun8i_mixer_probe, 869 .remove = sun8i_mixer_remove, 870 .driver = { 871 .name = "sun8i-mixer", 872 .of_match_table = sun8i_mixer_of_table, 873 }, 874 }; 875 module_platform_driver(sun8i_mixer_platform_driver); 876 877 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); 878 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver"); 879 MODULE_LICENSE("GPL"); 880