1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Free Electrons 4 * Copyright (C) 2015 NextThing Co 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/ioport.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_modes.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include <uapi/drm/drm_mode.h> 31 32 #include "sun4i_crtc.h" 33 #include "sun4i_dotclock.h" 34 #include "sun4i_drv.h" 35 #include "sun4i_lvds.h" 36 #include "sun4i_rgb.h" 37 #include "sun4i_tcon.h" 38 #include "sun6i_mipi_dsi.h" 39 #include "sun8i_tcon_top.h" 40 #include "sunxi_engine.h" 41 42 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) 43 { 44 struct drm_connector *connector; 45 struct drm_connector_list_iter iter; 46 47 drm_connector_list_iter_begin(encoder->dev, &iter); 48 drm_for_each_connector_iter(connector, &iter) 49 if (connector->encoder == encoder) { 50 drm_connector_list_iter_end(&iter); 51 return connector; 52 } 53 drm_connector_list_iter_end(&iter); 54 55 return NULL; 56 } 57 58 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder) 59 { 60 struct drm_connector *connector; 61 struct drm_display_info *info; 62 63 connector = sun4i_tcon_get_connector(encoder); 64 if (!connector) 65 return -EINVAL; 66 67 info = &connector->display_info; 68 if (info->num_bus_formats != 1) 69 return -EINVAL; 70 71 switch (info->bus_formats[0]) { 72 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 73 return 18; 74 75 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 76 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 77 return 24; 78 } 79 80 return -EINVAL; 81 } 82 83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, 84 bool enabled) 85 { 86 struct clk *clk; 87 88 switch (channel) { 89 case 0: 90 WARN_ON(!tcon->quirks->has_channel_0); 91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 92 SUN4I_TCON0_CTL_TCON_ENABLE, 93 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0); 94 clk = tcon->dclk; 95 break; 96 case 1: 97 WARN_ON(!tcon->quirks->has_channel_1); 98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 99 SUN4I_TCON1_CTL_TCON_ENABLE, 100 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0); 101 clk = tcon->sclk1; 102 break; 103 default: 104 DRM_WARN("Unknown channel... doing nothing\n"); 105 return; 106 } 107 108 if (enabled) { 109 clk_prepare_enable(clk); 110 clk_rate_exclusive_get(clk); 111 } else { 112 clk_rate_exclusive_put(clk); 113 clk_disable_unprepare(clk); 114 } 115 } 116 117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 118 const struct drm_encoder *encoder) 119 { 120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 121 SUN4I_TCON0_LVDS_ANA0_CK_EN | 122 SUN4I_TCON0_LVDS_ANA0_REG_V | 123 SUN4I_TCON0_LVDS_ANA0_REG_C | 124 SUN4I_TCON0_LVDS_ANA0_EN_MB | 125 SUN4I_TCON0_LVDS_ANA0_PD | 126 SUN4I_TCON0_LVDS_ANA0_DCHS); 127 128 udelay(2); /* delay at least 1200 ns */ 129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 130 SUN4I_TCON0_LVDS_ANA1_INIT, 131 SUN4I_TCON0_LVDS_ANA1_INIT); 132 udelay(1); /* delay at least 120 ns */ 133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 134 SUN4I_TCON0_LVDS_ANA1_UPDATE, 135 SUN4I_TCON0_LVDS_ANA1_UPDATE); 136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 137 SUN4I_TCON0_LVDS_ANA0_EN_MB, 138 SUN4I_TCON0_LVDS_ANA0_EN_MB); 139 } 140 141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 142 const struct drm_encoder *encoder) 143 { 144 u8 val; 145 146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 147 SUN6I_TCON0_LVDS_ANA0_C(2) | 148 SUN6I_TCON0_LVDS_ANA0_V(3) | 149 SUN6I_TCON0_LVDS_ANA0_PD(2) | 150 SUN6I_TCON0_LVDS_ANA0_EN_LDO); 151 udelay(2); 152 153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 154 SUN6I_TCON0_LVDS_ANA0_EN_MB, 155 SUN6I_TCON0_LVDS_ANA0_EN_MB); 156 udelay(2); 157 158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 159 SUN6I_TCON0_LVDS_ANA0_EN_DRVC, 160 SUN6I_TCON0_LVDS_ANA0_EN_DRVC); 161 162 if (sun4i_tcon_get_pixel_depth(encoder) == 18) 163 val = 7; 164 else 165 val = 0xf; 166 167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 168 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), 169 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); 170 } 171 172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, 173 const struct drm_encoder *encoder, 174 bool enabled) 175 { 176 if (enabled) { 177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 178 SUN4I_TCON0_LVDS_IF_EN, 179 SUN4I_TCON0_LVDS_IF_EN); 180 if (tcon->quirks->setup_lvds_phy) 181 tcon->quirks->setup_lvds_phy(tcon, encoder); 182 } else { 183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 184 SUN4I_TCON0_LVDS_IF_EN, 0); 185 } 186 } 187 188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, 189 const struct drm_encoder *encoder, 190 bool enabled) 191 { 192 bool is_lvds = false; 193 int channel; 194 195 switch (encoder->encoder_type) { 196 case DRM_MODE_ENCODER_LVDS: 197 is_lvds = true; 198 fallthrough; 199 case DRM_MODE_ENCODER_DSI: 200 case DRM_MODE_ENCODER_NONE: 201 channel = 0; 202 break; 203 case DRM_MODE_ENCODER_TMDS: 204 case DRM_MODE_ENCODER_TVDAC: 205 channel = 1; 206 break; 207 default: 208 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 209 return; 210 } 211 212 if (is_lvds && !enabled) 213 sun4i_tcon_lvds_set_status(tcon, encoder, false); 214 215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 216 SUN4I_TCON_GCTL_TCON_ENABLE, 217 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0); 218 219 if (is_lvds && enabled) 220 sun4i_tcon_lvds_set_status(tcon, encoder, true); 221 222 sun4i_tcon_channel_set_status(tcon, channel, enabled); 223 } 224 225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) 226 { 227 u32 mask, val = 0; 228 229 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis"); 230 231 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) | 232 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) | 233 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE; 234 235 if (enable) 236 val = mask; 237 238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); 239 } 240 EXPORT_SYMBOL(sun4i_tcon_enable_vblank); 241 242 /* 243 * This function is a helper for TCON output muxing. The TCON output 244 * muxing control register in earlier SoCs (without the TCON TOP block) 245 * are located in TCON0. This helper returns a pointer to TCON0's 246 * sun4i_tcon structure, or NULL if not found. 247 */ 248 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm) 249 { 250 struct sun4i_drv *drv = drm->dev_private; 251 struct sun4i_tcon *tcon; 252 253 list_for_each_entry(tcon, &drv->tcon_list, list) 254 if (tcon->id == 0) 255 return tcon; 256 257 dev_warn(drm->dev, 258 "TCON0 not found, display output muxing may not work\n"); 259 260 return NULL; 261 } 262 263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, 264 const struct drm_encoder *encoder) 265 { 266 int ret = -ENOTSUPP; 267 268 if (tcon->quirks->set_mux) 269 ret = tcon->quirks->set_mux(tcon, encoder); 270 271 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n", 272 encoder->name, encoder->crtc->name, ret); 273 } 274 275 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, 276 int channel) 277 { 278 int delay = mode->vtotal - mode->vdisplay; 279 280 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 281 delay /= 2; 282 283 if (channel == 1) 284 delay -= 2; 285 286 delay = min(delay, 30); 287 288 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); 289 290 return delay; 291 } 292 293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, 294 const struct drm_display_mode *mode) 295 { 296 /* Configure the dot clock */ 297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); 298 299 /* Set the resolution */ 300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, 301 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | 302 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); 303 } 304 305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, 306 const struct drm_connector *connector) 307 { 308 u32 bus_format = 0; 309 u32 val = 0; 310 311 /* XXX Would this ever happen? */ 312 if (!connector) 313 return; 314 315 /* 316 * FIXME: Undocumented bits 317 * 318 * The whole dithering process and these parameters are not 319 * explained in the vendor documents or BSP kernel code. 320 */ 321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); 322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); 323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); 324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); 325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); 326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); 327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); 328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); 329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); 330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); 331 332 /* Do dithering if panel only supports 6 bits per color */ 333 if (connector->display_info.bpc == 6) 334 val |= SUN4I_TCON0_FRM_CTL_EN; 335 336 if (connector->display_info.num_bus_formats == 1) 337 bus_format = connector->display_info.bus_formats[0]; 338 339 /* Check the connection format */ 340 switch (bus_format) { 341 case MEDIA_BUS_FMT_RGB565_1X16: 342 /* R and B components are only 5 bits deep */ 343 val |= SUN4I_TCON0_FRM_CTL_MODE_R; 344 val |= SUN4I_TCON0_FRM_CTL_MODE_B; 345 fallthrough; 346 case MEDIA_BUS_FMT_RGB666_1X18: 347 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 348 /* Fall through: enable dithering */ 349 val |= SUN4I_TCON0_FRM_CTL_EN; 350 break; 351 } 352 353 /* Write dithering settings */ 354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); 355 } 356 357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, 358 const struct drm_encoder *encoder, 359 const struct drm_display_mode *mode) 360 { 361 /* TODO support normal CPU interface modes */ 362 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 363 struct mipi_dsi_device *device = dsi->device; 364 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); 365 u8 lanes = device->lanes; 366 u32 block_space, start_delay; 367 u32 tcon_div; 368 369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; 370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; 371 372 sun4i_tcon0_mode_set_common(tcon, mode); 373 374 /* Set dithering if needed */ 375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 376 377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 378 SUN4I_TCON0_CTL_IF_MASK, 379 SUN4I_TCON0_CTL_IF_8080); 380 381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, 382 SUN4I_TCON_ECC_FIFO_EN); 383 384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, 385 SUN4I_TCON0_CPU_IF_MODE_DSI | 386 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH | 387 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN | 388 SUN4I_TCON0_CPU_IF_TRI_EN); 389 390 /* 391 * This looks suspicious, but it works... 392 * 393 * The datasheet says that this should be set higher than 20 * 394 * pixel cycle, but it's not clear what a pixel cycle is. 395 */ 396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); 397 tcon_div &= GENMASK(6, 0); 398 block_space = mode->htotal * bpp / (tcon_div * lanes); 399 block_space -= mode->hdisplay + 40; 400 401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, 402 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) | 403 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); 404 405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, 406 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); 407 408 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); 409 start_delay = start_delay * mode->crtc_htotal * 149; 410 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; 411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, 412 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) | 413 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay)); 414 415 /* 416 * The Allwinner BSP has a comment that the period should be 417 * the display clock * 15, but uses an hardcoded 3000... 418 */ 419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, 420 SUN4I_TCON_SAFE_PERIOD_NUM(3000) | 421 SUN4I_TCON_SAFE_PERIOD_MODE(3)); 422 423 /* Enable the output on the pins */ 424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 425 0xe0000000); 426 } 427 428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, 429 const struct drm_encoder *encoder, 430 const struct drm_display_mode *mode) 431 { 432 unsigned int bp; 433 u8 clk_delay; 434 u32 reg, val = 0; 435 436 WARN_ON(!tcon->quirks->has_channel_0); 437 438 tcon->dclk_min_div = 7; 439 tcon->dclk_max_div = 7; 440 sun4i_tcon0_mode_set_common(tcon, mode); 441 442 /* Set dithering if needed */ 443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 444 445 /* Adjust clock delay */ 446 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 448 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 449 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 450 451 /* 452 * This is called a backporch in the register documentation, 453 * but it really is the back porch + hsync 454 */ 455 bp = mode->crtc_htotal - mode->crtc_hsync_start; 456 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 457 mode->crtc_htotal, bp); 458 459 /* Set horizontal display timings */ 460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 461 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | 462 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 463 464 /* 465 * This is called a backporch in the register documentation, 466 * but it really is the back porch + hsync 467 */ 468 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 469 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 470 mode->crtc_vtotal, bp); 471 472 /* Set vertical display timings */ 473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 474 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 475 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 476 477 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0; 478 if (sun4i_tcon_get_pixel_depth(encoder) == 24) 479 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS; 480 else 481 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS; 482 483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); 484 485 /* Setup the polarity of the various signals */ 486 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) 487 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 488 489 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) 490 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 491 492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); 493 494 /* Map output pins to channel 0 */ 495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 496 SUN4I_TCON_GCTL_IOMAP_MASK, 497 SUN4I_TCON_GCTL_IOMAP_TCON0); 498 499 /* Enable the output on the pins */ 500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); 501 } 502 503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 504 const struct drm_encoder *encoder, 505 const struct drm_display_mode *mode) 506 { 507 struct drm_connector *connector = sun4i_tcon_get_connector(encoder); 508 const struct drm_display_info *info = &connector->display_info; 509 unsigned int bp, hsync, vsync; 510 u8 clk_delay; 511 u32 val = 0; 512 513 WARN_ON(!tcon->quirks->has_channel_0); 514 515 tcon->dclk_min_div = tcon->quirks->dclk_min_div; 516 tcon->dclk_max_div = 127; 517 sun4i_tcon0_mode_set_common(tcon, mode); 518 519 /* Set dithering if needed */ 520 sun4i_tcon0_mode_set_dithering(tcon, connector); 521 522 /* Adjust clock delay */ 523 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 525 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 526 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 527 528 /* 529 * This is called a backporch in the register documentation, 530 * but it really is the back porch + hsync 531 */ 532 bp = mode->crtc_htotal - mode->crtc_hsync_start; 533 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 534 mode->crtc_htotal, bp); 535 536 /* Set horizontal display timings */ 537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 538 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | 539 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 540 541 /* 542 * This is called a backporch in the register documentation, 543 * but it really is the back porch + hsync 544 */ 545 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 546 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 547 mode->crtc_vtotal, bp); 548 549 /* Set vertical display timings */ 550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 551 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 552 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 553 554 /* Set Hsync and Vsync length */ 555 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 556 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 557 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, 559 SUN4I_TCON0_BASIC3_V_SYNC(vsync) | 560 SUN4I_TCON0_BASIC3_H_SYNC(hsync)); 561 562 /* Setup the polarity of the various signals */ 563 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 564 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 565 566 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 567 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 568 569 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 570 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; 571 572 /* 573 * On A20 and similar SoCs, the only way to achieve Positive Edge 574 * (Rising Edge), is setting dclk clock phase to 2/3(240°). 575 * By default TCON works in Negative Edge(Falling Edge), 576 * this is why phase is set to 0 in that case. 577 * Unfortunately there's no way to logically invert dclk through 578 * IO_POL register. 579 * The only acceptable way to work, triple checked with scope, 580 * is using clock phase set to 0° for Negative Edge and set to 240° 581 * for Positive Edge. 582 * On A33 and similar SoCs there would be a 90° phase option, 583 * but it divides also dclk by 2. 584 * Following code is a way to avoid quirks all around TCON 585 * and DOTCLOCK drivers. 586 */ 587 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 588 clk_set_phase(tcon->dclk, 240); 589 590 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 591 clk_set_phase(tcon->dclk, 0); 592 593 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, 594 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | 595 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE | 596 SUN4I_TCON0_IO_POL_DE_NEGATIVE, 597 val); 598 599 /* Map output pins to channel 0 */ 600 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 601 SUN4I_TCON_GCTL_IOMAP_MASK, 602 SUN4I_TCON_GCTL_IOMAP_TCON0); 603 604 /* Enable the output on the pins */ 605 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); 606 } 607 608 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 609 const struct drm_display_mode *mode) 610 { 611 unsigned int bp, hsync, vsync, vtotal; 612 u8 clk_delay; 613 u32 val; 614 615 WARN_ON(!tcon->quirks->has_channel_1); 616 617 /* Configure the dot clock */ 618 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); 619 620 /* Adjust clock delay */ 621 clk_delay = sun4i_tcon_get_clk_delay(mode, 1); 622 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 623 SUN4I_TCON1_CTL_CLK_DELAY_MASK, 624 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay)); 625 626 /* Set interlaced mode */ 627 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 628 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; 629 else 630 val = 0; 631 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 632 SUN4I_TCON1_CTL_INTERLACE_ENABLE, 633 val); 634 635 /* Set the input resolution */ 636 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, 637 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | 638 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); 639 640 /* Set the upscaling resolution */ 641 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, 642 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | 643 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); 644 645 /* Set the output resolution */ 646 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, 647 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | 648 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); 649 650 /* Set horizontal display timings */ 651 bp = mode->crtc_htotal - mode->crtc_hsync_start; 652 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 653 mode->htotal, bp); 654 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, 655 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | 656 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)); 657 658 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 659 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 660 mode->crtc_vtotal, bp); 661 662 /* 663 * The vertical resolution needs to be doubled in all 664 * cases. We could use crtc_vtotal and always multiply by two, 665 * but that leads to a rounding error in interlace when vtotal 666 * is odd. 667 * 668 * This happens with TV's PAL for example, where vtotal will 669 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be 670 * 624, which apparently confuses the hardware. 671 * 672 * To work around this, we will always use vtotal, and 673 * multiply by two only if we're not in interlace. 674 */ 675 vtotal = mode->vtotal; 676 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 677 vtotal = vtotal * 2; 678 679 /* Set vertical display timings */ 680 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, 681 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) | 682 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)); 683 684 /* Set Hsync and Vsync length */ 685 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 686 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 687 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 688 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, 689 SUN4I_TCON1_BASIC5_V_SYNC(vsync) | 690 SUN4I_TCON1_BASIC5_H_SYNC(hsync)); 691 692 /* Map output pins to channel 1 */ 693 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 694 SUN4I_TCON_GCTL_IOMAP_MASK, 695 SUN4I_TCON_GCTL_IOMAP_TCON1); 696 } 697 698 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, 699 const struct drm_encoder *encoder, 700 const struct drm_display_mode *mode) 701 { 702 switch (encoder->encoder_type) { 703 case DRM_MODE_ENCODER_DSI: 704 /* DSI is tied to special case of CPU interface */ 705 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); 706 break; 707 case DRM_MODE_ENCODER_LVDS: 708 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); 709 break; 710 case DRM_MODE_ENCODER_NONE: 711 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); 712 sun4i_tcon_set_mux(tcon, 0, encoder); 713 break; 714 case DRM_MODE_ENCODER_TVDAC: 715 case DRM_MODE_ENCODER_TMDS: 716 sun4i_tcon1_mode_set(tcon, mode); 717 sun4i_tcon_set_mux(tcon, 1, encoder); 718 break; 719 default: 720 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 721 } 722 } 723 EXPORT_SYMBOL(sun4i_tcon_mode_set); 724 725 static void sun4i_tcon_finish_page_flip(struct drm_device *dev, 726 struct sun4i_crtc *scrtc) 727 { 728 unsigned long flags; 729 730 spin_lock_irqsave(&dev->event_lock, flags); 731 if (scrtc->event) { 732 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); 733 drm_crtc_vblank_put(&scrtc->crtc); 734 scrtc->event = NULL; 735 } 736 spin_unlock_irqrestore(&dev->event_lock, flags); 737 } 738 739 static irqreturn_t sun4i_tcon_handler(int irq, void *private) 740 { 741 struct sun4i_tcon *tcon = private; 742 struct drm_device *drm = tcon->drm; 743 struct sun4i_crtc *scrtc = tcon->crtc; 744 struct sunxi_engine *engine = scrtc->engine; 745 unsigned int status; 746 747 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); 748 749 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) | 750 SUN4I_TCON_GINT0_VBLANK_INT(1) | 751 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT))) 752 return IRQ_NONE; 753 754 drm_crtc_handle_vblank(&scrtc->crtc); 755 sun4i_tcon_finish_page_flip(drm, scrtc); 756 757 /* Acknowledge the interrupt */ 758 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, 759 SUN4I_TCON_GINT0_VBLANK_INT(0) | 760 SUN4I_TCON_GINT0_VBLANK_INT(1) | 761 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT, 762 0); 763 764 if (engine->ops->vblank_quirk) 765 engine->ops->vblank_quirk(engine); 766 767 return IRQ_HANDLED; 768 } 769 770 static int sun4i_tcon_init_clocks(struct device *dev, 771 struct sun4i_tcon *tcon) 772 { 773 tcon->clk = devm_clk_get(dev, "ahb"); 774 if (IS_ERR(tcon->clk)) { 775 dev_err(dev, "Couldn't get the TCON bus clock\n"); 776 return PTR_ERR(tcon->clk); 777 } 778 clk_prepare_enable(tcon->clk); 779 780 if (tcon->quirks->has_channel_0) { 781 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); 782 if (IS_ERR(tcon->sclk0)) { 783 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); 784 return PTR_ERR(tcon->sclk0); 785 } 786 } 787 clk_prepare_enable(tcon->sclk0); 788 789 if (tcon->quirks->has_channel_1) { 790 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); 791 if (IS_ERR(tcon->sclk1)) { 792 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); 793 return PTR_ERR(tcon->sclk1); 794 } 795 } 796 797 return 0; 798 } 799 800 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) 801 { 802 clk_disable_unprepare(tcon->sclk0); 803 clk_disable_unprepare(tcon->clk); 804 } 805 806 static int sun4i_tcon_init_irq(struct device *dev, 807 struct sun4i_tcon *tcon) 808 { 809 struct platform_device *pdev = to_platform_device(dev); 810 int irq, ret; 811 812 irq = platform_get_irq(pdev, 0); 813 if (irq < 0) 814 return irq; 815 816 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0, 817 dev_name(dev), tcon); 818 if (ret) { 819 dev_err(dev, "Couldn't request the IRQ\n"); 820 return ret; 821 } 822 823 return 0; 824 } 825 826 static const struct regmap_config sun4i_tcon_regmap_config = { 827 .reg_bits = 32, 828 .val_bits = 32, 829 .reg_stride = 4, 830 .max_register = 0x800, 831 }; 832 833 static int sun4i_tcon_init_regmap(struct device *dev, 834 struct sun4i_tcon *tcon) 835 { 836 struct platform_device *pdev = to_platform_device(dev); 837 struct resource *res; 838 void __iomem *regs; 839 840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 841 regs = devm_ioremap_resource(dev, res); 842 if (IS_ERR(regs)) 843 return PTR_ERR(regs); 844 845 tcon->regs = devm_regmap_init_mmio(dev, regs, 846 &sun4i_tcon_regmap_config); 847 if (IS_ERR(tcon->regs)) { 848 dev_err(dev, "Couldn't create the TCON regmap\n"); 849 return PTR_ERR(tcon->regs); 850 } 851 852 /* Make sure the TCON is disabled and all IRQs are off */ 853 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); 854 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); 855 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); 856 857 /* Disable IO lines and set them to tristate */ 858 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); 859 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); 860 861 return 0; 862 } 863 864 /* 865 * On SoCs with the old display pipeline design (Display Engine 1.0), 866 * the TCON is always tied to just one backend. Hence we can traverse 867 * the of_graph upwards to find the backend our tcon is connected to, 868 * and take its ID as our own. 869 * 870 * We can either identify backends from their compatible strings, which 871 * means maintaining a large list of them. Or, since the backend is 872 * registered and binded before the TCON, we can just go through the 873 * list of registered backends and compare the device node. 874 * 875 * As the structures now store engines instead of backends, here this 876 * function in fact searches the corresponding engine, and the ID is 877 * requested via the get_id function of the engine. 878 */ 879 static struct sunxi_engine * 880 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv, 881 struct device_node *node, 882 u32 port_id) 883 { 884 struct device_node *port, *ep, *remote; 885 struct sunxi_engine *engine = ERR_PTR(-EINVAL); 886 u32 reg = 0; 887 888 port = of_graph_get_port_by_id(node, port_id); 889 if (!port) 890 return ERR_PTR(-EINVAL); 891 892 /* 893 * This only works if there is only one path from the TCON 894 * to any display engine. Otherwise the probe order of the 895 * TCONs and display engines is not guaranteed. They may 896 * either bind to the wrong one, or worse, bind to the same 897 * one if additional checks are not done. 898 * 899 * Bail out if there are multiple input connections. 900 */ 901 if (of_get_available_child_count(port) != 1) 902 goto out_put_port; 903 904 /* Get the first connection without specifying an ID */ 905 ep = of_get_next_available_child(port, NULL); 906 if (!ep) 907 goto out_put_port; 908 909 remote = of_graph_get_remote_port_parent(ep); 910 if (!remote) 911 goto out_put_ep; 912 913 /* does this node match any registered engines? */ 914 list_for_each_entry(engine, &drv->engine_list, list) 915 if (remote == engine->node) 916 goto out_put_remote; 917 918 /* 919 * According to device tree binding input ports have even id 920 * number and output ports have odd id. Since component with 921 * more than one input and one output (TCON TOP) exits, correct 922 * remote input id has to be calculated by subtracting 1 from 923 * remote output id. If this for some reason can't be done, 0 924 * is used as input port id. 925 */ 926 of_node_put(port); 927 port = of_graph_get_remote_port(ep); 928 if (!of_property_read_u32(port, "reg", ®) && reg > 0) 929 reg -= 1; 930 931 /* keep looking through upstream ports */ 932 engine = sun4i_tcon_find_engine_traverse(drv, remote, reg); 933 934 out_put_remote: 935 of_node_put(remote); 936 out_put_ep: 937 of_node_put(ep); 938 out_put_port: 939 of_node_put(port); 940 941 return engine; 942 } 943 944 /* 945 * The device tree binding says that the remote endpoint ID of any 946 * connection between components, up to and including the TCON, of 947 * the display pipeline should be equal to the actual ID of the local 948 * component. Thus we can look at any one of the input connections of 949 * the TCONs, and use that connection's remote endpoint ID as our own. 950 * 951 * Since the user of this function already finds the input port, 952 * the port is passed in directly without further checks. 953 */ 954 static int sun4i_tcon_of_get_id_from_port(struct device_node *port) 955 { 956 struct device_node *ep; 957 int ret = -EINVAL; 958 959 /* try finding an upstream endpoint */ 960 for_each_available_child_of_node(port, ep) { 961 struct device_node *remote; 962 u32 reg; 963 964 remote = of_graph_get_remote_endpoint(ep); 965 if (!remote) 966 continue; 967 968 ret = of_property_read_u32(remote, "reg", ®); 969 if (ret) 970 continue; 971 972 ret = reg; 973 } 974 975 return ret; 976 } 977 978 /* 979 * Once we know the TCON's id, we can look through the list of 980 * engines to find a matching one. We assume all engines have 981 * been probed and added to the list. 982 */ 983 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv, 984 int id) 985 { 986 struct sunxi_engine *engine; 987 988 list_for_each_entry(engine, &drv->engine_list, list) 989 if (engine->id == id) 990 return engine; 991 992 return ERR_PTR(-EINVAL); 993 } 994 995 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node) 996 { 997 struct device_node *remote; 998 bool ret = false; 999 1000 remote = of_graph_get_remote_node(node, 0, -1); 1001 if (remote) { 1002 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1003 of_match_node(sun8i_tcon_top_of_table, remote)); 1004 of_node_put(remote); 1005 } 1006 1007 return ret; 1008 } 1009 1010 static int sun4i_tcon_get_index(struct sun4i_drv *drv) 1011 { 1012 struct list_head *pos; 1013 int size = 0; 1014 1015 /* 1016 * Because TCON is added to the list at the end of the probe 1017 * (after this function is called), index of the current TCON 1018 * will be same as current TCON list size. 1019 */ 1020 list_for_each(pos, &drv->tcon_list) 1021 ++size; 1022 1023 return size; 1024 } 1025 1026 /* 1027 * On SoCs with the old display pipeline design (Display Engine 1.0), 1028 * we assumed the TCON was always tied to just one backend. However 1029 * this proved not to be the case. On the A31, the TCON can select 1030 * either backend as its source. On the A20 (and likely on the A10), 1031 * the backend can choose which TCON to output to. 1032 * 1033 * The device tree binding says that the remote endpoint ID of any 1034 * connection between components, up to and including the TCON, of 1035 * the display pipeline should be equal to the actual ID of the local 1036 * component. Thus we should be able to look at any one of the input 1037 * connections of the TCONs, and use that connection's remote endpoint 1038 * ID as our own. 1039 * 1040 * However the connections between the backend and TCON were assumed 1041 * to be always singular, and their endpoit IDs were all incorrectly 1042 * set to 0. This means for these old device trees, we cannot just look 1043 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be 1044 * incorrectly identified as TCON0. 1045 * 1046 * This function first checks if the TCON node has 2 input endpoints. 1047 * If so, then the device tree is a corrected version, and it will use 1048 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above 1049 * to fetch the ID and engine directly. If not, then it is likely an 1050 * old device trees, where the endpoint IDs were incorrect, but did not 1051 * have endpoint connections between the backend and TCON across 1052 * different display pipelines. It will fall back to the old method of 1053 * traversing the of_graph to try and find a matching engine by device 1054 * node. 1055 * 1056 * In the case of single display pipeline device trees, either method 1057 * works. 1058 */ 1059 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv, 1060 struct device_node *node) 1061 { 1062 struct device_node *port; 1063 struct sunxi_engine *engine; 1064 1065 port = of_graph_get_port_by_id(node, 0); 1066 if (!port) 1067 return ERR_PTR(-EINVAL); 1068 1069 /* 1070 * Is this a corrected device tree with cross pipeline 1071 * connections between the backend and TCON? 1072 */ 1073 if (of_get_child_count(port) > 1) { 1074 int id; 1075 1076 /* 1077 * When pipeline has the same number of TCONs and engines which 1078 * are represented by frontends/backends (DE1) or mixers (DE2), 1079 * we match them by their respective IDs. However, if pipeline 1080 * contains TCON TOP, chances are that there are either more 1081 * TCONs than engines (R40) or TCONs with non-consecutive ids. 1082 * (H6). In that case it's easier just use TCON index in list 1083 * as an id. That means that on R40, any 2 TCONs can be enabled 1084 * in DT out of 4 (there are 2 mixers). Due to the design of 1085 * TCON TOP, remaining 2 TCONs can't be connected to anything 1086 * anyway. 1087 */ 1088 if (sun4i_tcon_connected_to_tcon_top(node)) 1089 id = sun4i_tcon_get_index(drv); 1090 else 1091 id = sun4i_tcon_of_get_id_from_port(port); 1092 1093 /* Get our engine by matching our ID */ 1094 engine = sun4i_tcon_get_engine_by_id(drv, id); 1095 1096 of_node_put(port); 1097 return engine; 1098 } 1099 1100 /* Fallback to old method by traversing input endpoints */ 1101 of_node_put(port); 1102 return sun4i_tcon_find_engine_traverse(drv, node, 0); 1103 } 1104 1105 static int sun4i_tcon_bind(struct device *dev, struct device *master, 1106 void *data) 1107 { 1108 struct drm_device *drm = data; 1109 struct sun4i_drv *drv = drm->dev_private; 1110 struct sunxi_engine *engine; 1111 struct device_node *remote; 1112 struct sun4i_tcon *tcon; 1113 struct reset_control *edp_rstc; 1114 bool has_lvds_rst, has_lvds_alt, can_lvds; 1115 int ret; 1116 1117 engine = sun4i_tcon_find_engine(drv, dev->of_node); 1118 if (IS_ERR(engine)) { 1119 dev_err(dev, "Couldn't find matching engine\n"); 1120 return -EPROBE_DEFER; 1121 } 1122 1123 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); 1124 if (!tcon) 1125 return -ENOMEM; 1126 dev_set_drvdata(dev, tcon); 1127 tcon->drm = drm; 1128 tcon->dev = dev; 1129 tcon->id = engine->id; 1130 tcon->quirks = of_device_get_match_data(dev); 1131 1132 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); 1133 if (IS_ERR(tcon->lcd_rst)) { 1134 dev_err(dev, "Couldn't get our reset line\n"); 1135 return PTR_ERR(tcon->lcd_rst); 1136 } 1137 1138 if (tcon->quirks->needs_edp_reset) { 1139 edp_rstc = devm_reset_control_get_shared(dev, "edp"); 1140 if (IS_ERR(edp_rstc)) { 1141 dev_err(dev, "Couldn't get edp reset line\n"); 1142 return PTR_ERR(edp_rstc); 1143 } 1144 1145 ret = reset_control_deassert(edp_rstc); 1146 if (ret) { 1147 dev_err(dev, "Couldn't deassert edp reset line\n"); 1148 return ret; 1149 } 1150 } 1151 1152 /* Make sure our TCON is reset */ 1153 ret = reset_control_reset(tcon->lcd_rst); 1154 if (ret) { 1155 dev_err(dev, "Couldn't deassert our reset line\n"); 1156 return ret; 1157 } 1158 1159 if (tcon->quirks->supports_lvds) { 1160 /* 1161 * This can only be made optional since we've had DT 1162 * nodes without the LVDS reset properties. 1163 * 1164 * If the property is missing, just disable LVDS, and 1165 * print a warning. 1166 */ 1167 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); 1168 if (IS_ERR(tcon->lvds_rst)) { 1169 dev_err(dev, "Couldn't get our reset line\n"); 1170 return PTR_ERR(tcon->lvds_rst); 1171 } else if (tcon->lvds_rst) { 1172 has_lvds_rst = true; 1173 reset_control_reset(tcon->lvds_rst); 1174 } else { 1175 has_lvds_rst = false; 1176 } 1177 1178 /* 1179 * This can only be made optional since we've had DT 1180 * nodes without the LVDS reset properties. 1181 * 1182 * If the property is missing, just disable LVDS, and 1183 * print a warning. 1184 */ 1185 if (tcon->quirks->has_lvds_alt) { 1186 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); 1187 if (IS_ERR(tcon->lvds_pll)) { 1188 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { 1189 has_lvds_alt = false; 1190 } else { 1191 dev_err(dev, "Couldn't get the LVDS PLL\n"); 1192 return PTR_ERR(tcon->lvds_pll); 1193 } 1194 } else { 1195 has_lvds_alt = true; 1196 } 1197 } 1198 1199 if (!has_lvds_rst || 1200 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { 1201 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); 1202 dev_warn(dev, "LVDS output disabled\n"); 1203 can_lvds = false; 1204 } else { 1205 can_lvds = true; 1206 } 1207 } else { 1208 can_lvds = false; 1209 } 1210 1211 ret = sun4i_tcon_init_clocks(dev, tcon); 1212 if (ret) { 1213 dev_err(dev, "Couldn't init our TCON clocks\n"); 1214 goto err_assert_reset; 1215 } 1216 1217 ret = sun4i_tcon_init_regmap(dev, tcon); 1218 if (ret) { 1219 dev_err(dev, "Couldn't init our TCON regmap\n"); 1220 goto err_free_clocks; 1221 } 1222 1223 if (tcon->quirks->has_channel_0) { 1224 ret = sun4i_dclk_create(dev, tcon); 1225 if (ret) { 1226 dev_err(dev, "Couldn't create our TCON dot clock\n"); 1227 goto err_free_clocks; 1228 } 1229 } 1230 1231 ret = sun4i_tcon_init_irq(dev, tcon); 1232 if (ret) { 1233 dev_err(dev, "Couldn't init our TCON interrupts\n"); 1234 goto err_free_dotclock; 1235 } 1236 1237 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); 1238 if (IS_ERR(tcon->crtc)) { 1239 dev_err(dev, "Couldn't create our CRTC\n"); 1240 ret = PTR_ERR(tcon->crtc); 1241 goto err_free_dotclock; 1242 } 1243 1244 if (tcon->quirks->has_channel_0) { 1245 /* 1246 * If we have an LVDS panel connected to the TCON, we should 1247 * just probe the LVDS connector. Otherwise, just probe RGB as 1248 * we used to. 1249 */ 1250 remote = of_graph_get_remote_node(dev->of_node, 1, 0); 1251 if (of_device_is_compatible(remote, "panel-lvds")) 1252 if (can_lvds) 1253 ret = sun4i_lvds_init(drm, tcon); 1254 else 1255 ret = -EINVAL; 1256 else 1257 ret = sun4i_rgb_init(drm, tcon); 1258 of_node_put(remote); 1259 1260 if (ret < 0) 1261 goto err_free_dotclock; 1262 } 1263 1264 if (tcon->quirks->needs_de_be_mux) { 1265 /* 1266 * We assume there is no dynamic muxing of backends 1267 * and TCONs, so we select the backend with same ID. 1268 * 1269 * While dynamic selection might be interesting, since 1270 * the CRTC is tied to the TCON, while the layers are 1271 * tied to the backends, this means, we will need to 1272 * switch between groups of layers. There might not be 1273 * a way to represent this constraint in DRM. 1274 */ 1275 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 1276 SUN4I_TCON0_CTL_SRC_SEL_MASK, 1277 tcon->id); 1278 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 1279 SUN4I_TCON1_CTL_SRC_SEL_MASK, 1280 tcon->id); 1281 } 1282 1283 list_add_tail(&tcon->list, &drv->tcon_list); 1284 1285 return 0; 1286 1287 err_free_dotclock: 1288 if (tcon->quirks->has_channel_0) 1289 sun4i_dclk_free(tcon); 1290 err_free_clocks: 1291 sun4i_tcon_free_clocks(tcon); 1292 err_assert_reset: 1293 reset_control_assert(tcon->lcd_rst); 1294 return ret; 1295 } 1296 1297 static void sun4i_tcon_unbind(struct device *dev, struct device *master, 1298 void *data) 1299 { 1300 struct sun4i_tcon *tcon = dev_get_drvdata(dev); 1301 1302 list_del(&tcon->list); 1303 if (tcon->quirks->has_channel_0) 1304 sun4i_dclk_free(tcon); 1305 sun4i_tcon_free_clocks(tcon); 1306 } 1307 1308 static const struct component_ops sun4i_tcon_ops = { 1309 .bind = sun4i_tcon_bind, 1310 .unbind = sun4i_tcon_unbind, 1311 }; 1312 1313 static int sun4i_tcon_probe(struct platform_device *pdev) 1314 { 1315 struct device_node *node = pdev->dev.of_node; 1316 const struct sun4i_tcon_quirks *quirks; 1317 struct drm_bridge *bridge; 1318 struct drm_panel *panel; 1319 int ret; 1320 1321 quirks = of_device_get_match_data(&pdev->dev); 1322 1323 /* panels and bridges are present only on TCONs with channel 0 */ 1324 if (quirks->has_channel_0) { 1325 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); 1326 if (ret == -EPROBE_DEFER) 1327 return ret; 1328 } 1329 1330 return component_add(&pdev->dev, &sun4i_tcon_ops); 1331 } 1332 1333 static int sun4i_tcon_remove(struct platform_device *pdev) 1334 { 1335 component_del(&pdev->dev, &sun4i_tcon_ops); 1336 1337 return 0; 1338 } 1339 1340 /* platform specific TCON muxing callbacks */ 1341 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, 1342 const struct drm_encoder *encoder) 1343 { 1344 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1345 u32 shift; 1346 1347 if (!tcon0) 1348 return -EINVAL; 1349 1350 switch (encoder->encoder_type) { 1351 case DRM_MODE_ENCODER_TMDS: 1352 /* HDMI */ 1353 shift = 8; 1354 break; 1355 default: 1356 return -EINVAL; 1357 } 1358 1359 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1360 0x3 << shift, tcon->id << shift); 1361 1362 return 0; 1363 } 1364 1365 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, 1366 const struct drm_encoder *encoder) 1367 { 1368 u32 val; 1369 1370 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1371 val = 1; 1372 else 1373 val = 0; 1374 1375 /* 1376 * FIXME: Undocumented bits 1377 */ 1378 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); 1379 } 1380 1381 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, 1382 const struct drm_encoder *encoder) 1383 { 1384 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1385 u32 shift; 1386 1387 if (!tcon0) 1388 return -EINVAL; 1389 1390 switch (encoder->encoder_type) { 1391 case DRM_MODE_ENCODER_TMDS: 1392 /* HDMI */ 1393 shift = 8; 1394 break; 1395 default: 1396 /* TODO A31 has MIPI DSI but A31s does not */ 1397 return -EINVAL; 1398 } 1399 1400 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1401 0x3 << shift, tcon->id << shift); 1402 1403 return 0; 1404 } 1405 1406 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, 1407 const struct drm_encoder *encoder) 1408 { 1409 struct device_node *port, *remote; 1410 struct platform_device *pdev; 1411 int id, ret; 1412 1413 /* find TCON TOP platform device and TCON id */ 1414 1415 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); 1416 if (!port) 1417 return -EINVAL; 1418 1419 id = sun4i_tcon_of_get_id_from_port(port); 1420 of_node_put(port); 1421 1422 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); 1423 if (!remote) 1424 return -EINVAL; 1425 1426 pdev = of_find_device_by_node(remote); 1427 of_node_put(remote); 1428 if (!pdev) 1429 return -EINVAL; 1430 1431 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1432 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { 1433 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); 1434 if (ret) { 1435 put_device(&pdev->dev); 1436 return ret; 1437 } 1438 } 1439 1440 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) { 1441 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); 1442 if (ret) { 1443 put_device(&pdev->dev); 1444 return ret; 1445 } 1446 } 1447 1448 return 0; 1449 } 1450 1451 static const struct sun4i_tcon_quirks sun4i_a10_quirks = { 1452 .has_channel_0 = true, 1453 .has_channel_1 = true, 1454 .dclk_min_div = 4, 1455 .set_mux = sun4i_a10_tcon_set_mux, 1456 }; 1457 1458 static const struct sun4i_tcon_quirks sun5i_a13_quirks = { 1459 .has_channel_0 = true, 1460 .has_channel_1 = true, 1461 .dclk_min_div = 4, 1462 .set_mux = sun5i_a13_tcon_set_mux, 1463 }; 1464 1465 static const struct sun4i_tcon_quirks sun6i_a31_quirks = { 1466 .has_channel_0 = true, 1467 .has_channel_1 = true, 1468 .has_lvds_alt = true, 1469 .needs_de_be_mux = true, 1470 .dclk_min_div = 1, 1471 .set_mux = sun6i_tcon_set_mux, 1472 }; 1473 1474 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = { 1475 .has_channel_0 = true, 1476 .has_channel_1 = true, 1477 .needs_de_be_mux = true, 1478 .dclk_min_div = 1, 1479 }; 1480 1481 static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = { 1482 .supports_lvds = true, 1483 .has_channel_0 = true, 1484 .has_channel_1 = true, 1485 .dclk_min_div = 4, 1486 /* Same display pipeline structure as A10 */ 1487 .set_mux = sun4i_a10_tcon_set_mux, 1488 .setup_lvds_phy = sun4i_tcon_setup_lvds_phy, 1489 }; 1490 1491 static const struct sun4i_tcon_quirks sun7i_a20_quirks = { 1492 .has_channel_0 = true, 1493 .has_channel_1 = true, 1494 .dclk_min_div = 4, 1495 /* Same display pipeline structure as A10 */ 1496 .set_mux = sun4i_a10_tcon_set_mux, 1497 }; 1498 1499 static const struct sun4i_tcon_quirks sun8i_a33_quirks = { 1500 .has_channel_0 = true, 1501 .has_lvds_alt = true, 1502 .dclk_min_div = 1, 1503 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1504 .supports_lvds = true, 1505 }; 1506 1507 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { 1508 .supports_lvds = true, 1509 .has_channel_0 = true, 1510 .dclk_min_div = 1, 1511 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1512 }; 1513 1514 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 1515 .has_channel_1 = true, 1516 }; 1517 1518 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { 1519 .has_channel_1 = true, 1520 .set_mux = sun8i_r40_tcon_tv_set_mux, 1521 }; 1522 1523 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = { 1524 .has_channel_0 = true, 1525 .dclk_min_div = 1, 1526 }; 1527 1528 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = { 1529 .has_channel_0 = true, 1530 .needs_edp_reset = true, 1531 .dclk_min_div = 1, 1532 }; 1533 1534 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = { 1535 .has_channel_1 = true, 1536 .needs_edp_reset = true, 1537 }; 1538 1539 /* sun4i_drv uses this list to check if a device node is a TCON */ 1540 const struct of_device_id sun4i_tcon_of_table[] = { 1541 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks }, 1542 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks }, 1543 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks }, 1544 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks }, 1545 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks }, 1546 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks }, 1547 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks }, 1548 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks }, 1549 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, 1550 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, 1551 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, 1552 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks }, 1553 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks }, 1554 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks }, 1555 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks }, 1556 { } 1557 }; 1558 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table); 1559 EXPORT_SYMBOL(sun4i_tcon_of_table); 1560 1561 static struct platform_driver sun4i_tcon_platform_driver = { 1562 .probe = sun4i_tcon_probe, 1563 .remove = sun4i_tcon_remove, 1564 .driver = { 1565 .name = "sun4i-tcon", 1566 .of_match_table = sun4i_tcon_of_table, 1567 }, 1568 }; 1569 module_platform_driver(sun4i_tcon_platform_driver); 1570 1571 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1572 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver"); 1573 MODULE_LICENSE("GPL"); 1574