1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_edid.h> 21 #include <drm/drm_encoder.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "sun4i_backend.h" 29 #include "sun4i_crtc.h" 30 #include "sun4i_drv.h" 31 #include "sun4i_hdmi.h" 32 33 static inline struct sun4i_hdmi * 34 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 35 { 36 return container_of(encoder, struct sun4i_hdmi, 37 encoder); 38 } 39 40 static inline struct sun4i_hdmi * 41 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 42 { 43 return container_of(connector, struct sun4i_hdmi, 44 connector); 45 } 46 47 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 48 struct drm_display_mode *mode) 49 { 50 struct hdmi_avi_infoframe frame; 51 u8 buffer[17]; 52 int i, ret; 53 54 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 55 &hdmi->connector, mode); 56 if (ret < 0) { 57 DRM_ERROR("Failed to get infoframes from mode\n"); 58 return ret; 59 } 60 61 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 62 if (ret < 0) { 63 DRM_ERROR("Failed to pack infoframes\n"); 64 return ret; 65 } 66 67 for (i = 0; i < sizeof(buffer); i++) 68 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 69 70 return 0; 71 } 72 73 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 74 struct drm_crtc_state *crtc_state, 75 struct drm_connector_state *conn_state) 76 { 77 struct drm_display_mode *mode = &crtc_state->mode; 78 79 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 80 return -EINVAL; 81 82 return 0; 83 } 84 85 static void sun4i_hdmi_disable(struct drm_encoder *encoder) 86 { 87 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 88 u32 val; 89 90 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 91 92 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 93 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 94 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 95 96 clk_disable_unprepare(hdmi->tmds_clk); 97 } 98 99 static void sun4i_hdmi_enable(struct drm_encoder *encoder) 100 { 101 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 102 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 103 struct drm_display_info *display = &hdmi->connector.display_info; 104 u32 val = 0; 105 106 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 107 108 clk_prepare_enable(hdmi->tmds_clk); 109 110 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 112 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 113 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 114 115 val = SUN4I_HDMI_VID_CTRL_ENABLE; 116 if (display->is_hdmi) 117 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 118 119 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 120 } 121 122 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, 123 struct drm_display_mode *mode, 124 struct drm_display_mode *adjusted_mode) 125 { 126 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 127 unsigned int x, y; 128 u32 val; 129 130 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 131 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 132 133 /* Set input sync enable */ 134 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 135 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 136 137 /* 138 * Setup output pad (?) controls 139 * 140 * This is done here instead of at probe/bind time because 141 * the controller seems to toggle some of the bits on its own. 142 * 143 * We can't just initialize the register there, we need to 144 * protect the clock bits that have already been read out and 145 * cached by the clock framework. 146 */ 147 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 148 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 149 val |= hdmi->variant->pad_ctrl1_init_val; 150 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 151 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 152 153 /* Setup timing registers */ 154 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 155 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 156 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 157 158 x = mode->htotal - mode->hsync_start; 159 y = mode->vtotal - mode->vsync_start; 160 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 161 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 162 163 x = mode->hsync_start - mode->hdisplay; 164 y = mode->vsync_start - mode->vdisplay; 165 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 166 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 167 168 x = mode->hsync_end - mode->hsync_start; 169 y = mode->vsync_end - mode->vsync_start; 170 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 171 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 172 173 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 174 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 175 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 176 177 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 178 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 179 180 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 181 } 182 183 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 184 const struct drm_display_mode *mode) 185 { 186 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 187 unsigned long rate = mode->clock * 1000; 188 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 189 long rounded_rate; 190 191 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 192 if (rate > 165000000) 193 return MODE_CLOCK_HIGH; 194 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 195 if (rounded_rate > 0 && 196 max_t(unsigned long, rounded_rate, rate) - 197 min_t(unsigned long, rounded_rate, rate) < diff) 198 return MODE_OK; 199 return MODE_NOCLOCK; 200 } 201 202 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 203 .atomic_check = sun4i_hdmi_atomic_check, 204 .disable = sun4i_hdmi_disable, 205 .enable = sun4i_hdmi_enable, 206 .mode_set = sun4i_hdmi_mode_set, 207 .mode_valid = sun4i_hdmi_mode_valid, 208 }; 209 210 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 211 { 212 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 213 struct edid *edid; 214 int ret; 215 216 edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c); 217 if (!edid) 218 return 0; 219 220 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 221 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 222 223 drm_connector_update_edid_property(connector, edid); 224 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 225 ret = drm_add_edid_modes(connector, edid); 226 kfree(edid); 227 228 return ret; 229 } 230 231 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 232 { 233 struct device_node *phandle, *remote; 234 struct i2c_adapter *ddc; 235 236 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 237 if (!remote) 238 return ERR_PTR(-EINVAL); 239 240 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 241 of_node_put(remote); 242 if (!phandle) 243 return ERR_PTR(-ENODEV); 244 245 ddc = of_get_i2c_adapter_by_node(phandle); 246 of_node_put(phandle); 247 if (!ddc) 248 return ERR_PTR(-EPROBE_DEFER); 249 250 return ddc; 251 } 252 253 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 254 .get_modes = sun4i_hdmi_get_modes, 255 }; 256 257 static enum drm_connector_status 258 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 259 { 260 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 261 unsigned long reg; 262 263 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 264 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 265 cec_phys_addr_invalidate(hdmi->cec_adap); 266 return connector_status_disconnected; 267 } 268 269 return connector_status_connected; 270 } 271 272 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 273 .detect = sun4i_hdmi_connector_detect, 274 .fill_modes = drm_helper_probe_single_connector_modes, 275 .destroy = drm_connector_cleanup, 276 .reset = drm_atomic_helper_connector_reset, 277 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 278 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 279 }; 280 281 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 282 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 283 { 284 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 285 286 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 287 } 288 289 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 290 { 291 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 292 293 /* Start driving the CEC pin low */ 294 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 295 } 296 297 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 298 { 299 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 300 301 /* 302 * Stop driving the CEC pin, the pull up will take over 303 * unless another CEC device is driving the pin low. 304 */ 305 writel(0, hdmi->base + SUN4I_HDMI_CEC); 306 } 307 308 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 309 .read = sun4i_hdmi_cec_pin_read, 310 .low = sun4i_hdmi_cec_pin_low, 311 .high = sun4i_hdmi_cec_pin_high, 312 }; 313 #endif 314 315 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 316 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 317 318 /* Only difference from sun5i is AMP is 4 instead of 6 */ 319 static const struct sun4i_hdmi_variant sun4i_variant = { 320 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 321 SUN4I_HDMI_PAD_CTRL0_CKEN | 322 SUN4I_HDMI_PAD_CTRL0_PWENG | 323 SUN4I_HDMI_PAD_CTRL0_PWEND | 324 SUN4I_HDMI_PAD_CTRL0_PWENC | 325 SUN4I_HDMI_PAD_CTRL0_LDODEN | 326 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 327 SUN4I_HDMI_PAD_CTRL0_BIASEN, 328 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 329 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 330 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 331 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 332 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 333 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 334 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 335 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 336 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 337 SUN4I_HDMI_PLL_CTRL_CS(7) | 338 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 339 SUN4I_HDMI_PLL_CTRL_S(7) | 340 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 341 SUN4I_HDMI_PLL_CTRL_SDIV2 | 342 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 343 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 344 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 345 SUN4I_HDMI_PLL_CTRL_BWS | 346 SUN4I_HDMI_PLL_CTRL_PLL_EN, 347 348 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 349 .ddc_clk_pre_divider = 2, 350 .ddc_clk_m_offset = 1, 351 352 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 353 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 354 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 355 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 356 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 357 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 358 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 359 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 360 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 361 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 362 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 363 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 364 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 365 366 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 367 .ddc_fifo_has_dir = true, 368 }; 369 370 static const struct sun4i_hdmi_variant sun5i_variant = { 371 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 372 SUN4I_HDMI_PAD_CTRL0_CKEN | 373 SUN4I_HDMI_PAD_CTRL0_PWENG | 374 SUN4I_HDMI_PAD_CTRL0_PWEND | 375 SUN4I_HDMI_PAD_CTRL0_PWENC | 376 SUN4I_HDMI_PAD_CTRL0_LDODEN | 377 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 378 SUN4I_HDMI_PAD_CTRL0_BIASEN, 379 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 380 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 381 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 382 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 383 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 384 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 385 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 386 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 387 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 388 SUN4I_HDMI_PLL_CTRL_CS(7) | 389 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 390 SUN4I_HDMI_PLL_CTRL_S(7) | 391 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 392 SUN4I_HDMI_PLL_CTRL_SDIV2 | 393 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 394 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 395 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 396 SUN4I_HDMI_PLL_CTRL_BWS | 397 SUN4I_HDMI_PLL_CTRL_PLL_EN, 398 399 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 400 .ddc_clk_pre_divider = 2, 401 .ddc_clk_m_offset = 1, 402 403 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 404 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 405 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 406 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 407 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 408 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 409 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 410 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 411 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 412 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 413 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 414 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 415 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 416 417 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 418 .ddc_fifo_has_dir = true, 419 }; 420 421 static const struct sun4i_hdmi_variant sun6i_variant = { 422 .has_ddc_parent_clk = true, 423 .has_reset_control = true, 424 .pad_ctrl0_init_val = 0xff | 425 SUN4I_HDMI_PAD_CTRL0_TXEN | 426 SUN4I_HDMI_PAD_CTRL0_CKEN | 427 SUN4I_HDMI_PAD_CTRL0_PWENG | 428 SUN4I_HDMI_PAD_CTRL0_PWEND | 429 SUN4I_HDMI_PAD_CTRL0_PWENC | 430 SUN4I_HDMI_PAD_CTRL0_LDODEN | 431 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 432 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 433 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 434 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 435 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 436 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 437 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 438 SUN4I_HDMI_PAD_CTRL1_PWSDT | 439 SUN4I_HDMI_PAD_CTRL1_PWSCK | 440 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 441 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 442 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 443 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 444 SUN4I_HDMI_PLL_CTRL_CS(3) | 445 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 446 SUN4I_HDMI_PLL_CTRL_S(4) | 447 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 448 SUN4I_HDMI_PLL_CTRL_SDIV2 | 449 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 450 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 451 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 452 SUN4I_HDMI_PLL_CTRL_PLL_EN, 453 454 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 455 .ddc_clk_pre_divider = 1, 456 .ddc_clk_m_offset = 2, 457 458 .tmds_clk_div_offset = 1, 459 460 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 461 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 462 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 463 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 464 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 465 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 466 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 467 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 468 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 469 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 470 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 471 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 472 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 473 474 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 475 .ddc_fifo_thres_incl = true, 476 }; 477 478 static const struct regmap_config sun4i_hdmi_regmap_config = { 479 .reg_bits = 32, 480 .val_bits = 32, 481 .reg_stride = 4, 482 .max_register = 0x580, 483 }; 484 485 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 486 void *data) 487 { 488 struct platform_device *pdev = to_platform_device(dev); 489 struct drm_device *drm = data; 490 struct cec_connector_info conn_info; 491 struct sun4i_drv *drv = drm->dev_private; 492 struct sun4i_hdmi *hdmi; 493 u32 reg; 494 int ret; 495 496 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 497 if (!hdmi) 498 return -ENOMEM; 499 dev_set_drvdata(dev, hdmi); 500 hdmi->dev = dev; 501 hdmi->drv = drv; 502 503 hdmi->variant = of_device_get_match_data(dev); 504 if (!hdmi->variant) 505 return -EINVAL; 506 507 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 508 if (IS_ERR(hdmi->base)) { 509 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 510 return PTR_ERR(hdmi->base); 511 } 512 513 if (hdmi->variant->has_reset_control) { 514 hdmi->reset = devm_reset_control_get(dev, NULL); 515 if (IS_ERR(hdmi->reset)) { 516 dev_err(dev, "Couldn't get the HDMI reset control\n"); 517 return PTR_ERR(hdmi->reset); 518 } 519 520 ret = reset_control_deassert(hdmi->reset); 521 if (ret) { 522 dev_err(dev, "Couldn't deassert HDMI reset\n"); 523 return ret; 524 } 525 } 526 527 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 528 if (IS_ERR(hdmi->bus_clk)) { 529 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 530 ret = PTR_ERR(hdmi->bus_clk); 531 goto err_assert_reset; 532 } 533 clk_prepare_enable(hdmi->bus_clk); 534 535 hdmi->mod_clk = devm_clk_get(dev, "mod"); 536 if (IS_ERR(hdmi->mod_clk)) { 537 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 538 ret = PTR_ERR(hdmi->mod_clk); 539 goto err_disable_bus_clk; 540 } 541 clk_prepare_enable(hdmi->mod_clk); 542 543 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 544 if (IS_ERR(hdmi->pll0_clk)) { 545 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 546 ret = PTR_ERR(hdmi->pll0_clk); 547 goto err_disable_mod_clk; 548 } 549 550 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 551 if (IS_ERR(hdmi->pll1_clk)) { 552 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 553 ret = PTR_ERR(hdmi->pll1_clk); 554 goto err_disable_mod_clk; 555 } 556 557 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 558 &sun4i_hdmi_regmap_config); 559 if (IS_ERR(hdmi->regmap)) { 560 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 561 ret = PTR_ERR(hdmi->regmap); 562 goto err_disable_mod_clk; 563 } 564 565 ret = sun4i_tmds_create(hdmi); 566 if (ret) { 567 dev_err(dev, "Couldn't create the TMDS clock\n"); 568 goto err_disable_mod_clk; 569 } 570 571 if (hdmi->variant->has_ddc_parent_clk) { 572 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 573 if (IS_ERR(hdmi->ddc_parent_clk)) { 574 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 575 ret = PTR_ERR(hdmi->ddc_parent_clk); 576 goto err_disable_mod_clk; 577 } 578 } else { 579 hdmi->ddc_parent_clk = hdmi->tmds_clk; 580 } 581 582 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 583 584 writel(hdmi->variant->pad_ctrl0_init_val, 585 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 586 587 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 588 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 589 reg |= hdmi->variant->pll_ctrl_init_val; 590 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 591 592 ret = sun4i_hdmi_i2c_create(dev, hdmi); 593 if (ret) { 594 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 595 goto err_disable_mod_clk; 596 } 597 598 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 599 if (IS_ERR(hdmi->ddc_i2c)) { 600 ret = PTR_ERR(hdmi->ddc_i2c); 601 if (ret == -ENODEV) 602 hdmi->ddc_i2c = NULL; 603 else 604 goto err_del_i2c_adapter; 605 } 606 607 drm_encoder_helper_add(&hdmi->encoder, 608 &sun4i_hdmi_helper_funcs); 609 ret = drm_simple_encoder_init(drm, &hdmi->encoder, 610 DRM_MODE_ENCODER_TMDS); 611 if (ret) { 612 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 613 goto err_put_ddc_i2c; 614 } 615 616 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 617 dev->of_node); 618 if (!hdmi->encoder.possible_crtcs) { 619 ret = -EPROBE_DEFER; 620 goto err_put_ddc_i2c; 621 } 622 623 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 624 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 625 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 626 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 627 if (ret < 0) 628 goto err_cleanup_connector; 629 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 630 hdmi->base + SUN4I_HDMI_CEC); 631 #endif 632 633 drm_connector_helper_add(&hdmi->connector, 634 &sun4i_hdmi_connector_helper_funcs); 635 ret = drm_connector_init_with_ddc(drm, &hdmi->connector, 636 &sun4i_hdmi_connector_funcs, 637 DRM_MODE_CONNECTOR_HDMIA, 638 hdmi->ddc_i2c); 639 if (ret) { 640 dev_err(dev, 641 "Couldn't initialise the HDMI connector\n"); 642 goto err_cleanup_connector; 643 } 644 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 645 cec_s_conn_info(hdmi->cec_adap, &conn_info); 646 647 /* There is no HPD interrupt, so we need to poll the controller */ 648 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 649 DRM_CONNECTOR_POLL_DISCONNECT; 650 651 ret = cec_register_adapter(hdmi->cec_adap, dev); 652 if (ret < 0) 653 goto err_cleanup_connector; 654 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 655 656 return 0; 657 658 err_cleanup_connector: 659 cec_delete_adapter(hdmi->cec_adap); 660 drm_encoder_cleanup(&hdmi->encoder); 661 err_put_ddc_i2c: 662 i2c_put_adapter(hdmi->ddc_i2c); 663 err_del_i2c_adapter: 664 i2c_del_adapter(hdmi->i2c); 665 err_disable_mod_clk: 666 clk_disable_unprepare(hdmi->mod_clk); 667 err_disable_bus_clk: 668 clk_disable_unprepare(hdmi->bus_clk); 669 err_assert_reset: 670 reset_control_assert(hdmi->reset); 671 return ret; 672 } 673 674 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 675 void *data) 676 { 677 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 678 679 cec_unregister_adapter(hdmi->cec_adap); 680 i2c_del_adapter(hdmi->i2c); 681 i2c_put_adapter(hdmi->ddc_i2c); 682 clk_disable_unprepare(hdmi->mod_clk); 683 clk_disable_unprepare(hdmi->bus_clk); 684 } 685 686 static const struct component_ops sun4i_hdmi_ops = { 687 .bind = sun4i_hdmi_bind, 688 .unbind = sun4i_hdmi_unbind, 689 }; 690 691 static int sun4i_hdmi_probe(struct platform_device *pdev) 692 { 693 return component_add(&pdev->dev, &sun4i_hdmi_ops); 694 } 695 696 static int sun4i_hdmi_remove(struct platform_device *pdev) 697 { 698 component_del(&pdev->dev, &sun4i_hdmi_ops); 699 700 return 0; 701 } 702 703 static const struct of_device_id sun4i_hdmi_of_table[] = { 704 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 705 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 706 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 707 { } 708 }; 709 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 710 711 static struct platform_driver sun4i_hdmi_driver = { 712 .probe = sun4i_hdmi_probe, 713 .remove = sun4i_hdmi_remove, 714 .driver = { 715 .name = "sun4i-hdmi", 716 .of_match_table = sun4i_hdmi_of_table, 717 }, 718 }; 719 module_platform_driver(sun4i_hdmi_driver); 720 721 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 722 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 723 MODULE_LICENSE("GPL"); 724