1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_edid.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 28 #include <drm/display/drm_hdmi_helper.h> 29 #include <drm/display/drm_hdmi_state_helper.h> 30 31 #include "sun4i_backend.h" 32 #include "sun4i_crtc.h" 33 #include "sun4i_drv.h" 34 #include "sun4i_hdmi.h" 35 36 #define drm_encoder_to_sun4i_hdmi(e) \ 37 container_of_const(e, struct sun4i_hdmi, encoder) 38 39 #define drm_connector_to_sun4i_hdmi(c) \ 40 container_of_const(c, struct sun4i_hdmi, connector) 41 42 static int sun4i_hdmi_clear_avi_infoframe(struct drm_connector *connector) 43 { 44 drm_warn_once(connector->dev, "clearing of AVI infoframe is not implemented\n"); 45 46 return 0; 47 } 48 49 static int sun4i_hdmi_write_avi_infoframe(struct drm_connector *connector, 50 const u8 *buffer, size_t len) 51 { 52 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 53 int i; 54 55 for (i = 0; i < len; i++) 56 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 57 58 return 0; 59 60 } 61 62 static int sun4i_hdmi_clear_hdmi_infoframe(struct drm_connector *connector) 63 { 64 drm_warn_once(connector->dev, "HDMI VSI not implemented\n"); 65 66 return 0; 67 } 68 69 static int sun4i_hdmi_write_hdmi_infoframe(struct drm_connector *connector, 70 const u8 *buffer, size_t len) 71 { 72 drm_warn_once(connector->dev, "HDMI VSI not implemented\n"); 73 74 return 0; 75 } 76 77 static void sun4i_hdmi_disable(struct drm_encoder *encoder, 78 struct drm_atomic_commit *state) 79 { 80 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 81 u32 val; 82 83 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 84 85 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 86 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 87 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 88 89 clk_disable_unprepare(hdmi->tmds_clk); 90 } 91 92 static void sun4i_hdmi_enable(struct drm_encoder *encoder, 93 struct drm_atomic_commit *state) 94 { 95 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 96 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 97 struct drm_connector *connector = &hdmi->connector; 98 struct drm_display_info *display = &connector->display_info; 99 struct drm_connector_state *conn_state = 100 drm_atomic_get_new_connector_state(state, connector); 101 unsigned long long tmds_rate = conn_state->hdmi.tmds_char_rate; 102 unsigned int x, y; 103 u32 val = 0; 104 105 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 106 107 clk_set_rate(hdmi->mod_clk, tmds_rate); 108 clk_set_rate(hdmi->tmds_clk, tmds_rate); 109 110 /* Set input sync enable */ 111 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 112 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 113 114 /* 115 * Setup output pad (?) controls 116 * 117 * This is done here instead of at probe/bind time because 118 * the controller seems to toggle some of the bits on its own. 119 * 120 * We can't just initialize the register there, we need to 121 * protect the clock bits that have already been read out and 122 * cached by the clock framework. 123 */ 124 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 125 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 126 val |= hdmi->variant->pad_ctrl1_init_val; 127 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 128 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 129 130 /* Setup timing registers */ 131 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 132 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 133 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 134 135 x = mode->htotal - mode->hsync_start; 136 y = mode->vtotal - mode->vsync_start; 137 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 138 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 139 140 x = mode->hsync_start - mode->hdisplay; 141 y = mode->vsync_start - mode->vdisplay; 142 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 143 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 144 145 x = mode->hsync_end - mode->hsync_start; 146 y = mode->vsync_end - mode->vsync_start; 147 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 148 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 149 150 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 151 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 152 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 153 154 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 155 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 156 157 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 158 159 clk_prepare_enable(hdmi->tmds_clk); 160 161 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 162 163 val = SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 164 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 165 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 166 167 val = SUN4I_HDMI_VID_CTRL_ENABLE; 168 if (display->is_hdmi) 169 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 170 171 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 172 } 173 174 static const struct drm_encoder_funcs sun4i_hdmi_funcs = { 175 .destroy = drm_encoder_cleanup, 176 }; 177 178 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 179 .atomic_disable = sun4i_hdmi_disable, 180 .atomic_enable = sun4i_hdmi_enable, 181 }; 182 183 static enum drm_mode_status 184 sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector, 185 const struct drm_display_mode *mode, 186 unsigned long long clock) 187 { 188 const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 189 unsigned long diff = div_u64(clock, 200); /* +-0.5% allowed by HDMI spec */ 190 long rounded_rate; 191 192 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 193 return MODE_BAD; 194 195 /* HDMI 1.0 max TMDS character rate */ 196 if (clock > HDMI_1_0_TMDS_CHAR_RATE_MAX_HZ) 197 return MODE_CLOCK_HIGH; 198 199 rounded_rate = clk_round_rate(hdmi->tmds_clk, clock); 200 if (rounded_rate > 0 && 201 max_t(unsigned long, rounded_rate, clock) - 202 min_t(unsigned long, rounded_rate, clock) < diff) 203 return MODE_OK; 204 205 return MODE_NOCLOCK; 206 } 207 208 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 209 { 210 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 211 const struct drm_edid *drm_edid; 212 int ret; 213 214 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c); 215 216 drm_edid_connector_update(connector, drm_edid); 217 cec_s_phys_addr(hdmi->cec_adap, 218 connector->display_info.source_physical_address, false); 219 220 if (!drm_edid) 221 return 0; 222 223 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 224 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 225 226 227 ret = drm_edid_connector_add_modes(connector); 228 drm_edid_free(drm_edid); 229 230 return ret; 231 } 232 233 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 234 { 235 struct device_node *phandle, *remote; 236 struct i2c_adapter *ddc; 237 238 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 239 if (!remote) 240 return ERR_PTR(-EINVAL); 241 242 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 243 of_node_put(remote); 244 if (!phandle) 245 return ERR_PTR(-ENODEV); 246 247 ddc = of_get_i2c_adapter_by_node(phandle); 248 of_node_put(phandle); 249 if (!ddc) 250 return ERR_PTR(-EPROBE_DEFER); 251 252 return ddc; 253 } 254 255 static const struct drm_connector_hdmi_funcs sun4i_hdmi_hdmi_connector_funcs = { 256 .tmds_char_rate_valid = sun4i_hdmi_connector_clock_valid, 257 .avi = { 258 .clear_infoframe = sun4i_hdmi_clear_avi_infoframe, 259 .write_infoframe = sun4i_hdmi_write_avi_infoframe, 260 }, 261 .hdmi = { 262 .clear_infoframe = sun4i_hdmi_clear_hdmi_infoframe, 263 .write_infoframe = sun4i_hdmi_write_hdmi_infoframe, 264 }, 265 }; 266 267 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 268 .atomic_check = drm_atomic_helper_connector_hdmi_check, 269 .mode_valid = drm_hdmi_connector_mode_valid, 270 .get_modes = sun4i_hdmi_get_modes, 271 }; 272 273 static enum drm_connector_status 274 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 275 { 276 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 277 unsigned long reg; 278 279 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 280 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 281 cec_phys_addr_invalidate(hdmi->cec_adap); 282 return connector_status_disconnected; 283 } 284 285 return connector_status_connected; 286 } 287 288 static void sun4i_hdmi_connector_reset(struct drm_connector *connector) 289 { 290 drm_atomic_helper_connector_reset(connector); 291 __drm_atomic_helper_connector_hdmi_state_init(connector, connector->state); 292 } 293 294 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 295 .detect = sun4i_hdmi_connector_detect, 296 .fill_modes = drm_helper_probe_single_connector_modes, 297 .reset = sun4i_hdmi_connector_reset, 298 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 299 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 300 }; 301 302 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 303 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 304 { 305 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 306 307 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 308 } 309 310 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 311 { 312 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 313 314 /* Start driving the CEC pin low */ 315 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 316 } 317 318 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 319 { 320 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 321 322 /* 323 * Stop driving the CEC pin, the pull up will take over 324 * unless another CEC device is driving the pin low. 325 */ 326 writel(0, hdmi->base + SUN4I_HDMI_CEC); 327 } 328 329 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 330 .read = sun4i_hdmi_cec_pin_read, 331 .low = sun4i_hdmi_cec_pin_low, 332 .high = sun4i_hdmi_cec_pin_high, 333 }; 334 #endif 335 336 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 337 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 338 339 /* Only difference from sun5i is AMP is 4 instead of 6 */ 340 static const struct sun4i_hdmi_variant sun4i_variant = { 341 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 342 SUN4I_HDMI_PAD_CTRL0_CKEN | 343 SUN4I_HDMI_PAD_CTRL0_PWENG | 344 SUN4I_HDMI_PAD_CTRL0_PWEND | 345 SUN4I_HDMI_PAD_CTRL0_PWENC | 346 SUN4I_HDMI_PAD_CTRL0_LDODEN | 347 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 348 SUN4I_HDMI_PAD_CTRL0_BIASEN, 349 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 350 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 351 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 352 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 353 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 354 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 355 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 356 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 357 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 358 SUN4I_HDMI_PLL_CTRL_CS(7) | 359 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 360 SUN4I_HDMI_PLL_CTRL_S(7) | 361 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 362 SUN4I_HDMI_PLL_CTRL_SDIV2 | 363 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 364 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 365 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 366 SUN4I_HDMI_PLL_CTRL_BWS | 367 SUN4I_HDMI_PLL_CTRL_PLL_EN, 368 369 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 370 .ddc_clk_pre_divider = 2, 371 .ddc_clk_m_offset = 1, 372 373 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 374 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 375 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 376 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 377 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 378 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 379 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 380 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 381 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 382 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 383 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 384 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 385 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 386 387 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 388 .ddc_fifo_has_dir = true, 389 }; 390 391 static const struct sun4i_hdmi_variant sun5i_variant = { 392 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 393 SUN4I_HDMI_PAD_CTRL0_CKEN | 394 SUN4I_HDMI_PAD_CTRL0_PWENG | 395 SUN4I_HDMI_PAD_CTRL0_PWEND | 396 SUN4I_HDMI_PAD_CTRL0_PWENC | 397 SUN4I_HDMI_PAD_CTRL0_LDODEN | 398 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 399 SUN4I_HDMI_PAD_CTRL0_BIASEN, 400 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 401 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 402 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 403 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 404 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 405 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 406 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 407 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 408 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 409 SUN4I_HDMI_PLL_CTRL_CS(7) | 410 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 411 SUN4I_HDMI_PLL_CTRL_S(7) | 412 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 413 SUN4I_HDMI_PLL_CTRL_SDIV2 | 414 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 415 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 416 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 417 SUN4I_HDMI_PLL_CTRL_BWS | 418 SUN4I_HDMI_PLL_CTRL_PLL_EN, 419 420 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 421 .ddc_clk_pre_divider = 2, 422 .ddc_clk_m_offset = 1, 423 424 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 425 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 426 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 427 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 428 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 429 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 430 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 431 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 432 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 433 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 434 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 435 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 436 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 437 438 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 439 .ddc_fifo_has_dir = true, 440 }; 441 442 static const struct sun4i_hdmi_variant sun6i_variant = { 443 .has_ddc_parent_clk = true, 444 .has_reset_control = true, 445 .pad_ctrl0_init_val = 0xff | 446 SUN4I_HDMI_PAD_CTRL0_TXEN | 447 SUN4I_HDMI_PAD_CTRL0_CKEN | 448 SUN4I_HDMI_PAD_CTRL0_PWENG | 449 SUN4I_HDMI_PAD_CTRL0_PWEND | 450 SUN4I_HDMI_PAD_CTRL0_PWENC | 451 SUN4I_HDMI_PAD_CTRL0_LDODEN | 452 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 453 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 454 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 455 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 456 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 457 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 458 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 459 SUN4I_HDMI_PAD_CTRL1_PWSDT | 460 SUN4I_HDMI_PAD_CTRL1_PWSCK | 461 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 462 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 463 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 464 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 465 SUN4I_HDMI_PLL_CTRL_CS(3) | 466 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 467 SUN4I_HDMI_PLL_CTRL_S(4) | 468 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 469 SUN4I_HDMI_PLL_CTRL_SDIV2 | 470 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 471 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 472 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 473 SUN4I_HDMI_PLL_CTRL_PLL_EN, 474 475 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 476 .ddc_clk_pre_divider = 1, 477 .ddc_clk_m_offset = 2, 478 479 .tmds_clk_div_offset = 1, 480 481 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 482 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 483 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 484 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 485 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 486 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 487 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 488 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 489 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 490 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 491 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 492 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 493 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 494 495 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 496 .ddc_fifo_thres_incl = true, 497 }; 498 499 static const struct regmap_config sun4i_hdmi_regmap_config = { 500 .reg_bits = 32, 501 .val_bits = 32, 502 .reg_stride = 4, 503 .max_register = 0x580, 504 }; 505 506 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 507 void *data) 508 { 509 struct platform_device *pdev = to_platform_device(dev); 510 struct drm_device *drm = data; 511 struct cec_connector_info conn_info; 512 struct sun4i_drv *drv = drm->dev_private; 513 struct sun4i_hdmi *hdmi; 514 u32 reg; 515 int ret; 516 517 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 518 if (!hdmi) 519 return -ENOMEM; 520 dev_set_drvdata(dev, hdmi); 521 hdmi->dev = dev; 522 hdmi->drv = drv; 523 524 hdmi->variant = of_device_get_match_data(dev); 525 if (!hdmi->variant) 526 return -EINVAL; 527 528 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 529 if (IS_ERR(hdmi->base)) { 530 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 531 return PTR_ERR(hdmi->base); 532 } 533 534 if (hdmi->variant->has_reset_control) { 535 hdmi->reset = devm_reset_control_get(dev, NULL); 536 if (IS_ERR(hdmi->reset)) { 537 dev_err(dev, "Couldn't get the HDMI reset control\n"); 538 return PTR_ERR(hdmi->reset); 539 } 540 541 ret = reset_control_deassert(hdmi->reset); 542 if (ret) { 543 dev_err(dev, "Couldn't deassert HDMI reset\n"); 544 return ret; 545 } 546 } 547 548 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 549 if (IS_ERR(hdmi->bus_clk)) { 550 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 551 ret = PTR_ERR(hdmi->bus_clk); 552 goto err_assert_reset; 553 } 554 clk_prepare_enable(hdmi->bus_clk); 555 556 hdmi->mod_clk = devm_clk_get(dev, "mod"); 557 if (IS_ERR(hdmi->mod_clk)) { 558 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 559 ret = PTR_ERR(hdmi->mod_clk); 560 goto err_disable_bus_clk; 561 } 562 clk_prepare_enable(hdmi->mod_clk); 563 564 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 565 if (IS_ERR(hdmi->pll0_clk)) { 566 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 567 ret = PTR_ERR(hdmi->pll0_clk); 568 goto err_disable_mod_clk; 569 } 570 571 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 572 if (IS_ERR(hdmi->pll1_clk)) { 573 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 574 ret = PTR_ERR(hdmi->pll1_clk); 575 goto err_disable_mod_clk; 576 } 577 578 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 579 &sun4i_hdmi_regmap_config); 580 if (IS_ERR(hdmi->regmap)) { 581 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 582 ret = PTR_ERR(hdmi->regmap); 583 goto err_disable_mod_clk; 584 } 585 586 ret = sun4i_tmds_create(hdmi); 587 if (ret) { 588 dev_err(dev, "Couldn't create the TMDS clock\n"); 589 goto err_disable_mod_clk; 590 } 591 592 if (hdmi->variant->has_ddc_parent_clk) { 593 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 594 if (IS_ERR(hdmi->ddc_parent_clk)) { 595 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 596 ret = PTR_ERR(hdmi->ddc_parent_clk); 597 goto err_disable_mod_clk; 598 } 599 } else { 600 hdmi->ddc_parent_clk = hdmi->tmds_clk; 601 } 602 603 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 604 605 writel(hdmi->variant->pad_ctrl0_init_val, 606 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 607 608 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 609 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 610 reg |= hdmi->variant->pll_ctrl_init_val; 611 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 612 613 ret = sun4i_hdmi_i2c_create(dev, hdmi); 614 if (ret) { 615 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 616 goto err_disable_mod_clk; 617 } 618 619 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 620 if (IS_ERR(hdmi->ddc_i2c)) { 621 ret = PTR_ERR(hdmi->ddc_i2c); 622 if (ret == -ENODEV) 623 hdmi->ddc_i2c = NULL; 624 else 625 goto err_del_i2c_adapter; 626 } 627 628 drm_encoder_helper_add(&hdmi->encoder, 629 &sun4i_hdmi_helper_funcs); 630 ret = drm_encoder_init(drm, &hdmi->encoder, &sun4i_hdmi_funcs, 631 DRM_MODE_ENCODER_TMDS, NULL); 632 if (ret) { 633 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 634 goto err_put_ddc_i2c; 635 } 636 637 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 638 dev->of_node); 639 if (!hdmi->encoder.possible_crtcs) { 640 ret = -EPROBE_DEFER; 641 goto err_put_ddc_i2c; 642 } 643 644 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 645 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 646 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 647 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 648 if (ret < 0) 649 goto err_cleanup_connector; 650 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 651 hdmi->base + SUN4I_HDMI_CEC); 652 #endif 653 654 drm_connector_helper_add(&hdmi->connector, 655 &sun4i_hdmi_connector_helper_funcs); 656 ret = drmm_connector_hdmi_init(drm, &hdmi->connector, 657 /* 658 * NOTE: Those are likely to be 659 * wrong, but I couldn't find the 660 * actual ones in the BSP. 661 */ 662 "AW", "HDMI", 663 &sun4i_hdmi_connector_funcs, 664 &sun4i_hdmi_hdmi_connector_funcs, 665 DRM_MODE_CONNECTOR_HDMIA, 666 hdmi->ddc_i2c, 667 BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444), 668 8); 669 if (ret) { 670 dev_err(dev, 671 "Couldn't initialise the HDMI connector\n"); 672 goto err_cleanup_connector; 673 } 674 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 675 cec_s_conn_info(hdmi->cec_adap, &conn_info); 676 677 /* There is no HPD interrupt, so we need to poll the controller */ 678 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 679 DRM_CONNECTOR_POLL_DISCONNECT; 680 681 ret = cec_register_adapter(hdmi->cec_adap, dev); 682 if (ret < 0) 683 goto err_cleanup_connector; 684 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 685 686 return 0; 687 688 err_cleanup_connector: 689 cec_delete_adapter(hdmi->cec_adap); 690 drm_encoder_cleanup(&hdmi->encoder); 691 err_put_ddc_i2c: 692 i2c_put_adapter(hdmi->ddc_i2c); 693 err_del_i2c_adapter: 694 i2c_del_adapter(hdmi->i2c); 695 err_disable_mod_clk: 696 clk_disable_unprepare(hdmi->mod_clk); 697 err_disable_bus_clk: 698 clk_disable_unprepare(hdmi->bus_clk); 699 err_assert_reset: 700 reset_control_assert(hdmi->reset); 701 return ret; 702 } 703 704 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 705 void *data) 706 { 707 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 708 709 cec_unregister_adapter(hdmi->cec_adap); 710 i2c_del_adapter(hdmi->i2c); 711 i2c_put_adapter(hdmi->ddc_i2c); 712 clk_disable_unprepare(hdmi->mod_clk); 713 clk_disable_unprepare(hdmi->bus_clk); 714 } 715 716 static const struct component_ops sun4i_hdmi_ops = { 717 .bind = sun4i_hdmi_bind, 718 .unbind = sun4i_hdmi_unbind, 719 }; 720 721 static int sun4i_hdmi_probe(struct platform_device *pdev) 722 { 723 return component_add(&pdev->dev, &sun4i_hdmi_ops); 724 } 725 726 static void sun4i_hdmi_remove(struct platform_device *pdev) 727 { 728 component_del(&pdev->dev, &sun4i_hdmi_ops); 729 } 730 731 static const struct of_device_id sun4i_hdmi_of_table[] = { 732 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 733 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 734 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 735 { } 736 }; 737 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 738 739 static struct platform_driver sun4i_hdmi_driver = { 740 .probe = sun4i_hdmi_probe, 741 .remove = sun4i_hdmi_remove, 742 .driver = { 743 .name = "sun4i-hdmi", 744 .of_match_table = sun4i_hdmi_of_table, 745 }, 746 }; 747 module_platform_driver(sun4i_hdmi_driver); 748 749 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 750 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 751 MODULE_LICENSE("GPL"); 752