1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_edid.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include <drm/display/drm_hdmi_helper.h> 30 #include <drm/display/drm_hdmi_state_helper.h> 31 32 #include "sun4i_backend.h" 33 #include "sun4i_crtc.h" 34 #include "sun4i_drv.h" 35 #include "sun4i_hdmi.h" 36 37 #define drm_encoder_to_sun4i_hdmi(e) \ 38 container_of_const(e, struct sun4i_hdmi, encoder) 39 40 #define drm_connector_to_sun4i_hdmi(c) \ 41 container_of_const(c, struct sun4i_hdmi, connector) 42 43 static int sun4i_hdmi_clear_avi_infoframe(struct drm_connector *connector) 44 { 45 drm_warn_once(connector->dev, "clearing of AVI infoframe is not implemented\n"); 46 47 return 0; 48 } 49 50 static int sun4i_hdmi_write_avi_infoframe(struct drm_connector *connector, 51 const u8 *buffer, size_t len) 52 { 53 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 54 int i; 55 56 for (i = 0; i < len; i++) 57 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 58 59 return 0; 60 61 } 62 63 static int sun4i_hdmi_clear_hdmi_infoframe(struct drm_connector *connector) 64 { 65 drm_warn_once(connector->dev, "HDMI VSI not implemented\n"); 66 67 return 0; 68 } 69 70 static int sun4i_hdmi_write_hdmi_infoframe(struct drm_connector *connector, 71 const u8 *buffer, size_t len) 72 { 73 drm_warn_once(connector->dev, "HDMI VSI not implemented\n"); 74 75 return 0; 76 } 77 78 static void sun4i_hdmi_disable(struct drm_encoder *encoder, 79 struct drm_atomic_state *state) 80 { 81 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 82 u32 val; 83 84 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 85 86 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 87 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 88 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 89 90 clk_disable_unprepare(hdmi->tmds_clk); 91 } 92 93 static void sun4i_hdmi_enable(struct drm_encoder *encoder, 94 struct drm_atomic_state *state) 95 { 96 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 97 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 98 struct drm_connector *connector = &hdmi->connector; 99 struct drm_display_info *display = &connector->display_info; 100 struct drm_connector_state *conn_state = 101 drm_atomic_get_new_connector_state(state, connector); 102 unsigned long long tmds_rate = conn_state->hdmi.tmds_char_rate; 103 unsigned int x, y; 104 u32 val = 0; 105 106 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 107 108 clk_set_rate(hdmi->mod_clk, tmds_rate); 109 clk_set_rate(hdmi->tmds_clk, tmds_rate); 110 111 /* Set input sync enable */ 112 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 113 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 114 115 /* 116 * Setup output pad (?) controls 117 * 118 * This is done here instead of at probe/bind time because 119 * the controller seems to toggle some of the bits on its own. 120 * 121 * We can't just initialize the register there, we need to 122 * protect the clock bits that have already been read out and 123 * cached by the clock framework. 124 */ 125 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 126 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 127 val |= hdmi->variant->pad_ctrl1_init_val; 128 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 129 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 130 131 /* Setup timing registers */ 132 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 133 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 134 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 135 136 x = mode->htotal - mode->hsync_start; 137 y = mode->vtotal - mode->vsync_start; 138 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 139 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 140 141 x = mode->hsync_start - mode->hdisplay; 142 y = mode->vsync_start - mode->vdisplay; 143 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 144 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 145 146 x = mode->hsync_end - mode->hsync_start; 147 y = mode->vsync_end - mode->vsync_start; 148 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 149 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 150 151 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 152 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 153 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 154 155 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 156 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 157 158 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 159 160 clk_prepare_enable(hdmi->tmds_clk); 161 162 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 163 164 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 165 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 166 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 167 168 val = SUN4I_HDMI_VID_CTRL_ENABLE; 169 if (display->is_hdmi) 170 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 171 172 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 173 } 174 175 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 176 .atomic_disable = sun4i_hdmi_disable, 177 .atomic_enable = sun4i_hdmi_enable, 178 }; 179 180 static enum drm_mode_status 181 sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector, 182 const struct drm_display_mode *mode, 183 unsigned long long clock) 184 { 185 const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 186 unsigned long diff = div_u64(clock, 200); /* +-0.5% allowed by HDMI spec */ 187 long rounded_rate; 188 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 190 return MODE_BAD; 191 192 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 193 if (clock > 165000000) 194 return MODE_CLOCK_HIGH; 195 196 rounded_rate = clk_round_rate(hdmi->tmds_clk, clock); 197 if (rounded_rate > 0 && 198 max_t(unsigned long, rounded_rate, clock) - 199 min_t(unsigned long, rounded_rate, clock) < diff) 200 return MODE_OK; 201 202 return MODE_NOCLOCK; 203 } 204 205 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 206 { 207 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 208 const struct drm_edid *drm_edid; 209 int ret; 210 211 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c); 212 213 drm_edid_connector_update(connector, drm_edid); 214 cec_s_phys_addr(hdmi->cec_adap, 215 connector->display_info.source_physical_address, false); 216 217 if (!drm_edid) 218 return 0; 219 220 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 221 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 222 223 224 ret = drm_edid_connector_add_modes(connector); 225 drm_edid_free(drm_edid); 226 227 return ret; 228 } 229 230 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 231 { 232 struct device_node *phandle, *remote; 233 struct i2c_adapter *ddc; 234 235 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 236 if (!remote) 237 return ERR_PTR(-EINVAL); 238 239 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 240 of_node_put(remote); 241 if (!phandle) 242 return ERR_PTR(-ENODEV); 243 244 ddc = of_get_i2c_adapter_by_node(phandle); 245 of_node_put(phandle); 246 if (!ddc) 247 return ERR_PTR(-EPROBE_DEFER); 248 249 return ddc; 250 } 251 252 static const struct drm_connector_hdmi_funcs sun4i_hdmi_hdmi_connector_funcs = { 253 .tmds_char_rate_valid = sun4i_hdmi_connector_clock_valid, 254 .avi = { 255 .clear_infoframe = sun4i_hdmi_clear_avi_infoframe, 256 .write_infoframe = sun4i_hdmi_write_avi_infoframe, 257 }, 258 .hdmi = { 259 .clear_infoframe = sun4i_hdmi_clear_hdmi_infoframe, 260 .write_infoframe = sun4i_hdmi_write_hdmi_infoframe, 261 }, 262 }; 263 264 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 265 .atomic_check = drm_atomic_helper_connector_hdmi_check, 266 .mode_valid = drm_hdmi_connector_mode_valid, 267 .get_modes = sun4i_hdmi_get_modes, 268 }; 269 270 static enum drm_connector_status 271 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 272 { 273 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 274 unsigned long reg; 275 276 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 277 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 278 cec_phys_addr_invalidate(hdmi->cec_adap); 279 return connector_status_disconnected; 280 } 281 282 return connector_status_connected; 283 } 284 285 static void sun4i_hdmi_connector_reset(struct drm_connector *connector) 286 { 287 drm_atomic_helper_connector_reset(connector); 288 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 289 } 290 291 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 292 .detect = sun4i_hdmi_connector_detect, 293 .fill_modes = drm_helper_probe_single_connector_modes, 294 .reset = sun4i_hdmi_connector_reset, 295 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 296 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 297 }; 298 299 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 300 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 301 { 302 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 303 304 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 305 } 306 307 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 308 { 309 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 310 311 /* Start driving the CEC pin low */ 312 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 313 } 314 315 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 316 { 317 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 318 319 /* 320 * Stop driving the CEC pin, the pull up will take over 321 * unless another CEC device is driving the pin low. 322 */ 323 writel(0, hdmi->base + SUN4I_HDMI_CEC); 324 } 325 326 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 327 .read = sun4i_hdmi_cec_pin_read, 328 .low = sun4i_hdmi_cec_pin_low, 329 .high = sun4i_hdmi_cec_pin_high, 330 }; 331 #endif 332 333 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 334 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 335 336 /* Only difference from sun5i is AMP is 4 instead of 6 */ 337 static const struct sun4i_hdmi_variant sun4i_variant = { 338 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 339 SUN4I_HDMI_PAD_CTRL0_CKEN | 340 SUN4I_HDMI_PAD_CTRL0_PWENG | 341 SUN4I_HDMI_PAD_CTRL0_PWEND | 342 SUN4I_HDMI_PAD_CTRL0_PWENC | 343 SUN4I_HDMI_PAD_CTRL0_LDODEN | 344 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 345 SUN4I_HDMI_PAD_CTRL0_BIASEN, 346 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 347 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 348 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 349 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 350 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 351 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 352 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 353 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 354 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 355 SUN4I_HDMI_PLL_CTRL_CS(7) | 356 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 357 SUN4I_HDMI_PLL_CTRL_S(7) | 358 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 359 SUN4I_HDMI_PLL_CTRL_SDIV2 | 360 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 361 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 362 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 363 SUN4I_HDMI_PLL_CTRL_BWS | 364 SUN4I_HDMI_PLL_CTRL_PLL_EN, 365 366 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 367 .ddc_clk_pre_divider = 2, 368 .ddc_clk_m_offset = 1, 369 370 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 371 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 372 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 373 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 374 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 375 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 376 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 377 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 378 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 379 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 380 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 381 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 382 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 383 384 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 385 .ddc_fifo_has_dir = true, 386 }; 387 388 static const struct sun4i_hdmi_variant sun5i_variant = { 389 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 390 SUN4I_HDMI_PAD_CTRL0_CKEN | 391 SUN4I_HDMI_PAD_CTRL0_PWENG | 392 SUN4I_HDMI_PAD_CTRL0_PWEND | 393 SUN4I_HDMI_PAD_CTRL0_PWENC | 394 SUN4I_HDMI_PAD_CTRL0_LDODEN | 395 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 396 SUN4I_HDMI_PAD_CTRL0_BIASEN, 397 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 398 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 399 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 400 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 401 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 402 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 403 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 404 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 405 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 406 SUN4I_HDMI_PLL_CTRL_CS(7) | 407 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 408 SUN4I_HDMI_PLL_CTRL_S(7) | 409 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 410 SUN4I_HDMI_PLL_CTRL_SDIV2 | 411 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 412 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 413 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 414 SUN4I_HDMI_PLL_CTRL_BWS | 415 SUN4I_HDMI_PLL_CTRL_PLL_EN, 416 417 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 418 .ddc_clk_pre_divider = 2, 419 .ddc_clk_m_offset = 1, 420 421 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 422 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 423 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 424 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 425 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 426 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 427 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 428 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 429 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 430 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 431 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 432 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 433 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 434 435 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 436 .ddc_fifo_has_dir = true, 437 }; 438 439 static const struct sun4i_hdmi_variant sun6i_variant = { 440 .has_ddc_parent_clk = true, 441 .has_reset_control = true, 442 .pad_ctrl0_init_val = 0xff | 443 SUN4I_HDMI_PAD_CTRL0_TXEN | 444 SUN4I_HDMI_PAD_CTRL0_CKEN | 445 SUN4I_HDMI_PAD_CTRL0_PWENG | 446 SUN4I_HDMI_PAD_CTRL0_PWEND | 447 SUN4I_HDMI_PAD_CTRL0_PWENC | 448 SUN4I_HDMI_PAD_CTRL0_LDODEN | 449 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 450 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 451 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 452 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 453 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 454 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 455 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 456 SUN4I_HDMI_PAD_CTRL1_PWSDT | 457 SUN4I_HDMI_PAD_CTRL1_PWSCK | 458 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 459 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 460 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 461 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 462 SUN4I_HDMI_PLL_CTRL_CS(3) | 463 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 464 SUN4I_HDMI_PLL_CTRL_S(4) | 465 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 466 SUN4I_HDMI_PLL_CTRL_SDIV2 | 467 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 468 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 469 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 470 SUN4I_HDMI_PLL_CTRL_PLL_EN, 471 472 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 473 .ddc_clk_pre_divider = 1, 474 .ddc_clk_m_offset = 2, 475 476 .tmds_clk_div_offset = 1, 477 478 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 479 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 480 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 481 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 482 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 483 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 484 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 485 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 486 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 487 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 488 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 489 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 490 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 491 492 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 493 .ddc_fifo_thres_incl = true, 494 }; 495 496 static const struct regmap_config sun4i_hdmi_regmap_config = { 497 .reg_bits = 32, 498 .val_bits = 32, 499 .reg_stride = 4, 500 .max_register = 0x580, 501 }; 502 503 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 504 void *data) 505 { 506 struct platform_device *pdev = to_platform_device(dev); 507 struct drm_device *drm = data; 508 struct cec_connector_info conn_info; 509 struct sun4i_drv *drv = drm->dev_private; 510 struct sun4i_hdmi *hdmi; 511 u32 reg; 512 int ret; 513 514 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 515 if (!hdmi) 516 return -ENOMEM; 517 dev_set_drvdata(dev, hdmi); 518 hdmi->dev = dev; 519 hdmi->drv = drv; 520 521 hdmi->variant = of_device_get_match_data(dev); 522 if (!hdmi->variant) 523 return -EINVAL; 524 525 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 526 if (IS_ERR(hdmi->base)) { 527 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 528 return PTR_ERR(hdmi->base); 529 } 530 531 if (hdmi->variant->has_reset_control) { 532 hdmi->reset = devm_reset_control_get(dev, NULL); 533 if (IS_ERR(hdmi->reset)) { 534 dev_err(dev, "Couldn't get the HDMI reset control\n"); 535 return PTR_ERR(hdmi->reset); 536 } 537 538 ret = reset_control_deassert(hdmi->reset); 539 if (ret) { 540 dev_err(dev, "Couldn't deassert HDMI reset\n"); 541 return ret; 542 } 543 } 544 545 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 546 if (IS_ERR(hdmi->bus_clk)) { 547 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 548 ret = PTR_ERR(hdmi->bus_clk); 549 goto err_assert_reset; 550 } 551 clk_prepare_enable(hdmi->bus_clk); 552 553 hdmi->mod_clk = devm_clk_get(dev, "mod"); 554 if (IS_ERR(hdmi->mod_clk)) { 555 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 556 ret = PTR_ERR(hdmi->mod_clk); 557 goto err_disable_bus_clk; 558 } 559 clk_prepare_enable(hdmi->mod_clk); 560 561 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 562 if (IS_ERR(hdmi->pll0_clk)) { 563 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 564 ret = PTR_ERR(hdmi->pll0_clk); 565 goto err_disable_mod_clk; 566 } 567 568 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 569 if (IS_ERR(hdmi->pll1_clk)) { 570 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 571 ret = PTR_ERR(hdmi->pll1_clk); 572 goto err_disable_mod_clk; 573 } 574 575 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 576 &sun4i_hdmi_regmap_config); 577 if (IS_ERR(hdmi->regmap)) { 578 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 579 ret = PTR_ERR(hdmi->regmap); 580 goto err_disable_mod_clk; 581 } 582 583 ret = sun4i_tmds_create(hdmi); 584 if (ret) { 585 dev_err(dev, "Couldn't create the TMDS clock\n"); 586 goto err_disable_mod_clk; 587 } 588 589 if (hdmi->variant->has_ddc_parent_clk) { 590 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 591 if (IS_ERR(hdmi->ddc_parent_clk)) { 592 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 593 ret = PTR_ERR(hdmi->ddc_parent_clk); 594 goto err_disable_mod_clk; 595 } 596 } else { 597 hdmi->ddc_parent_clk = hdmi->tmds_clk; 598 } 599 600 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 601 602 writel(hdmi->variant->pad_ctrl0_init_val, 603 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 604 605 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 606 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 607 reg |= hdmi->variant->pll_ctrl_init_val; 608 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 609 610 ret = sun4i_hdmi_i2c_create(dev, hdmi); 611 if (ret) { 612 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 613 goto err_disable_mod_clk; 614 } 615 616 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 617 if (IS_ERR(hdmi->ddc_i2c)) { 618 ret = PTR_ERR(hdmi->ddc_i2c); 619 if (ret == -ENODEV) 620 hdmi->ddc_i2c = NULL; 621 else 622 goto err_del_i2c_adapter; 623 } 624 625 drm_encoder_helper_add(&hdmi->encoder, 626 &sun4i_hdmi_helper_funcs); 627 ret = drm_simple_encoder_init(drm, &hdmi->encoder, 628 DRM_MODE_ENCODER_TMDS); 629 if (ret) { 630 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 631 goto err_put_ddc_i2c; 632 } 633 634 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 635 dev->of_node); 636 if (!hdmi->encoder.possible_crtcs) { 637 ret = -EPROBE_DEFER; 638 goto err_put_ddc_i2c; 639 } 640 641 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 642 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 643 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 644 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 645 if (ret < 0) 646 goto err_cleanup_connector; 647 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 648 hdmi->base + SUN4I_HDMI_CEC); 649 #endif 650 651 drm_connector_helper_add(&hdmi->connector, 652 &sun4i_hdmi_connector_helper_funcs); 653 ret = drmm_connector_hdmi_init(drm, &hdmi->connector, 654 /* 655 * NOTE: Those are likely to be 656 * wrong, but I couldn't find the 657 * actual ones in the BSP. 658 */ 659 "AW", "HDMI", 660 &sun4i_hdmi_connector_funcs, 661 &sun4i_hdmi_hdmi_connector_funcs, 662 DRM_MODE_CONNECTOR_HDMIA, 663 hdmi->ddc_i2c, 664 BIT(HDMI_COLORSPACE_RGB), 665 8); 666 if (ret) { 667 dev_err(dev, 668 "Couldn't initialise the HDMI connector\n"); 669 goto err_cleanup_connector; 670 } 671 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 672 cec_s_conn_info(hdmi->cec_adap, &conn_info); 673 674 /* There is no HPD interrupt, so we need to poll the controller */ 675 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 676 DRM_CONNECTOR_POLL_DISCONNECT; 677 678 ret = cec_register_adapter(hdmi->cec_adap, dev); 679 if (ret < 0) 680 goto err_cleanup_connector; 681 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 682 683 return 0; 684 685 err_cleanup_connector: 686 cec_delete_adapter(hdmi->cec_adap); 687 drm_encoder_cleanup(&hdmi->encoder); 688 err_put_ddc_i2c: 689 i2c_put_adapter(hdmi->ddc_i2c); 690 err_del_i2c_adapter: 691 i2c_del_adapter(hdmi->i2c); 692 err_disable_mod_clk: 693 clk_disable_unprepare(hdmi->mod_clk); 694 err_disable_bus_clk: 695 clk_disable_unprepare(hdmi->bus_clk); 696 err_assert_reset: 697 reset_control_assert(hdmi->reset); 698 return ret; 699 } 700 701 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 702 void *data) 703 { 704 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 705 706 cec_unregister_adapter(hdmi->cec_adap); 707 i2c_del_adapter(hdmi->i2c); 708 i2c_put_adapter(hdmi->ddc_i2c); 709 clk_disable_unprepare(hdmi->mod_clk); 710 clk_disable_unprepare(hdmi->bus_clk); 711 } 712 713 static const struct component_ops sun4i_hdmi_ops = { 714 .bind = sun4i_hdmi_bind, 715 .unbind = sun4i_hdmi_unbind, 716 }; 717 718 static int sun4i_hdmi_probe(struct platform_device *pdev) 719 { 720 return component_add(&pdev->dev, &sun4i_hdmi_ops); 721 } 722 723 static void sun4i_hdmi_remove(struct platform_device *pdev) 724 { 725 component_del(&pdev->dev, &sun4i_hdmi_ops); 726 } 727 728 static const struct of_device_id sun4i_hdmi_of_table[] = { 729 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 730 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 731 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 732 { } 733 }; 734 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 735 736 static struct platform_driver sun4i_hdmi_driver = { 737 .probe = sun4i_hdmi_probe, 738 .remove = sun4i_hdmi_remove, 739 .driver = { 740 .name = "sun4i-hdmi", 741 .of_match_table = sun4i_hdmi_of_table, 742 }, 743 }; 744 module_platform_driver(sun4i_hdmi_driver); 745 746 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 747 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 748 MODULE_LICENSE("GPL"); 749