1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_edid.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_print.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include "sun4i_backend.h" 30 #include "sun4i_crtc.h" 31 #include "sun4i_drv.h" 32 #include "sun4i_hdmi.h" 33 34 #define drm_encoder_to_sun4i_hdmi(e) \ 35 container_of_const(e, struct sun4i_hdmi, encoder) 36 37 #define drm_connector_to_sun4i_hdmi(c) \ 38 container_of_const(c, struct sun4i_hdmi, connector) 39 40 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 41 struct drm_display_mode *mode) 42 { 43 struct hdmi_avi_infoframe frame; 44 u8 buffer[17]; 45 int i, ret; 46 47 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 48 &hdmi->connector, mode); 49 if (ret < 0) { 50 DRM_ERROR("Failed to get infoframes from mode\n"); 51 return ret; 52 } 53 54 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 55 if (ret < 0) { 56 DRM_ERROR("Failed to pack infoframes\n"); 57 return ret; 58 } 59 60 for (i = 0; i < sizeof(buffer); i++) 61 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 62 63 return 0; 64 } 65 66 static void sun4i_hdmi_disable(struct drm_encoder *encoder, 67 struct drm_atomic_state *state) 68 { 69 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 70 u32 val; 71 72 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 73 74 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 75 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 76 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 77 78 clk_disable_unprepare(hdmi->tmds_clk); 79 } 80 81 static void sun4i_hdmi_enable(struct drm_encoder *encoder, 82 struct drm_atomic_state *state) 83 { 84 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 85 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 86 struct drm_display_info *display = &hdmi->connector.display_info; 87 unsigned int x, y; 88 u32 val = 0; 89 90 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 91 92 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 93 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 94 95 /* Set input sync enable */ 96 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 97 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 98 99 /* 100 * Setup output pad (?) controls 101 * 102 * This is done here instead of at probe/bind time because 103 * the controller seems to toggle some of the bits on its own. 104 * 105 * We can't just initialize the register there, we need to 106 * protect the clock bits that have already been read out and 107 * cached by the clock framework. 108 */ 109 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 110 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 111 val |= hdmi->variant->pad_ctrl1_init_val; 112 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 113 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 114 115 /* Setup timing registers */ 116 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 117 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 118 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 119 120 x = mode->htotal - mode->hsync_start; 121 y = mode->vtotal - mode->vsync_start; 122 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 123 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 124 125 x = mode->hsync_start - mode->hdisplay; 126 y = mode->vsync_start - mode->vdisplay; 127 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 128 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 129 130 x = mode->hsync_end - mode->hsync_start; 131 y = mode->vsync_end - mode->vsync_start; 132 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 133 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 134 135 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 136 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 137 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 138 139 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 140 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 141 142 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 143 144 clk_prepare_enable(hdmi->tmds_clk); 145 146 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 147 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 148 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 149 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 150 151 val = SUN4I_HDMI_VID_CTRL_ENABLE; 152 if (display->is_hdmi) 153 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 154 155 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 156 } 157 158 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 159 .atomic_disable = sun4i_hdmi_disable, 160 .atomic_enable = sun4i_hdmi_enable, 161 }; 162 163 static enum drm_mode_status 164 sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector, 165 const struct drm_display_mode *mode, 166 unsigned long long clock) 167 { 168 const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 169 unsigned long diff = div_u64(clock, 200); /* +-0.5% allowed by HDMI spec */ 170 long rounded_rate; 171 172 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 173 return MODE_BAD; 174 175 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 176 if (clock > 165000000) 177 return MODE_CLOCK_HIGH; 178 179 rounded_rate = clk_round_rate(hdmi->tmds_clk, clock); 180 if (rounded_rate > 0 && 181 max_t(unsigned long, rounded_rate, clock) - 182 min_t(unsigned long, rounded_rate, clock) < diff) 183 return MODE_OK; 184 185 return MODE_NOCLOCK; 186 } 187 188 static int sun4i_hdmi_connector_atomic_check(struct drm_connector *connector, 189 struct drm_atomic_state *state) 190 { 191 struct drm_connector_state *conn_state = 192 drm_atomic_get_new_connector_state(state, connector); 193 struct drm_crtc *crtc = conn_state->crtc; 194 struct drm_crtc_state *crtc_state = crtc->state; 195 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 196 enum drm_mode_status status; 197 198 status = sun4i_hdmi_connector_clock_valid(connector, mode, 199 mode->clock * 1000); 200 if (status != MODE_OK) 201 return -EINVAL; 202 203 return 0; 204 } 205 206 static enum drm_mode_status 207 sun4i_hdmi_connector_mode_valid(struct drm_connector *connector, 208 struct drm_display_mode *mode) 209 { 210 return sun4i_hdmi_connector_clock_valid(connector, mode, 211 mode->clock * 1000); 212 } 213 214 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 215 { 216 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 217 const struct drm_edid *drm_edid; 218 int ret; 219 220 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c); 221 222 drm_edid_connector_update(connector, drm_edid); 223 cec_s_phys_addr(hdmi->cec_adap, 224 connector->display_info.source_physical_address, false); 225 226 if (!drm_edid) 227 return 0; 228 229 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 230 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 231 232 233 ret = drm_edid_connector_add_modes(connector); 234 drm_edid_free(drm_edid); 235 236 return ret; 237 } 238 239 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 240 { 241 struct device_node *phandle, *remote; 242 struct i2c_adapter *ddc; 243 244 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 245 if (!remote) 246 return ERR_PTR(-EINVAL); 247 248 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 249 of_node_put(remote); 250 if (!phandle) 251 return ERR_PTR(-ENODEV); 252 253 ddc = of_get_i2c_adapter_by_node(phandle); 254 of_node_put(phandle); 255 if (!ddc) 256 return ERR_PTR(-EPROBE_DEFER); 257 258 return ddc; 259 } 260 261 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 262 .atomic_check = sun4i_hdmi_connector_atomic_check, 263 .mode_valid = sun4i_hdmi_connector_mode_valid, 264 .get_modes = sun4i_hdmi_get_modes, 265 }; 266 267 static enum drm_connector_status 268 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 269 { 270 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 271 unsigned long reg; 272 273 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 274 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 275 cec_phys_addr_invalidate(hdmi->cec_adap); 276 return connector_status_disconnected; 277 } 278 279 return connector_status_connected; 280 } 281 282 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 283 .detect = sun4i_hdmi_connector_detect, 284 .fill_modes = drm_helper_probe_single_connector_modes, 285 .destroy = drm_connector_cleanup, 286 .reset = drm_atomic_helper_connector_reset, 287 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 288 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 289 }; 290 291 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 292 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 293 { 294 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 295 296 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 297 } 298 299 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 300 { 301 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 302 303 /* Start driving the CEC pin low */ 304 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 305 } 306 307 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 308 { 309 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 310 311 /* 312 * Stop driving the CEC pin, the pull up will take over 313 * unless another CEC device is driving the pin low. 314 */ 315 writel(0, hdmi->base + SUN4I_HDMI_CEC); 316 } 317 318 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 319 .read = sun4i_hdmi_cec_pin_read, 320 .low = sun4i_hdmi_cec_pin_low, 321 .high = sun4i_hdmi_cec_pin_high, 322 }; 323 #endif 324 325 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 326 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 327 328 /* Only difference from sun5i is AMP is 4 instead of 6 */ 329 static const struct sun4i_hdmi_variant sun4i_variant = { 330 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 331 SUN4I_HDMI_PAD_CTRL0_CKEN | 332 SUN4I_HDMI_PAD_CTRL0_PWENG | 333 SUN4I_HDMI_PAD_CTRL0_PWEND | 334 SUN4I_HDMI_PAD_CTRL0_PWENC | 335 SUN4I_HDMI_PAD_CTRL0_LDODEN | 336 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 337 SUN4I_HDMI_PAD_CTRL0_BIASEN, 338 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 339 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 340 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 341 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 342 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 343 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 344 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 345 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 346 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 347 SUN4I_HDMI_PLL_CTRL_CS(7) | 348 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 349 SUN4I_HDMI_PLL_CTRL_S(7) | 350 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 351 SUN4I_HDMI_PLL_CTRL_SDIV2 | 352 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 353 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 354 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 355 SUN4I_HDMI_PLL_CTRL_BWS | 356 SUN4I_HDMI_PLL_CTRL_PLL_EN, 357 358 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 359 .ddc_clk_pre_divider = 2, 360 .ddc_clk_m_offset = 1, 361 362 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 363 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 364 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 365 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 366 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 367 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 368 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 369 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 370 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 371 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 372 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 373 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 374 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 375 376 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 377 .ddc_fifo_has_dir = true, 378 }; 379 380 static const struct sun4i_hdmi_variant sun5i_variant = { 381 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 382 SUN4I_HDMI_PAD_CTRL0_CKEN | 383 SUN4I_HDMI_PAD_CTRL0_PWENG | 384 SUN4I_HDMI_PAD_CTRL0_PWEND | 385 SUN4I_HDMI_PAD_CTRL0_PWENC | 386 SUN4I_HDMI_PAD_CTRL0_LDODEN | 387 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 388 SUN4I_HDMI_PAD_CTRL0_BIASEN, 389 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 390 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 391 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 392 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 393 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 394 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 395 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 396 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 397 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 398 SUN4I_HDMI_PLL_CTRL_CS(7) | 399 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 400 SUN4I_HDMI_PLL_CTRL_S(7) | 401 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 402 SUN4I_HDMI_PLL_CTRL_SDIV2 | 403 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 404 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 405 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 406 SUN4I_HDMI_PLL_CTRL_BWS | 407 SUN4I_HDMI_PLL_CTRL_PLL_EN, 408 409 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 410 .ddc_clk_pre_divider = 2, 411 .ddc_clk_m_offset = 1, 412 413 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 414 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 415 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 416 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 417 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 418 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 419 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 420 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 421 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 422 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 423 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 424 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 425 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 426 427 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 428 .ddc_fifo_has_dir = true, 429 }; 430 431 static const struct sun4i_hdmi_variant sun6i_variant = { 432 .has_ddc_parent_clk = true, 433 .has_reset_control = true, 434 .pad_ctrl0_init_val = 0xff | 435 SUN4I_HDMI_PAD_CTRL0_TXEN | 436 SUN4I_HDMI_PAD_CTRL0_CKEN | 437 SUN4I_HDMI_PAD_CTRL0_PWENG | 438 SUN4I_HDMI_PAD_CTRL0_PWEND | 439 SUN4I_HDMI_PAD_CTRL0_PWENC | 440 SUN4I_HDMI_PAD_CTRL0_LDODEN | 441 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 442 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 443 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 444 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 445 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 446 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 447 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 448 SUN4I_HDMI_PAD_CTRL1_PWSDT | 449 SUN4I_HDMI_PAD_CTRL1_PWSCK | 450 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 451 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 452 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 453 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 454 SUN4I_HDMI_PLL_CTRL_CS(3) | 455 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 456 SUN4I_HDMI_PLL_CTRL_S(4) | 457 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 458 SUN4I_HDMI_PLL_CTRL_SDIV2 | 459 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 460 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 461 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 462 SUN4I_HDMI_PLL_CTRL_PLL_EN, 463 464 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 465 .ddc_clk_pre_divider = 1, 466 .ddc_clk_m_offset = 2, 467 468 .tmds_clk_div_offset = 1, 469 470 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 471 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 472 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 473 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 474 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 475 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 476 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 477 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 478 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 479 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 480 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 481 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 482 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 483 484 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 485 .ddc_fifo_thres_incl = true, 486 }; 487 488 static const struct regmap_config sun4i_hdmi_regmap_config = { 489 .reg_bits = 32, 490 .val_bits = 32, 491 .reg_stride = 4, 492 .max_register = 0x580, 493 }; 494 495 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 496 void *data) 497 { 498 struct platform_device *pdev = to_platform_device(dev); 499 struct drm_device *drm = data; 500 struct cec_connector_info conn_info; 501 struct sun4i_drv *drv = drm->dev_private; 502 struct sun4i_hdmi *hdmi; 503 u32 reg; 504 int ret; 505 506 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 507 if (!hdmi) 508 return -ENOMEM; 509 dev_set_drvdata(dev, hdmi); 510 hdmi->dev = dev; 511 hdmi->drv = drv; 512 513 hdmi->variant = of_device_get_match_data(dev); 514 if (!hdmi->variant) 515 return -EINVAL; 516 517 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 518 if (IS_ERR(hdmi->base)) { 519 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 520 return PTR_ERR(hdmi->base); 521 } 522 523 if (hdmi->variant->has_reset_control) { 524 hdmi->reset = devm_reset_control_get(dev, NULL); 525 if (IS_ERR(hdmi->reset)) { 526 dev_err(dev, "Couldn't get the HDMI reset control\n"); 527 return PTR_ERR(hdmi->reset); 528 } 529 530 ret = reset_control_deassert(hdmi->reset); 531 if (ret) { 532 dev_err(dev, "Couldn't deassert HDMI reset\n"); 533 return ret; 534 } 535 } 536 537 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 538 if (IS_ERR(hdmi->bus_clk)) { 539 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 540 ret = PTR_ERR(hdmi->bus_clk); 541 goto err_assert_reset; 542 } 543 clk_prepare_enable(hdmi->bus_clk); 544 545 hdmi->mod_clk = devm_clk_get(dev, "mod"); 546 if (IS_ERR(hdmi->mod_clk)) { 547 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 548 ret = PTR_ERR(hdmi->mod_clk); 549 goto err_disable_bus_clk; 550 } 551 clk_prepare_enable(hdmi->mod_clk); 552 553 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 554 if (IS_ERR(hdmi->pll0_clk)) { 555 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 556 ret = PTR_ERR(hdmi->pll0_clk); 557 goto err_disable_mod_clk; 558 } 559 560 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 561 if (IS_ERR(hdmi->pll1_clk)) { 562 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 563 ret = PTR_ERR(hdmi->pll1_clk); 564 goto err_disable_mod_clk; 565 } 566 567 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 568 &sun4i_hdmi_regmap_config); 569 if (IS_ERR(hdmi->regmap)) { 570 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 571 ret = PTR_ERR(hdmi->regmap); 572 goto err_disable_mod_clk; 573 } 574 575 ret = sun4i_tmds_create(hdmi); 576 if (ret) { 577 dev_err(dev, "Couldn't create the TMDS clock\n"); 578 goto err_disable_mod_clk; 579 } 580 581 if (hdmi->variant->has_ddc_parent_clk) { 582 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 583 if (IS_ERR(hdmi->ddc_parent_clk)) { 584 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 585 ret = PTR_ERR(hdmi->ddc_parent_clk); 586 goto err_disable_mod_clk; 587 } 588 } else { 589 hdmi->ddc_parent_clk = hdmi->tmds_clk; 590 } 591 592 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 593 594 writel(hdmi->variant->pad_ctrl0_init_val, 595 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 596 597 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 598 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 599 reg |= hdmi->variant->pll_ctrl_init_val; 600 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 601 602 ret = sun4i_hdmi_i2c_create(dev, hdmi); 603 if (ret) { 604 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 605 goto err_disable_mod_clk; 606 } 607 608 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 609 if (IS_ERR(hdmi->ddc_i2c)) { 610 ret = PTR_ERR(hdmi->ddc_i2c); 611 if (ret == -ENODEV) 612 hdmi->ddc_i2c = NULL; 613 else 614 goto err_del_i2c_adapter; 615 } 616 617 drm_encoder_helper_add(&hdmi->encoder, 618 &sun4i_hdmi_helper_funcs); 619 ret = drm_simple_encoder_init(drm, &hdmi->encoder, 620 DRM_MODE_ENCODER_TMDS); 621 if (ret) { 622 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 623 goto err_put_ddc_i2c; 624 } 625 626 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 627 dev->of_node); 628 if (!hdmi->encoder.possible_crtcs) { 629 ret = -EPROBE_DEFER; 630 goto err_put_ddc_i2c; 631 } 632 633 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 634 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 635 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 636 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 637 if (ret < 0) 638 goto err_cleanup_connector; 639 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 640 hdmi->base + SUN4I_HDMI_CEC); 641 #endif 642 643 drm_connector_helper_add(&hdmi->connector, 644 &sun4i_hdmi_connector_helper_funcs); 645 ret = drm_connector_init_with_ddc(drm, &hdmi->connector, 646 &sun4i_hdmi_connector_funcs, 647 DRM_MODE_CONNECTOR_HDMIA, 648 hdmi->ddc_i2c); 649 if (ret) { 650 dev_err(dev, 651 "Couldn't initialise the HDMI connector\n"); 652 goto err_cleanup_connector; 653 } 654 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 655 cec_s_conn_info(hdmi->cec_adap, &conn_info); 656 657 /* There is no HPD interrupt, so we need to poll the controller */ 658 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 659 DRM_CONNECTOR_POLL_DISCONNECT; 660 661 ret = cec_register_adapter(hdmi->cec_adap, dev); 662 if (ret < 0) 663 goto err_cleanup_connector; 664 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 665 666 return 0; 667 668 err_cleanup_connector: 669 cec_delete_adapter(hdmi->cec_adap); 670 drm_encoder_cleanup(&hdmi->encoder); 671 err_put_ddc_i2c: 672 i2c_put_adapter(hdmi->ddc_i2c); 673 err_del_i2c_adapter: 674 i2c_del_adapter(hdmi->i2c); 675 err_disable_mod_clk: 676 clk_disable_unprepare(hdmi->mod_clk); 677 err_disable_bus_clk: 678 clk_disable_unprepare(hdmi->bus_clk); 679 err_assert_reset: 680 reset_control_assert(hdmi->reset); 681 return ret; 682 } 683 684 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 685 void *data) 686 { 687 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 688 689 cec_unregister_adapter(hdmi->cec_adap); 690 i2c_del_adapter(hdmi->i2c); 691 i2c_put_adapter(hdmi->ddc_i2c); 692 clk_disable_unprepare(hdmi->mod_clk); 693 clk_disable_unprepare(hdmi->bus_clk); 694 } 695 696 static const struct component_ops sun4i_hdmi_ops = { 697 .bind = sun4i_hdmi_bind, 698 .unbind = sun4i_hdmi_unbind, 699 }; 700 701 static int sun4i_hdmi_probe(struct platform_device *pdev) 702 { 703 return component_add(&pdev->dev, &sun4i_hdmi_ops); 704 } 705 706 static void sun4i_hdmi_remove(struct platform_device *pdev) 707 { 708 component_del(&pdev->dev, &sun4i_hdmi_ops); 709 } 710 711 static const struct of_device_id sun4i_hdmi_of_table[] = { 712 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 713 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 714 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 715 { } 716 }; 717 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 718 719 static struct platform_driver sun4i_hdmi_driver = { 720 .probe = sun4i_hdmi_probe, 721 .remove_new = sun4i_hdmi_remove, 722 .driver = { 723 .name = "sun4i-hdmi", 724 .of_match_table = sun4i_hdmi_of_table, 725 }, 726 }; 727 module_platform_driver(sun4i_hdmi_driver); 728 729 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 730 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 731 MODULE_LICENSE("GPL"); 732