1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #ifndef _SUN4I_HDMI_H_ 13 #define _SUN4I_HDMI_H_ 14 15 #include <drm/drm_connector.h> 16 #include <drm/drm_encoder.h> 17 18 #define SUN4I_HDMI_CTRL_REG 0x004 19 #define SUN4I_HDMI_CTRL_ENABLE BIT(31) 20 21 #define SUN4I_HDMI_IRQ_REG 0x008 22 #define SUN4I_HDMI_IRQ_STA_MASK 0x73 23 #define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) 24 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) 25 26 #define SUN4I_HDMI_HPD_REG 0x00c 27 #define SUN4I_HDMI_HPD_HIGH BIT(0) 28 29 #define SUN4I_HDMI_VID_CTRL_REG 0x010 30 #define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) 31 #define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) 32 33 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 34 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 35 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c 36 #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 37 38 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0))) 39 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16) 40 41 #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 42 #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16) 43 #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) 44 #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) 45 46 #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n)) 47 48 #define SUN4I_HDMI_PAD_CTRL0_REG 0x200 49 #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) 50 #define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30) 51 #define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29) 52 #define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) 53 #define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) 54 #define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) 55 #define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) 56 #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) 57 58 #define SUN4I_HDMI_PAD_CTRL1_REG 0x204 59 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) 60 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) 61 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) 62 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) 63 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) 64 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) 65 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10) 66 #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) 67 #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3) 68 69 #define SUN4I_HDMI_PLL_CTRL_REG 0x208 70 #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) 71 #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) 72 #define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29) 73 #define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28) 74 #define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27) 75 #define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25) 76 #define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20) 77 #define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17) 78 #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12) 79 #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8) 80 #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4) 81 #define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4) 82 #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf) 83 84 #define SUN4I_HDMI_PLL_DBG0_REG 0x20c 85 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21) 86 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) 87 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 88 89 #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) 90 #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) 91 92 #define SUN4I_HDMI_UNKNOWN_REG 0x300 93 #define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) 94 95 #define SUN4I_HDMI_DDC_CTRL_REG 0x500 96 #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) 97 #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) 98 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) 99 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) 100 #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) 101 102 #define SUN4I_HDMI_DDC_ADDR_REG 0x504 103 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) 104 #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) 105 #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) 106 #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) 107 108 #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 109 #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) 110 111 #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 112 #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c 113 114 #define SUN4I_HDMI_DDC_CMD_REG 0x520 115 #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 116 117 #define SUN4I_HDMI_DDC_CLK_REG 0x528 118 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) 119 #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7) 120 121 #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540 122 #define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) 123 #define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) 124 125 #define SUN4I_HDMI_DDC_FIFO_SIZE 16 126 127 enum sun4i_hdmi_pkt_type { 128 SUN4I_HDMI_PKT_AVI = 2, 129 SUN4I_HDMI_PKT_END = 15, 130 }; 131 132 struct sun4i_hdmi { 133 struct drm_connector connector; 134 struct drm_encoder encoder; 135 struct device *dev; 136 137 void __iomem *base; 138 139 /* Parent clocks */ 140 struct clk *bus_clk; 141 struct clk *mod_clk; 142 struct clk *pll0_clk; 143 struct clk *pll1_clk; 144 145 /* And the clocks we create */ 146 struct clk *ddc_clk; 147 struct clk *tmds_clk; 148 149 struct sun4i_drv *drv; 150 151 bool hdmi_monitor; 152 }; 153 154 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); 155 int sun4i_tmds_create(struct sun4i_hdmi *hdmi); 156 157 #endif /* _SUN4I_HDMI_H_ */ 158