xref: /linux/drivers/gpu/drm/sun4i/sun4i_backend.h (revision bab2c80e5a6c855657482eac9e97f5f3eedb509a)
1 /*
2  * Copyright (C) 2015 Free Electrons
3  * Copyright (C) 2015 NextThing Co
4  *
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #ifndef _SUN4I_BACKEND_H_
14 #define _SUN4I_BACKEND_H_
15 
16 #include <linux/clk.h>
17 #include <linux/list.h>
18 #include <linux/of.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 
22 #include "sunxi_engine.h"
23 
24 #define SUN4I_BACKEND_MODCTL_REG		0x800
25 #define SUN4I_BACKEND_MODCTL_LINE_SEL			BIT(29)
26 #define SUN4I_BACKEND_MODCTL_ITLMOD_EN			BIT(28)
27 #define SUN4I_BACKEND_MODCTL_OUT_SEL			GENMASK(22, 20)
28 #define SUN4I_BACKEND_MODCTL_OUT_LCD0				(0 << 20)
29 #define SUN4I_BACKEND_MODCTL_OUT_LCD1				(1 << 20)
30 #define SUN4I_BACKEND_MODCTL_OUT_FE0				(6 << 20)
31 #define SUN4I_BACKEND_MODCTL_OUT_FE1				(7 << 20)
32 #define SUN4I_BACKEND_MODCTL_HWC_EN			BIT(16)
33 #define SUN4I_BACKEND_MODCTL_LAY_EN(l)			BIT(8 + l)
34 #define SUN4I_BACKEND_MODCTL_OCSC_EN			BIT(5)
35 #define SUN4I_BACKEND_MODCTL_DFLK_EN			BIT(4)
36 #define SUN4I_BACKEND_MODCTL_DLP_START_CTL		BIT(2)
37 #define SUN4I_BACKEND_MODCTL_START_CTL			BIT(1)
38 #define SUN4I_BACKEND_MODCTL_DEBE_EN			BIT(0)
39 
40 #define SUN4I_BACKEND_BACKCOLOR_REG		0x804
41 #define SUN4I_BACKEND_BACKCOLOR(r, g, b)		(((r) << 16) | ((g) << 8) | (b))
42 
43 #define SUN4I_BACKEND_DISSIZE_REG		0x808
44 #define SUN4I_BACKEND_DISSIZE(w, h)			(((((h) - 1) & 0xffff) << 16) | \
45 							 (((w) - 1) & 0xffff))
46 
47 #define SUN4I_BACKEND_LAYSIZE_REG(l)		(0x810 + (0x4 * (l)))
48 #define SUN4I_BACKEND_LAYSIZE(w, h)			(((((h) - 1) & 0x1fff) << 16) | \
49 							 (((w) - 1) & 0x1fff))
50 
51 #define SUN4I_BACKEND_LAYCOOR_REG(l)		(0x820 + (0x4 * (l)))
52 #define SUN4I_BACKEND_LAYCOOR(x, y)			((((u32)(y) & 0xffff) << 16) | \
53 							 ((u32)(x) & 0xffff))
54 
55 #define SUN4I_BACKEND_LAYLINEWIDTH_REG(l)	(0x840 + (0x4 * (l)))
56 
57 #define SUN4I_BACKEND_LAYFB_L32ADD_REG(l)	(0x850 + (0x4 * (l)))
58 
59 #define SUN4I_BACKEND_LAYFB_H4ADD_REG		0x860
60 #define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l)		GENMASK(3 + ((l) * 8), (l) * 8)
61 #define SUN4I_BACKEND_LAYFB_H4ADD(l, val)		((val) << ((l) * 8))
62 
63 #define SUN4I_BACKEND_REGBUFFCTL_REG		0x870
64 #define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS		BIT(1)
65 #define SUN4I_BACKEND_REGBUFFCTL_LOADCTL		BIT(0)
66 
67 #define SUN4I_BACKEND_CKMAX_REG			0x880
68 #define SUN4I_BACKEND_CKMIN_REG			0x884
69 #define SUN4I_BACKEND_CKCFG_REG			0x888
70 #define SUN4I_BACKEND_ATTCTL_REG0(l)		(0x890 + (0x4 * (l)))
71 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK	GENMASK(31, 24)
72 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(x)		((x) << 24)
73 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK	BIT(15)
74 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x)		((x) << 15)
75 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK	GENMASK(11, 10)
76 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)			((x) << 10)
77 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN		BIT(2)
78 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN		BIT(1)
79 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN	BIT(0)
80 
81 #define SUN4I_BACKEND_ATTCTL_REG1(l)		(0x8a0 + (0x4 * (l)))
82 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT		GENMASK(15, 14)
83 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT		GENMASK(13, 12)
84 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT		GENMASK(11, 8)
85 #define SUN4I_BACKEND_LAY_FBFMT_1BPP				(0 << 8)
86 #define SUN4I_BACKEND_LAY_FBFMT_2BPP				(1 << 8)
87 #define SUN4I_BACKEND_LAY_FBFMT_4BPP				(2 << 8)
88 #define SUN4I_BACKEND_LAY_FBFMT_8BPP				(3 << 8)
89 #define SUN4I_BACKEND_LAY_FBFMT_RGB655				(4 << 8)
90 #define SUN4I_BACKEND_LAY_FBFMT_RGB565				(5 << 8)
91 #define SUN4I_BACKEND_LAY_FBFMT_RGB556				(6 << 8)
92 #define SUN4I_BACKEND_LAY_FBFMT_ARGB1555			(7 << 8)
93 #define SUN4I_BACKEND_LAY_FBFMT_RGBA5551			(8 << 8)
94 #define SUN4I_BACKEND_LAY_FBFMT_XRGB8888			(9 << 8)
95 #define SUN4I_BACKEND_LAY_FBFMT_ARGB8888			(10 << 8)
96 #define SUN4I_BACKEND_LAY_FBFMT_RGB888				(11 << 8)
97 #define SUN4I_BACKEND_LAY_FBFMT_ARGB4444			(12 << 8)
98 #define SUN4I_BACKEND_LAY_FBFMT_RGBA4444			(13 << 8)
99 
100 #define SUN4I_BACKEND_DLCDPCTL_REG		0x8b0
101 #define SUN4I_BACKEND_DLCDPFRMBUF_ADDRCTL_REG	0x8b4
102 #define SUN4I_BACKEND_DLCDPCOOR_REG0		0x8b8
103 #define SUN4I_BACKEND_DLCDPCOOR_REG1		0x8bc
104 
105 #define SUN4I_BACKEND_INT_EN_REG		0x8c0
106 #define SUN4I_BACKEND_INT_FLAG_REG		0x8c4
107 #define SUN4I_BACKEND_REG_LOAD_FINISHED			BIT(1)
108 
109 #define SUN4I_BACKEND_HWCCTL_REG		0x8d8
110 #define SUN4I_BACKEND_HWCFBCTL_REG		0x8e0
111 #define SUN4I_BACKEND_WBCTL_REG			0x8f0
112 #define SUN4I_BACKEND_WBADD_REG			0x8f4
113 #define SUN4I_BACKEND_WBLINEWIDTH_REG		0x8f8
114 #define SUN4I_BACKEND_SPREN_REG			0x900
115 #define SUN4I_BACKEND_SPRFMTCTL_REG		0x908
116 #define SUN4I_BACKEND_SPRALPHACTL_REG		0x90c
117 
118 #define SUN4I_BACKEND_IYUVCTL_REG		0x920
119 #define SUN4I_BACKEND_IYUVCTL_FBFMT_MASK		GENMASK(14, 12)
120 #define SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV444		(4 << 12)
121 #define SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422		(3 << 12)
122 #define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV444		(2 << 12)
123 #define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV222		(1 << 12)
124 #define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV111		(0 << 12)
125 #define SUN4I_BACKEND_IYUVCTL_FBPS_MASK			GENMASK(9, 8)
126 #define SUN4I_BACKEND_IYUVCTL_FBPS_YVYU				(3 << 8)
127 #define SUN4I_BACKEND_IYUVCTL_FBPS_VYUY				(2 << 8)
128 #define SUN4I_BACKEND_IYUVCTL_FBPS_YUYV				(1 << 8)
129 #define SUN4I_BACKEND_IYUVCTL_FBPS_UYVY				(0 << 8)
130 #define SUN4I_BACKEND_IYUVCTL_FBPS_VUYA				(1 << 8)
131 #define SUN4I_BACKEND_IYUVCTL_FBPS_AYUV				(0 << 8)
132 #define SUN4I_BACKEND_IYUVCTL_EN			BIT(0)
133 
134 #define SUN4I_BACKEND_IYUVADD_REG(c)		(0x930 + (0x4 * (c)))
135 
136 #define SUN4I_BACKEND_IYUVLINEWIDTH_REG(c)	(0x940 + (0x4 * (c)))
137 
138 #define SUN4I_BACKEND_YGCOEF_REG(c)		(0x950 + (0x4 * (c)))
139 #define SUN4I_BACKEND_YGCONS_REG		0x95c
140 #define SUN4I_BACKEND_URCOEF_REG(c)		(0x960 + (0x4 * (c)))
141 #define SUN4I_BACKEND_URCONS_REG		0x96c
142 #define SUN4I_BACKEND_VBCOEF_REG(c)		(0x970 + (0x4 * (c)))
143 #define SUN4I_BACKEND_VBCONS_REG		0x97c
144 #define SUN4I_BACKEND_KSCTL_REG			0x980
145 #define SUN4I_BACKEND_KSBKCOLOR_REG		0x984
146 #define SUN4I_BACKEND_KSFSTLINEWIDTH_REG	0x988
147 #define SUN4I_BACKEND_KSVSCAFCT_REG		0x98c
148 #define SUN4I_BACKEND_KSHSCACOEF_REG(x)		(0x9a0 + (0x4 * (x)))
149 #define SUN4I_BACKEND_OCCTL_REG			0x9c0
150 #define SUN4I_BACKEND_OCCTL_ENABLE			BIT(0)
151 
152 #define SUN4I_BACKEND_OCRCOEF_REG(x)		(0x9d0 + (0x4 * (x)))
153 #define SUN4I_BACKEND_OCRCONS_REG		0x9dc
154 #define SUN4I_BACKEND_OCGCOEF_REG(x)		(0x9e0 + (0x4 * (x)))
155 #define SUN4I_BACKEND_OCGCONS_REG		0x9ec
156 #define SUN4I_BACKEND_OCBCOEF_REG(x)		(0x9f0 + (0x4 * (x)))
157 #define SUN4I_BACKEND_OCBCONS_REG		0x9fc
158 #define SUN4I_BACKEND_SPRCOORCTL_REG(s)		(0xa00 + (0x4 * (s)))
159 #define SUN4I_BACKEND_SPRATTCTL_REG(s)		(0xb00 + (0x4 * (s)))
160 #define SUN4I_BACKEND_SPRADD_REG(s)		(0xc00 + (0x4 * (s)))
161 #define SUN4I_BACKEND_SPRLINEWIDTH_REG(s)	(0xd00 + (0x4 * (s)))
162 
163 #define SUN4I_BACKEND_SPRPALTAB_OFF		0x4000
164 #define SUN4I_BACKEND_GAMMATAB_OFF		0x4400
165 #define SUN4I_BACKEND_HWCPATTERN_OFF		0x4800
166 #define SUN4I_BACKEND_HWCCOLORTAB_OFF		0x4c00
167 #define SUN4I_BACKEND_PIPE_OFF(p)		(0x5000 + (0x400 * (p)))
168 
169 #define SUN4I_BACKEND_NUM_LAYERS		4
170 #define SUN4I_BACKEND_NUM_ALPHA_LAYERS		1
171 #define SUN4I_BACKEND_NUM_FRONTEND_LAYERS	1
172 #define SUN4I_BACKEND_NUM_YUV_PLANES		1
173 
174 struct sun4i_backend {
175 	struct sunxi_engine	engine;
176 	struct sun4i_frontend	*frontend;
177 
178 	struct reset_control	*reset;
179 
180 	struct clk		*bus_clk;
181 	struct clk		*mod_clk;
182 	struct clk		*ram_clk;
183 
184 	struct clk		*sat_clk;
185 	struct reset_control	*sat_reset;
186 
187 	/* Protects against races in the frontend teardown */
188 	spinlock_t		frontend_lock;
189 	bool			frontend_teardown;
190 };
191 
192 static inline struct sun4i_backend *
193 engine_to_sun4i_backend(struct sunxi_engine *engine)
194 {
195 	return container_of(engine, struct sun4i_backend, engine);
196 }
197 
198 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
199 				int layer, bool enable);
200 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
201 				     int layer, struct drm_plane *plane);
202 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
203 				       int layer, struct drm_plane *plane);
204 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
205 				      int layer, struct drm_plane *plane);
206 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
207 					int layer, uint32_t in_fmt);
208 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend,
209 				    int layer, struct drm_plane *plane);
210 
211 #endif /* _SUN4I_BACKEND_H_ */
212