1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/of_address.h> 14 #include <linux/of_graph.h> 15 #include <linux/reset.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_fb_cma_helper.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_plane_helper.h> 25 26 #include <video/videomode.h> 27 28 #include "ltdc.h" 29 30 #define NB_CRTC 1 31 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 32 33 #define MAX_IRQ 4 34 35 #define MAX_ENDPOINTS 2 36 37 #define HWVER_10200 0x010200 38 #define HWVER_10300 0x010300 39 #define HWVER_20101 0x020101 40 41 /* 42 * The address of some registers depends on the HW version: such registers have 43 * an extra offset specified with reg_ofs. 44 */ 45 #define REG_OFS_NONE 0 46 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 47 #define REG_OFS (ldev->caps.reg_ofs) 48 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 49 50 /* Global register offsets */ 51 #define LTDC_IDR 0x0000 /* IDentification */ 52 #define LTDC_LCR 0x0004 /* Layer Count */ 53 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 54 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 55 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 56 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 57 #define LTDC_GCR 0x0018 /* Global Control */ 58 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 59 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 60 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 61 #define LTDC_GACR 0x0028 /* GAmma Correction */ 62 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 63 #define LTDC_IER 0x0034 /* Interrupt Enable */ 64 #define LTDC_ISR 0x0038 /* Interrupt Status */ 65 #define LTDC_ICR 0x003C /* Interrupt Clear */ 66 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 67 #define LTDC_CPSR 0x0044 /* Current Position Status */ 68 #define LTDC_CDSR 0x0048 /* Current Display Status */ 69 70 /* Layer register offsets */ 71 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 72 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 73 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 74 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 75 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 76 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 77 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 78 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 79 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 80 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 81 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 82 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 83 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 84 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 85 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 86 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 87 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 88 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 89 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 90 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 91 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 92 93 /* Bit definitions */ 94 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 95 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 96 97 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 98 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 99 100 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 101 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 102 103 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 104 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 105 106 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 107 #define GCR_DEN BIT(16) /* Dither ENable */ 108 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 109 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 110 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 111 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 112 113 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 114 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 115 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 116 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 117 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 118 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 119 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 120 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 121 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 122 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 123 #define GC1R_TP BIT(25) /* Timing Programmable */ 124 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 125 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 126 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 127 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 128 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 129 130 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 131 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 132 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 133 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 134 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 135 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 136 137 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 138 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 139 140 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 141 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 142 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 143 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 144 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 145 146 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 147 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 148 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 149 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 150 151 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 152 153 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 154 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 155 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 156 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 157 158 #define LXCR_LEN BIT(0) /* Layer ENable */ 159 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 160 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 161 162 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 163 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 164 165 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 166 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 167 168 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 169 170 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 171 172 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 173 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 174 175 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 176 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 177 178 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 179 180 #define CLUT_SIZE 256 181 182 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 183 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 184 #define BF1_CA 0x400 /* Constant Alpha */ 185 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 186 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 187 188 #define NB_PF 8 /* Max nb of HW pixel format */ 189 190 enum ltdc_pix_fmt { 191 PF_NONE, 192 /* RGB formats */ 193 PF_ARGB8888, /* ARGB [32 bits] */ 194 PF_RGBA8888, /* RGBA [32 bits] */ 195 PF_RGB888, /* RGB [24 bits] */ 196 PF_RGB565, /* RGB [16 bits] */ 197 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 198 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 199 /* Indexed formats */ 200 PF_L8, /* Indexed 8 bits [8 bits] */ 201 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 202 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 203 }; 204 205 /* The index gives the encoding of the pixel format for an HW version */ 206 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 207 PF_ARGB8888, /* 0x00 */ 208 PF_RGB888, /* 0x01 */ 209 PF_RGB565, /* 0x02 */ 210 PF_ARGB1555, /* 0x03 */ 211 PF_ARGB4444, /* 0x04 */ 212 PF_L8, /* 0x05 */ 213 PF_AL44, /* 0x06 */ 214 PF_AL88 /* 0x07 */ 215 }; 216 217 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 218 PF_ARGB8888, /* 0x00 */ 219 PF_RGB888, /* 0x01 */ 220 PF_RGB565, /* 0x02 */ 221 PF_RGBA8888, /* 0x03 */ 222 PF_AL44, /* 0x04 */ 223 PF_L8, /* 0x05 */ 224 PF_ARGB1555, /* 0x06 */ 225 PF_ARGB4444 /* 0x07 */ 226 }; 227 228 static inline u32 reg_read(void __iomem *base, u32 reg) 229 { 230 return readl_relaxed(base + reg); 231 } 232 233 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 234 { 235 writel_relaxed(val, base + reg); 236 } 237 238 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 239 { 240 reg_write(base, reg, reg_read(base, reg) | mask); 241 } 242 243 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 244 { 245 reg_write(base, reg, reg_read(base, reg) & ~mask); 246 } 247 248 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 249 u32 val) 250 { 251 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 252 } 253 254 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 255 { 256 return (struct ltdc_device *)crtc->dev->dev_private; 257 } 258 259 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 260 { 261 return (struct ltdc_device *)plane->dev->dev_private; 262 } 263 264 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 265 { 266 return (struct ltdc_device *)enc->dev->dev_private; 267 } 268 269 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 270 { 271 enum ltdc_pix_fmt pf; 272 273 switch (drm_fmt) { 274 case DRM_FORMAT_ARGB8888: 275 case DRM_FORMAT_XRGB8888: 276 pf = PF_ARGB8888; 277 break; 278 case DRM_FORMAT_RGBA8888: 279 case DRM_FORMAT_RGBX8888: 280 pf = PF_RGBA8888; 281 break; 282 case DRM_FORMAT_RGB888: 283 pf = PF_RGB888; 284 break; 285 case DRM_FORMAT_RGB565: 286 pf = PF_RGB565; 287 break; 288 case DRM_FORMAT_ARGB1555: 289 case DRM_FORMAT_XRGB1555: 290 pf = PF_ARGB1555; 291 break; 292 case DRM_FORMAT_ARGB4444: 293 case DRM_FORMAT_XRGB4444: 294 pf = PF_ARGB4444; 295 break; 296 case DRM_FORMAT_C8: 297 pf = PF_L8; 298 break; 299 default: 300 pf = PF_NONE; 301 break; 302 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 303 } 304 305 return pf; 306 } 307 308 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 309 { 310 switch (pf) { 311 case PF_ARGB8888: 312 return DRM_FORMAT_ARGB8888; 313 case PF_RGBA8888: 314 return DRM_FORMAT_RGBA8888; 315 case PF_RGB888: 316 return DRM_FORMAT_RGB888; 317 case PF_RGB565: 318 return DRM_FORMAT_RGB565; 319 case PF_ARGB1555: 320 return DRM_FORMAT_ARGB1555; 321 case PF_ARGB4444: 322 return DRM_FORMAT_ARGB4444; 323 case PF_L8: 324 return DRM_FORMAT_C8; 325 case PF_AL44: /* No DRM support */ 326 case PF_AL88: /* No DRM support */ 327 case PF_NONE: 328 default: 329 return 0; 330 } 331 } 332 333 static inline u32 get_pixelformat_without_alpha(u32 drm) 334 { 335 switch (drm) { 336 case DRM_FORMAT_ARGB4444: 337 return DRM_FORMAT_XRGB4444; 338 case DRM_FORMAT_RGBA4444: 339 return DRM_FORMAT_RGBX4444; 340 case DRM_FORMAT_ARGB1555: 341 return DRM_FORMAT_XRGB1555; 342 case DRM_FORMAT_RGBA5551: 343 return DRM_FORMAT_RGBX5551; 344 case DRM_FORMAT_ARGB8888: 345 return DRM_FORMAT_XRGB8888; 346 case DRM_FORMAT_RGBA8888: 347 return DRM_FORMAT_RGBX8888; 348 default: 349 return 0; 350 } 351 } 352 353 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 354 { 355 struct drm_device *ddev = arg; 356 struct ltdc_device *ldev = ddev->dev_private; 357 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 358 359 /* Line IRQ : trigger the vblank event */ 360 if (ldev->irq_status & ISR_LIF) 361 drm_crtc_handle_vblank(crtc); 362 363 /* Save FIFO Underrun & Transfer Error status */ 364 mutex_lock(&ldev->err_lock); 365 if (ldev->irq_status & ISR_FUIF) 366 ldev->error_status |= ISR_FUIF; 367 if (ldev->irq_status & ISR_TERRIF) 368 ldev->error_status |= ISR_TERRIF; 369 mutex_unlock(&ldev->err_lock); 370 371 return IRQ_HANDLED; 372 } 373 374 static irqreturn_t ltdc_irq(int irq, void *arg) 375 { 376 struct drm_device *ddev = arg; 377 struct ltdc_device *ldev = ddev->dev_private; 378 379 /* Read & Clear the interrupt status */ 380 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 381 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 382 383 return IRQ_WAKE_THREAD; 384 } 385 386 /* 387 * DRM_CRTC 388 */ 389 390 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 391 { 392 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 393 struct drm_color_lut *lut; 394 u32 val; 395 int i; 396 397 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 398 return; 399 400 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 401 402 for (i = 0; i < CLUT_SIZE; i++, lut++) { 403 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 404 (lut->blue >> 8) | (i << 24); 405 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 406 } 407 } 408 409 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 410 struct drm_crtc_state *old_state) 411 { 412 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 413 414 DRM_DEBUG_DRIVER("\n"); 415 416 /* Sets the background color value */ 417 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 418 419 /* Enable IRQ */ 420 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 421 422 /* Immediately commit the planes */ 423 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 424 425 /* Enable LTDC */ 426 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 427 428 drm_crtc_vblank_on(crtc); 429 } 430 431 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 432 struct drm_crtc_state *old_state) 433 { 434 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 435 436 DRM_DEBUG_DRIVER("\n"); 437 438 drm_crtc_vblank_off(crtc); 439 440 /* disable LTDC */ 441 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 442 443 /* disable IRQ */ 444 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 445 446 /* immediately commit disable of layers before switching off LTDC */ 447 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 448 } 449 450 #define CLK_TOLERANCE_HZ 50 451 452 static enum drm_mode_status 453 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 454 const struct drm_display_mode *mode) 455 { 456 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 457 int target = mode->clock * 1000; 458 int target_min = target - CLK_TOLERANCE_HZ; 459 int target_max = target + CLK_TOLERANCE_HZ; 460 int result; 461 462 result = clk_round_rate(ldev->pixel_clk, target); 463 464 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 465 466 /* Filter modes according to the max frequency supported by the pads */ 467 if (result > ldev->caps.pad_max_freq_hz) 468 return MODE_CLOCK_HIGH; 469 470 /* 471 * Accept all "preferred" modes: 472 * - this is important for panels because panel clock tolerances are 473 * bigger than hdmi ones and there is no reason to not accept them 474 * (the fps may vary a little but it is not a problem). 475 * - the hdmi preferred mode will be accepted too, but userland will 476 * be able to use others hdmi "valid" modes if necessary. 477 */ 478 if (mode->type & DRM_MODE_TYPE_PREFERRED) 479 return MODE_OK; 480 481 /* 482 * Filter modes according to the clock value, particularly useful for 483 * hdmi modes that require precise pixel clocks. 484 */ 485 if (result < target_min || result > target_max) 486 return MODE_CLOCK_RANGE; 487 488 return MODE_OK; 489 } 490 491 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 492 const struct drm_display_mode *mode, 493 struct drm_display_mode *adjusted_mode) 494 { 495 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 496 int rate = mode->clock * 1000; 497 498 /* 499 * TODO clk_round_rate() does not work yet. When ready, it can 500 * be used instead of clk_set_rate() then clk_get_rate(). 501 */ 502 503 clk_disable(ldev->pixel_clk); 504 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 505 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 506 return false; 507 } 508 clk_enable(ldev->pixel_clk); 509 510 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 511 512 return true; 513 } 514 515 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 516 { 517 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 518 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 519 struct videomode vm; 520 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 521 u32 total_width, total_height; 522 u32 val; 523 524 drm_display_mode_to_videomode(mode, &vm); 525 526 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 527 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 528 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 529 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 530 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 531 532 /* Convert video timings to ltdc timings */ 533 hsync = vm.hsync_len - 1; 534 vsync = vm.vsync_len - 1; 535 accum_hbp = hsync + vm.hback_porch; 536 accum_vbp = vsync + vm.vback_porch; 537 accum_act_w = accum_hbp + vm.hactive; 538 accum_act_h = accum_vbp + vm.vactive; 539 total_width = accum_act_w + vm.hfront_porch; 540 total_height = accum_act_h + vm.vfront_porch; 541 542 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 543 val = 0; 544 545 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 546 val |= GCR_HSPOL; 547 548 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 549 val |= GCR_VSPOL; 550 551 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 552 val |= GCR_DEPOL; 553 554 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 555 val |= GCR_PCPOL; 556 557 reg_update_bits(ldev->regs, LTDC_GCR, 558 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 559 560 /* Set Synchronization size */ 561 val = (hsync << 16) | vsync; 562 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 563 564 /* Set Accumulated Back porch */ 565 val = (accum_hbp << 16) | accum_vbp; 566 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 567 568 /* Set Accumulated Active Width */ 569 val = (accum_act_w << 16) | accum_act_h; 570 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 571 572 /* Set total width & height */ 573 val = (total_width << 16) | total_height; 574 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 575 576 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 577 } 578 579 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 580 struct drm_crtc_state *old_crtc_state) 581 { 582 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 583 struct drm_pending_vblank_event *event = crtc->state->event; 584 585 DRM_DEBUG_ATOMIC("\n"); 586 587 ltdc_crtc_update_clut(crtc); 588 589 /* Commit shadow registers = update planes at next vblank */ 590 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 591 592 if (event) { 593 crtc->state->event = NULL; 594 595 spin_lock_irq(&crtc->dev->event_lock); 596 if (drm_crtc_vblank_get(crtc) == 0) 597 drm_crtc_arm_vblank_event(crtc, event); 598 else 599 drm_crtc_send_vblank_event(crtc, event); 600 spin_unlock_irq(&crtc->dev->event_lock); 601 } 602 } 603 604 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 605 .mode_valid = ltdc_crtc_mode_valid, 606 .mode_fixup = ltdc_crtc_mode_fixup, 607 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 608 .atomic_flush = ltdc_crtc_atomic_flush, 609 .atomic_enable = ltdc_crtc_atomic_enable, 610 .atomic_disable = ltdc_crtc_atomic_disable, 611 }; 612 613 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 614 { 615 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 616 617 DRM_DEBUG_DRIVER("\n"); 618 reg_set(ldev->regs, LTDC_IER, IER_LIE); 619 620 return 0; 621 } 622 623 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 624 { 625 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 626 627 DRM_DEBUG_DRIVER("\n"); 628 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 629 } 630 631 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 632 bool in_vblank_irq, int *vpos, int *hpos, 633 ktime_t *stime, ktime_t *etime, 634 const struct drm_display_mode *mode) 635 { 636 struct ltdc_device *ldev = ddev->dev_private; 637 int line, vactive_start, vactive_end, vtotal; 638 639 if (stime) 640 *stime = ktime_get(); 641 642 /* The active area starts after vsync + front porch and ends 643 * at vsync + front porc + display size. 644 * The total height also include back porch. 645 * We have 3 possible cases to handle: 646 * - line < vactive_start: vpos = line - vactive_start and will be 647 * negative 648 * - vactive_start < line < vactive_end: vpos = line - vactive_start 649 * and will be positive 650 * - line > vactive_end: vpos = line - vtotal - vactive_start 651 * and will negative 652 * 653 * Computation for the two first cases are identical so we can 654 * simplify the code and only test if line > vactive_end 655 */ 656 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 657 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 658 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 659 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 660 661 if (line > vactive_end) 662 *vpos = line - vtotal - vactive_start; 663 else 664 *vpos = line - vactive_start; 665 666 *hpos = 0; 667 668 if (etime) 669 *etime = ktime_get(); 670 671 return true; 672 } 673 674 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 675 .destroy = drm_crtc_cleanup, 676 .set_config = drm_atomic_helper_set_config, 677 .page_flip = drm_atomic_helper_page_flip, 678 .reset = drm_atomic_helper_crtc_reset, 679 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 680 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 681 .enable_vblank = ltdc_crtc_enable_vblank, 682 .disable_vblank = ltdc_crtc_disable_vblank, 683 .gamma_set = drm_atomic_helper_legacy_gamma_set, 684 }; 685 686 /* 687 * DRM_PLANE 688 */ 689 690 static int ltdc_plane_atomic_check(struct drm_plane *plane, 691 struct drm_plane_state *state) 692 { 693 struct drm_framebuffer *fb = state->fb; 694 u32 src_x, src_y, src_w, src_h; 695 696 DRM_DEBUG_DRIVER("\n"); 697 698 if (!fb) 699 return 0; 700 701 /* convert src_ from 16:16 format */ 702 src_x = state->src_x >> 16; 703 src_y = state->src_y >> 16; 704 src_w = state->src_w >> 16; 705 src_h = state->src_h >> 16; 706 707 /* Reject scaling */ 708 if (src_w != state->crtc_w || src_h != state->crtc_h) { 709 DRM_ERROR("Scaling is not supported"); 710 return -EINVAL; 711 } 712 713 return 0; 714 } 715 716 static void ltdc_plane_atomic_update(struct drm_plane *plane, 717 struct drm_plane_state *oldstate) 718 { 719 struct ltdc_device *ldev = plane_to_ltdc(plane); 720 struct drm_plane_state *state = plane->state; 721 struct drm_framebuffer *fb = state->fb; 722 u32 lofs = plane->index * LAY_OFS; 723 u32 x0 = state->crtc_x; 724 u32 x1 = state->crtc_x + state->crtc_w - 1; 725 u32 y0 = state->crtc_y; 726 u32 y1 = state->crtc_y + state->crtc_h - 1; 727 u32 src_x, src_y, src_w, src_h; 728 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 729 enum ltdc_pix_fmt pf; 730 731 if (!state->crtc || !fb) { 732 DRM_DEBUG_DRIVER("fb or crtc NULL"); 733 return; 734 } 735 736 /* convert src_ from 16:16 format */ 737 src_x = state->src_x >> 16; 738 src_y = state->src_y >> 16; 739 src_w = state->src_w >> 16; 740 src_h = state->src_h >> 16; 741 742 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 743 plane->base.id, fb->base.id, 744 src_w, src_h, src_x, src_y, 745 state->crtc_w, state->crtc_h, 746 state->crtc_x, state->crtc_y); 747 748 bpcr = reg_read(ldev->regs, LTDC_BPCR); 749 ahbp = (bpcr & BPCR_AHBP) >> 16; 750 avbp = bpcr & BPCR_AVBP; 751 752 /* Configures the horizontal start and stop position */ 753 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 754 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 755 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 756 757 /* Configures the vertical start and stop position */ 758 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 759 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 760 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 761 762 /* Specifies the pixel format */ 763 pf = to_ltdc_pixelformat(fb->format->format); 764 for (val = 0; val < NB_PF; val++) 765 if (ldev->caps.pix_fmt_hw[val] == pf) 766 break; 767 768 if (val == NB_PF) { 769 DRM_ERROR("Pixel format %.4s not supported\n", 770 (char *)&fb->format->format); 771 val = 0; /* set by default ARGB 32 bits */ 772 } 773 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 774 775 /* Configures the color frame buffer pitch in bytes & line length */ 776 pitch_in_bytes = fb->pitches[0]; 777 line_length = drm_format_plane_cpp(fb->format->format, 0) * 778 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 779 val = ((pitch_in_bytes << 16) | line_length); 780 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 781 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 782 783 /* Specifies the constant alpha value */ 784 val = CONSTA_MAX; 785 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 786 787 /* Specifies the blending factors */ 788 val = BF1_PAXCA | BF2_1PAXCA; 789 if (!fb->format->has_alpha) 790 val = BF1_CA | BF2_1CA; 791 792 /* Manage hw-specific capabilities */ 793 if (ldev->caps.non_alpha_only_l1 && 794 plane->type != DRM_PLANE_TYPE_PRIMARY) 795 val = BF1_PAXCA | BF2_1PAXCA; 796 797 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 798 LXBFCR_BF2 | LXBFCR_BF1, val); 799 800 /* Configures the frame buffer line number */ 801 val = y1 - y0 + 1; 802 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 803 804 /* Sets the FB address */ 805 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 806 807 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 808 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 809 810 /* Enable layer and CLUT if needed */ 811 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 812 val |= LXCR_LEN; 813 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 814 LXCR_LEN | LXCR_CLUTEN, val); 815 816 ldev->plane_fpsi[plane->index].counter++; 817 818 mutex_lock(&ldev->err_lock); 819 if (ldev->error_status & ISR_FUIF) { 820 DRM_DEBUG_DRIVER("Fifo underrun\n"); 821 ldev->error_status &= ~ISR_FUIF; 822 } 823 if (ldev->error_status & ISR_TERRIF) { 824 DRM_DEBUG_DRIVER("Transfer error\n"); 825 ldev->error_status &= ~ISR_TERRIF; 826 } 827 mutex_unlock(&ldev->err_lock); 828 } 829 830 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 831 struct drm_plane_state *oldstate) 832 { 833 struct ltdc_device *ldev = plane_to_ltdc(plane); 834 u32 lofs = plane->index * LAY_OFS; 835 836 /* disable layer */ 837 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 838 839 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 840 oldstate->crtc->base.id, plane->base.id); 841 } 842 843 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 844 const struct drm_plane_state *state) 845 { 846 struct drm_plane *plane = state->plane; 847 struct ltdc_device *ldev = plane_to_ltdc(plane); 848 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 849 int ms_since_last; 850 ktime_t now; 851 852 now = ktime_get(); 853 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 854 855 drm_printf(p, "\tuser_updates=%dfps\n", 856 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 857 858 fpsi->last_timestamp = now; 859 fpsi->counter = 0; 860 } 861 862 static const struct drm_plane_funcs ltdc_plane_funcs = { 863 .update_plane = drm_atomic_helper_update_plane, 864 .disable_plane = drm_atomic_helper_disable_plane, 865 .destroy = drm_plane_cleanup, 866 .reset = drm_atomic_helper_plane_reset, 867 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 868 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 869 .atomic_print_state = ltdc_plane_atomic_print_state, 870 }; 871 872 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 873 .atomic_check = ltdc_plane_atomic_check, 874 .atomic_update = ltdc_plane_atomic_update, 875 .atomic_disable = ltdc_plane_atomic_disable, 876 }; 877 878 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 879 enum drm_plane_type type) 880 { 881 unsigned long possible_crtcs = CRTC_MASK; 882 struct ltdc_device *ldev = ddev->dev_private; 883 struct device *dev = ddev->dev; 884 struct drm_plane *plane; 885 unsigned int i, nb_fmt = 0; 886 u32 formats[NB_PF * 2]; 887 u32 drm_fmt, drm_fmt_no_alpha; 888 int ret; 889 890 /* Get supported pixel formats */ 891 for (i = 0; i < NB_PF; i++) { 892 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 893 if (!drm_fmt) 894 continue; 895 formats[nb_fmt++] = drm_fmt; 896 897 /* Add the no-alpha related format if any & supported */ 898 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 899 if (!drm_fmt_no_alpha) 900 continue; 901 902 /* Manage hw-specific capabilities */ 903 if (ldev->caps.non_alpha_only_l1 && 904 type != DRM_PLANE_TYPE_PRIMARY) 905 continue; 906 907 formats[nb_fmt++] = drm_fmt_no_alpha; 908 } 909 910 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 911 if (!plane) 912 return NULL; 913 914 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 915 <dc_plane_funcs, formats, nb_fmt, 916 NULL, type, NULL); 917 if (ret < 0) 918 return NULL; 919 920 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 921 922 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 923 924 return plane; 925 } 926 927 static void ltdc_plane_destroy_all(struct drm_device *ddev) 928 { 929 struct drm_plane *plane, *plane_temp; 930 931 list_for_each_entry_safe(plane, plane_temp, 932 &ddev->mode_config.plane_list, head) 933 drm_plane_cleanup(plane); 934 } 935 936 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 937 { 938 struct ltdc_device *ldev = ddev->dev_private; 939 struct drm_plane *primary, *overlay; 940 unsigned int i; 941 int ret; 942 943 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 944 if (!primary) { 945 DRM_ERROR("Can not create primary plane\n"); 946 return -EINVAL; 947 } 948 949 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 950 <dc_crtc_funcs, NULL); 951 if (ret) { 952 DRM_ERROR("Can not initialize CRTC\n"); 953 goto cleanup; 954 } 955 956 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 957 958 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 959 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 960 961 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 962 963 /* Add planes. Note : the first layer is used by primary plane */ 964 for (i = 1; i < ldev->caps.nb_layers; i++) { 965 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 966 if (!overlay) { 967 ret = -ENOMEM; 968 DRM_ERROR("Can not create overlay plane %d\n", i); 969 goto cleanup; 970 } 971 } 972 973 return 0; 974 975 cleanup: 976 ltdc_plane_destroy_all(ddev); 977 return ret; 978 } 979 980 /* 981 * DRM_ENCODER 982 */ 983 984 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 985 .destroy = drm_encoder_cleanup, 986 }; 987 988 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 989 { 990 struct drm_encoder *encoder; 991 int ret; 992 993 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 994 if (!encoder) 995 return -ENOMEM; 996 997 encoder->possible_crtcs = CRTC_MASK; 998 encoder->possible_clones = 0; /* No cloning support */ 999 1000 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1001 DRM_MODE_ENCODER_DPI, NULL); 1002 1003 ret = drm_bridge_attach(encoder, bridge, NULL); 1004 if (ret) { 1005 drm_encoder_cleanup(encoder); 1006 return -EINVAL; 1007 } 1008 1009 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1010 1011 return 0; 1012 } 1013 1014 static int ltdc_get_caps(struct drm_device *ddev) 1015 { 1016 struct ltdc_device *ldev = ddev->dev_private; 1017 u32 bus_width_log2, lcr, gc2r; 1018 1019 /* at least 1 layer must be managed */ 1020 lcr = reg_read(ldev->regs, LTDC_LCR); 1021 1022 ldev->caps.nb_layers = max_t(int, lcr, 1); 1023 1024 /* set data bus width */ 1025 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1026 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1027 ldev->caps.bus_width = 8 << bus_width_log2; 1028 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1029 1030 switch (ldev->caps.hw_version) { 1031 case HWVER_10200: 1032 case HWVER_10300: 1033 ldev->caps.reg_ofs = REG_OFS_NONE; 1034 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1035 /* 1036 * Hw older versions support non-alpha color formats derived 1037 * from native alpha color formats only on the primary layer. 1038 * For instance, RG16 native format without alpha works fine 1039 * on 2nd layer but XR24 (derived color format from AR24) 1040 * does not work on 2nd layer. 1041 */ 1042 ldev->caps.non_alpha_only_l1 = true; 1043 ldev->caps.pad_max_freq_hz = 90000000; 1044 if (ldev->caps.hw_version == HWVER_10200) 1045 ldev->caps.pad_max_freq_hz = 65000000; 1046 break; 1047 case HWVER_20101: 1048 ldev->caps.reg_ofs = REG_OFS_4; 1049 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1050 ldev->caps.non_alpha_only_l1 = false; 1051 ldev->caps.pad_max_freq_hz = 150000000; 1052 break; 1053 default: 1054 return -ENODEV; 1055 } 1056 1057 return 0; 1058 } 1059 1060 int ltdc_load(struct drm_device *ddev) 1061 { 1062 struct platform_device *pdev = to_platform_device(ddev->dev); 1063 struct ltdc_device *ldev = ddev->dev_private; 1064 struct device *dev = ddev->dev; 1065 struct device_node *np = dev->of_node; 1066 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1067 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1068 struct drm_crtc *crtc; 1069 struct reset_control *rstc; 1070 struct resource *res; 1071 int irq, ret, i, endpoint_not_ready = -ENODEV; 1072 1073 DRM_DEBUG_DRIVER("\n"); 1074 1075 /* Get endpoints if any */ 1076 for (i = 0; i < MAX_ENDPOINTS; i++) { 1077 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1078 &bridge[i]); 1079 1080 /* 1081 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1082 * else if at least one endpoint is ready, continue probing. 1083 */ 1084 if (ret == -EPROBE_DEFER) 1085 return ret; 1086 else if (!ret) 1087 endpoint_not_ready = 0; 1088 } 1089 1090 if (endpoint_not_ready) 1091 return endpoint_not_ready; 1092 1093 rstc = devm_reset_control_get_exclusive(dev, NULL); 1094 1095 mutex_init(&ldev->err_lock); 1096 1097 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1098 if (IS_ERR(ldev->pixel_clk)) { 1099 DRM_ERROR("Unable to get lcd clock\n"); 1100 return -ENODEV; 1101 } 1102 1103 if (clk_prepare_enable(ldev->pixel_clk)) { 1104 DRM_ERROR("Unable to prepare pixel clock\n"); 1105 return -ENODEV; 1106 } 1107 1108 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1109 ldev->regs = devm_ioremap_resource(dev, res); 1110 if (IS_ERR(ldev->regs)) { 1111 DRM_ERROR("Unable to get ltdc registers\n"); 1112 ret = PTR_ERR(ldev->regs); 1113 goto err; 1114 } 1115 1116 for (i = 0; i < MAX_IRQ; i++) { 1117 irq = platform_get_irq(pdev, i); 1118 if (irq < 0) 1119 continue; 1120 1121 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1122 ltdc_irq_thread, IRQF_ONESHOT, 1123 dev_name(dev), ddev); 1124 if (ret) { 1125 DRM_ERROR("Failed to register LTDC interrupt\n"); 1126 goto err; 1127 } 1128 } 1129 1130 if (!IS_ERR(rstc)) { 1131 reset_control_assert(rstc); 1132 usleep_range(10, 20); 1133 reset_control_deassert(rstc); 1134 } 1135 1136 /* Disable interrupts */ 1137 reg_clear(ldev->regs, LTDC_IER, 1138 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1139 1140 ret = ltdc_get_caps(ddev); 1141 if (ret) { 1142 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1143 ldev->caps.hw_version); 1144 goto err; 1145 } 1146 1147 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 1148 1149 /* Add endpoints panels or bridges if any */ 1150 for (i = 0; i < MAX_ENDPOINTS; i++) { 1151 if (panel[i]) { 1152 bridge[i] = drm_panel_bridge_add(panel[i], 1153 DRM_MODE_CONNECTOR_DPI); 1154 if (IS_ERR(bridge[i])) { 1155 DRM_ERROR("panel-bridge endpoint %d\n", i); 1156 ret = PTR_ERR(bridge[i]); 1157 goto err; 1158 } 1159 } 1160 1161 if (bridge[i]) { 1162 ret = ltdc_encoder_init(ddev, bridge[i]); 1163 if (ret) { 1164 DRM_ERROR("init encoder endpoint %d\n", i); 1165 goto err; 1166 } 1167 } 1168 } 1169 1170 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1171 if (!crtc) { 1172 DRM_ERROR("Failed to allocate crtc\n"); 1173 ret = -ENOMEM; 1174 goto err; 1175 } 1176 1177 ret = ltdc_crtc_init(ddev, crtc); 1178 if (ret) { 1179 DRM_ERROR("Failed to init crtc\n"); 1180 goto err; 1181 } 1182 1183 ret = drm_vblank_init(ddev, NB_CRTC); 1184 if (ret) { 1185 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1186 goto err; 1187 } 1188 1189 /* Allow usage of vblank without having to call drm_irq_install */ 1190 ddev->irq_enabled = 1; 1191 1192 return 0; 1193 1194 err: 1195 for (i = 0; i < MAX_ENDPOINTS; i++) 1196 drm_panel_bridge_remove(bridge[i]); 1197 1198 clk_disable_unprepare(ldev->pixel_clk); 1199 1200 return ret; 1201 } 1202 1203 void ltdc_unload(struct drm_device *ddev) 1204 { 1205 struct ltdc_device *ldev = ddev->dev_private; 1206 int i; 1207 1208 DRM_DEBUG_DRIVER("\n"); 1209 1210 for (i = 0; i < MAX_ENDPOINTS; i++) 1211 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1212 1213 clk_disable_unprepare(ldev->pixel_clk); 1214 } 1215 1216 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1217 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1218 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1219 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1220 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1221 MODULE_LICENSE("GPL v2"); 1222