1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_device.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_gem_cma_helper.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_simple_kms_helper.h> 35 #include <drm/drm_vblank.h> 36 37 #include <video/videomode.h> 38 39 #include "ltdc.h" 40 41 #define NB_CRTC 1 42 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 43 44 #define MAX_IRQ 4 45 46 #define HWVER_10200 0x010200 47 #define HWVER_10300 0x010300 48 #define HWVER_20101 0x020101 49 50 /* 51 * The address of some registers depends on the HW version: such registers have 52 * an extra offset specified with reg_ofs. 53 */ 54 #define REG_OFS_NONE 0 55 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 56 #define REG_OFS (ldev->caps.reg_ofs) 57 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 58 59 /* Global register offsets */ 60 #define LTDC_IDR 0x0000 /* IDentification */ 61 #define LTDC_LCR 0x0004 /* Layer Count */ 62 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 63 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 64 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 65 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 66 #define LTDC_GCR 0x0018 /* Global Control */ 67 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 68 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 69 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 70 #define LTDC_GACR 0x0028 /* GAmma Correction */ 71 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 72 #define LTDC_IER 0x0034 /* Interrupt Enable */ 73 #define LTDC_ISR 0x0038 /* Interrupt Status */ 74 #define LTDC_ICR 0x003C /* Interrupt Clear */ 75 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 76 #define LTDC_CPSR 0x0044 /* Current Position Status */ 77 #define LTDC_CDSR 0x0048 /* Current Display Status */ 78 79 /* Layer register offsets */ 80 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 81 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 82 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 83 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 84 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 85 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 86 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 87 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 88 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 89 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 90 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 91 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 92 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 93 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 94 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 95 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 96 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 97 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 98 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 99 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 100 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 101 102 /* Bit definitions */ 103 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 104 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 105 106 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 107 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 108 109 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 110 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 111 112 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 113 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 114 115 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 116 #define GCR_DEN BIT(16) /* Dither ENable */ 117 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 118 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 119 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 120 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 121 122 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 123 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 124 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 125 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 126 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 127 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 128 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 129 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 130 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 131 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 132 #define GC1R_TP BIT(25) /* Timing Programmable */ 133 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 134 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 135 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 136 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 137 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 138 139 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 140 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 141 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 142 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 143 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 144 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 145 146 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 147 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 148 149 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 150 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 151 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 152 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 153 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 154 155 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 156 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 157 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 158 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 159 160 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 161 162 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 163 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 164 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 165 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 166 167 #define LXCR_LEN BIT(0) /* Layer ENable */ 168 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 169 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 170 171 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 172 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 173 174 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 175 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 176 177 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 178 179 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 180 181 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 182 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 183 184 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 185 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 186 187 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 188 189 #define CLUT_SIZE 256 190 191 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 192 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 193 #define BF1_CA 0x400 /* Constant Alpha */ 194 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 195 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 196 197 #define NB_PF 8 /* Max nb of HW pixel format */ 198 199 enum ltdc_pix_fmt { 200 PF_NONE, 201 /* RGB formats */ 202 PF_ARGB8888, /* ARGB [32 bits] */ 203 PF_RGBA8888, /* RGBA [32 bits] */ 204 PF_RGB888, /* RGB [24 bits] */ 205 PF_RGB565, /* RGB [16 bits] */ 206 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 207 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 208 /* Indexed formats */ 209 PF_L8, /* Indexed 8 bits [8 bits] */ 210 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 211 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 212 }; 213 214 /* The index gives the encoding of the pixel format for an HW version */ 215 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 216 PF_ARGB8888, /* 0x00 */ 217 PF_RGB888, /* 0x01 */ 218 PF_RGB565, /* 0x02 */ 219 PF_ARGB1555, /* 0x03 */ 220 PF_ARGB4444, /* 0x04 */ 221 PF_L8, /* 0x05 */ 222 PF_AL44, /* 0x06 */ 223 PF_AL88 /* 0x07 */ 224 }; 225 226 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 227 PF_ARGB8888, /* 0x00 */ 228 PF_RGB888, /* 0x01 */ 229 PF_RGB565, /* 0x02 */ 230 PF_RGBA8888, /* 0x03 */ 231 PF_AL44, /* 0x04 */ 232 PF_L8, /* 0x05 */ 233 PF_ARGB1555, /* 0x06 */ 234 PF_ARGB4444 /* 0x07 */ 235 }; 236 237 static const u64 ltdc_format_modifiers[] = { 238 DRM_FORMAT_MOD_LINEAR, 239 DRM_FORMAT_MOD_INVALID 240 }; 241 242 static inline u32 reg_read(void __iomem *base, u32 reg) 243 { 244 return readl_relaxed(base + reg); 245 } 246 247 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 248 { 249 writel_relaxed(val, base + reg); 250 } 251 252 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 253 { 254 reg_write(base, reg, reg_read(base, reg) | mask); 255 } 256 257 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 258 { 259 reg_write(base, reg, reg_read(base, reg) & ~mask); 260 } 261 262 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 263 u32 val) 264 { 265 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 266 } 267 268 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 269 { 270 return (struct ltdc_device *)crtc->dev->dev_private; 271 } 272 273 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 274 { 275 return (struct ltdc_device *)plane->dev->dev_private; 276 } 277 278 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 279 { 280 return (struct ltdc_device *)enc->dev->dev_private; 281 } 282 283 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 284 { 285 enum ltdc_pix_fmt pf; 286 287 switch (drm_fmt) { 288 case DRM_FORMAT_ARGB8888: 289 case DRM_FORMAT_XRGB8888: 290 pf = PF_ARGB8888; 291 break; 292 case DRM_FORMAT_RGBA8888: 293 case DRM_FORMAT_RGBX8888: 294 pf = PF_RGBA8888; 295 break; 296 case DRM_FORMAT_RGB888: 297 pf = PF_RGB888; 298 break; 299 case DRM_FORMAT_RGB565: 300 pf = PF_RGB565; 301 break; 302 case DRM_FORMAT_ARGB1555: 303 case DRM_FORMAT_XRGB1555: 304 pf = PF_ARGB1555; 305 break; 306 case DRM_FORMAT_ARGB4444: 307 case DRM_FORMAT_XRGB4444: 308 pf = PF_ARGB4444; 309 break; 310 case DRM_FORMAT_C8: 311 pf = PF_L8; 312 break; 313 default: 314 pf = PF_NONE; 315 break; 316 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 317 } 318 319 return pf; 320 } 321 322 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 323 { 324 switch (pf) { 325 case PF_ARGB8888: 326 return DRM_FORMAT_ARGB8888; 327 case PF_RGBA8888: 328 return DRM_FORMAT_RGBA8888; 329 case PF_RGB888: 330 return DRM_FORMAT_RGB888; 331 case PF_RGB565: 332 return DRM_FORMAT_RGB565; 333 case PF_ARGB1555: 334 return DRM_FORMAT_ARGB1555; 335 case PF_ARGB4444: 336 return DRM_FORMAT_ARGB4444; 337 case PF_L8: 338 return DRM_FORMAT_C8; 339 case PF_AL44: /* No DRM support */ 340 case PF_AL88: /* No DRM support */ 341 case PF_NONE: 342 default: 343 return 0; 344 } 345 } 346 347 static inline u32 get_pixelformat_without_alpha(u32 drm) 348 { 349 switch (drm) { 350 case DRM_FORMAT_ARGB4444: 351 return DRM_FORMAT_XRGB4444; 352 case DRM_FORMAT_RGBA4444: 353 return DRM_FORMAT_RGBX4444; 354 case DRM_FORMAT_ARGB1555: 355 return DRM_FORMAT_XRGB1555; 356 case DRM_FORMAT_RGBA5551: 357 return DRM_FORMAT_RGBX5551; 358 case DRM_FORMAT_ARGB8888: 359 return DRM_FORMAT_XRGB8888; 360 case DRM_FORMAT_RGBA8888: 361 return DRM_FORMAT_RGBX8888; 362 default: 363 return 0; 364 } 365 } 366 367 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 368 { 369 struct drm_device *ddev = arg; 370 struct ltdc_device *ldev = ddev->dev_private; 371 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 372 373 /* Line IRQ : trigger the vblank event */ 374 if (ldev->irq_status & ISR_LIF) 375 drm_crtc_handle_vblank(crtc); 376 377 /* Save FIFO Underrun & Transfer Error status */ 378 mutex_lock(&ldev->err_lock); 379 if (ldev->irq_status & ISR_FUIF) 380 ldev->error_status |= ISR_FUIF; 381 if (ldev->irq_status & ISR_TERRIF) 382 ldev->error_status |= ISR_TERRIF; 383 mutex_unlock(&ldev->err_lock); 384 385 return IRQ_HANDLED; 386 } 387 388 static irqreturn_t ltdc_irq(int irq, void *arg) 389 { 390 struct drm_device *ddev = arg; 391 struct ltdc_device *ldev = ddev->dev_private; 392 393 /* Read & Clear the interrupt status */ 394 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 395 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 396 397 return IRQ_WAKE_THREAD; 398 } 399 400 /* 401 * DRM_CRTC 402 */ 403 404 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 405 { 406 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 407 struct drm_color_lut *lut; 408 u32 val; 409 int i; 410 411 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 412 return; 413 414 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 415 416 for (i = 0; i < CLUT_SIZE; i++, lut++) { 417 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 418 (lut->blue >> 8) | (i << 24); 419 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 420 } 421 } 422 423 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 424 struct drm_atomic_state *state) 425 { 426 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 427 struct drm_device *ddev = crtc->dev; 428 429 DRM_DEBUG_DRIVER("\n"); 430 431 pm_runtime_get_sync(ddev->dev); 432 433 /* Sets the background color value */ 434 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 435 436 /* Enable IRQ */ 437 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 438 439 /* Commit shadow registers = update planes at next vblank */ 440 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 441 442 drm_crtc_vblank_on(crtc); 443 } 444 445 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 446 struct drm_atomic_state *state) 447 { 448 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 449 struct drm_device *ddev = crtc->dev; 450 451 DRM_DEBUG_DRIVER("\n"); 452 453 drm_crtc_vblank_off(crtc); 454 455 /* disable IRQ */ 456 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 457 458 /* immediately commit disable of layers before switching off LTDC */ 459 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 460 461 pm_runtime_put_sync(ddev->dev); 462 } 463 464 #define CLK_TOLERANCE_HZ 50 465 466 static enum drm_mode_status 467 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 468 const struct drm_display_mode *mode) 469 { 470 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 471 int target = mode->clock * 1000; 472 int target_min = target - CLK_TOLERANCE_HZ; 473 int target_max = target + CLK_TOLERANCE_HZ; 474 int result; 475 476 result = clk_round_rate(ldev->pixel_clk, target); 477 478 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 479 480 /* Filter modes according to the max frequency supported by the pads */ 481 if (result > ldev->caps.pad_max_freq_hz) 482 return MODE_CLOCK_HIGH; 483 484 /* 485 * Accept all "preferred" modes: 486 * - this is important for panels because panel clock tolerances are 487 * bigger than hdmi ones and there is no reason to not accept them 488 * (the fps may vary a little but it is not a problem). 489 * - the hdmi preferred mode will be accepted too, but userland will 490 * be able to use others hdmi "valid" modes if necessary. 491 */ 492 if (mode->type & DRM_MODE_TYPE_PREFERRED) 493 return MODE_OK; 494 495 /* 496 * Filter modes according to the clock value, particularly useful for 497 * hdmi modes that require precise pixel clocks. 498 */ 499 if (result < target_min || result > target_max) 500 return MODE_CLOCK_RANGE; 501 502 return MODE_OK; 503 } 504 505 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 506 const struct drm_display_mode *mode, 507 struct drm_display_mode *adjusted_mode) 508 { 509 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 510 int rate = mode->clock * 1000; 511 512 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 513 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 514 return false; 515 } 516 517 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 518 519 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 520 mode->clock, adjusted_mode->clock); 521 522 return true; 523 } 524 525 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 526 { 527 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 528 struct drm_device *ddev = crtc->dev; 529 struct drm_connector_list_iter iter; 530 struct drm_connector *connector = NULL; 531 struct drm_encoder *encoder = NULL; 532 struct drm_bridge *bridge = NULL; 533 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 534 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 535 u32 total_width, total_height; 536 u32 bus_flags = 0; 537 u32 val; 538 int ret; 539 540 /* get encoder from crtc */ 541 drm_for_each_encoder(encoder, ddev) 542 if (encoder->crtc == crtc) 543 break; 544 545 if (encoder) { 546 /* get bridge from encoder */ 547 list_for_each_entry(bridge, &encoder->bridge_chain, chain_node) 548 if (bridge->encoder == encoder) 549 break; 550 551 /* Get the connector from encoder */ 552 drm_connector_list_iter_begin(ddev, &iter); 553 drm_for_each_connector_iter(connector, &iter) 554 if (connector->encoder == encoder) 555 break; 556 drm_connector_list_iter_end(&iter); 557 } 558 559 if (bridge && bridge->timings) 560 bus_flags = bridge->timings->input_bus_flags; 561 else if (connector) 562 bus_flags = connector->display_info.bus_flags; 563 564 if (!pm_runtime_active(ddev->dev)) { 565 ret = pm_runtime_get_sync(ddev->dev); 566 if (ret) { 567 DRM_ERROR("Failed to set mode, cannot get sync\n"); 568 return; 569 } 570 } 571 572 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 573 DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 574 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 575 mode->hsync_start - mode->hdisplay, 576 mode->htotal - mode->hsync_end, 577 mode->hsync_end - mode->hsync_start, 578 mode->vsync_start - mode->vdisplay, 579 mode->vtotal - mode->vsync_end, 580 mode->vsync_end - mode->vsync_start); 581 582 /* Convert video timings to ltdc timings */ 583 hsync = mode->hsync_end - mode->hsync_start - 1; 584 vsync = mode->vsync_end - mode->vsync_start - 1; 585 accum_hbp = mode->htotal - mode->hsync_start - 1; 586 accum_vbp = mode->vtotal - mode->vsync_start - 1; 587 accum_act_w = accum_hbp + mode->hdisplay; 588 accum_act_h = accum_vbp + mode->vdisplay; 589 total_width = mode->htotal - 1; 590 total_height = mode->vtotal - 1; 591 592 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 593 val = 0; 594 595 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 596 val |= GCR_HSPOL; 597 598 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 599 val |= GCR_VSPOL; 600 601 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 602 val |= GCR_DEPOL; 603 604 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 605 val |= GCR_PCPOL; 606 607 reg_update_bits(ldev->regs, LTDC_GCR, 608 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 609 610 /* Set Synchronization size */ 611 val = (hsync << 16) | vsync; 612 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 613 614 /* Set Accumulated Back porch */ 615 val = (accum_hbp << 16) | accum_vbp; 616 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 617 618 /* Set Accumulated Active Width */ 619 val = (accum_act_w << 16) | accum_act_h; 620 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 621 622 /* Set total width & height */ 623 val = (total_width << 16) | total_height; 624 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 625 626 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 627 } 628 629 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 630 struct drm_atomic_state *state) 631 { 632 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 633 struct drm_device *ddev = crtc->dev; 634 struct drm_pending_vblank_event *event = crtc->state->event; 635 636 DRM_DEBUG_ATOMIC("\n"); 637 638 ltdc_crtc_update_clut(crtc); 639 640 /* Commit shadow registers = update planes at next vblank */ 641 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 642 643 if (event) { 644 crtc->state->event = NULL; 645 646 spin_lock_irq(&ddev->event_lock); 647 if (drm_crtc_vblank_get(crtc) == 0) 648 drm_crtc_arm_vblank_event(crtc, event); 649 else 650 drm_crtc_send_vblank_event(crtc, event); 651 spin_unlock_irq(&ddev->event_lock); 652 } 653 } 654 655 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 656 bool in_vblank_irq, 657 int *vpos, int *hpos, 658 ktime_t *stime, ktime_t *etime, 659 const struct drm_display_mode *mode) 660 { 661 struct drm_device *ddev = crtc->dev; 662 struct ltdc_device *ldev = ddev->dev_private; 663 int line, vactive_start, vactive_end, vtotal; 664 665 if (stime) 666 *stime = ktime_get(); 667 668 /* The active area starts after vsync + front porch and ends 669 * at vsync + front porc + display size. 670 * The total height also include back porch. 671 * We have 3 possible cases to handle: 672 * - line < vactive_start: vpos = line - vactive_start and will be 673 * negative 674 * - vactive_start < line < vactive_end: vpos = line - vactive_start 675 * and will be positive 676 * - line > vactive_end: vpos = line - vtotal - vactive_start 677 * and will negative 678 * 679 * Computation for the two first cases are identical so we can 680 * simplify the code and only test if line > vactive_end 681 */ 682 if (pm_runtime_active(ddev->dev)) { 683 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 684 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 685 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 686 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 687 688 if (line > vactive_end) 689 *vpos = line - vtotal - vactive_start; 690 else 691 *vpos = line - vactive_start; 692 } else { 693 *vpos = 0; 694 } 695 696 *hpos = 0; 697 698 if (etime) 699 *etime = ktime_get(); 700 701 return true; 702 } 703 704 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 705 .mode_valid = ltdc_crtc_mode_valid, 706 .mode_fixup = ltdc_crtc_mode_fixup, 707 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 708 .atomic_flush = ltdc_crtc_atomic_flush, 709 .atomic_enable = ltdc_crtc_atomic_enable, 710 .atomic_disable = ltdc_crtc_atomic_disable, 711 .get_scanout_position = ltdc_crtc_get_scanout_position, 712 }; 713 714 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 715 { 716 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 717 struct drm_crtc_state *state = crtc->state; 718 719 DRM_DEBUG_DRIVER("\n"); 720 721 if (state->enable) 722 reg_set(ldev->regs, LTDC_IER, IER_LIE); 723 else 724 return -EPERM; 725 726 return 0; 727 } 728 729 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 730 { 731 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 732 733 DRM_DEBUG_DRIVER("\n"); 734 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 735 } 736 737 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 738 .destroy = drm_crtc_cleanup, 739 .set_config = drm_atomic_helper_set_config, 740 .page_flip = drm_atomic_helper_page_flip, 741 .reset = drm_atomic_helper_crtc_reset, 742 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 743 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 744 .enable_vblank = ltdc_crtc_enable_vblank, 745 .disable_vblank = ltdc_crtc_disable_vblank, 746 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 747 }; 748 749 /* 750 * DRM_PLANE 751 */ 752 753 static int ltdc_plane_atomic_check(struct drm_plane *plane, 754 struct drm_atomic_state *state) 755 { 756 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 757 plane); 758 struct drm_framebuffer *fb = new_plane_state->fb; 759 u32 src_w, src_h; 760 761 DRM_DEBUG_DRIVER("\n"); 762 763 if (!fb) 764 return 0; 765 766 /* convert src_ from 16:16 format */ 767 src_w = new_plane_state->src_w >> 16; 768 src_h = new_plane_state->src_h >> 16; 769 770 /* Reject scaling */ 771 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 772 DRM_ERROR("Scaling is not supported"); 773 return -EINVAL; 774 } 775 776 return 0; 777 } 778 779 static void ltdc_plane_atomic_update(struct drm_plane *plane, 780 struct drm_atomic_state *state) 781 { 782 struct ltdc_device *ldev = plane_to_ltdc(plane); 783 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 784 plane); 785 struct drm_framebuffer *fb = newstate->fb; 786 u32 lofs = plane->index * LAY_OFS; 787 u32 x0 = newstate->crtc_x; 788 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 789 u32 y0 = newstate->crtc_y; 790 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 791 u32 src_x, src_y, src_w, src_h; 792 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 793 enum ltdc_pix_fmt pf; 794 795 if (!newstate->crtc || !fb) { 796 DRM_DEBUG_DRIVER("fb or crtc NULL"); 797 return; 798 } 799 800 /* convert src_ from 16:16 format */ 801 src_x = newstate->src_x >> 16; 802 src_y = newstate->src_y >> 16; 803 src_w = newstate->src_w >> 16; 804 src_h = newstate->src_h >> 16; 805 806 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 807 plane->base.id, fb->base.id, 808 src_w, src_h, src_x, src_y, 809 newstate->crtc_w, newstate->crtc_h, 810 newstate->crtc_x, newstate->crtc_y); 811 812 bpcr = reg_read(ldev->regs, LTDC_BPCR); 813 ahbp = (bpcr & BPCR_AHBP) >> 16; 814 avbp = bpcr & BPCR_AVBP; 815 816 /* Configures the horizontal start and stop position */ 817 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 818 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 819 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 820 821 /* Configures the vertical start and stop position */ 822 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 823 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 824 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 825 826 /* Specifies the pixel format */ 827 pf = to_ltdc_pixelformat(fb->format->format); 828 for (val = 0; val < NB_PF; val++) 829 if (ldev->caps.pix_fmt_hw[val] == pf) 830 break; 831 832 if (val == NB_PF) { 833 DRM_ERROR("Pixel format %.4s not supported\n", 834 (char *)&fb->format->format); 835 val = 0; /* set by default ARGB 32 bits */ 836 } 837 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 838 839 /* Configures the color frame buffer pitch in bytes & line length */ 840 pitch_in_bytes = fb->pitches[0]; 841 line_length = fb->format->cpp[0] * 842 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 843 val = ((pitch_in_bytes << 16) | line_length); 844 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 845 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 846 847 /* Specifies the constant alpha value */ 848 val = CONSTA_MAX; 849 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 850 851 /* Specifies the blending factors */ 852 val = BF1_PAXCA | BF2_1PAXCA; 853 if (!fb->format->has_alpha) 854 val = BF1_CA | BF2_1CA; 855 856 /* Manage hw-specific capabilities */ 857 if (ldev->caps.non_alpha_only_l1 && 858 plane->type != DRM_PLANE_TYPE_PRIMARY) 859 val = BF1_PAXCA | BF2_1PAXCA; 860 861 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 862 LXBFCR_BF2 | LXBFCR_BF1, val); 863 864 /* Configures the frame buffer line number */ 865 val = y1 - y0 + 1; 866 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 867 868 /* Sets the FB address */ 869 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0); 870 871 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 872 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 873 874 /* Enable layer and CLUT if needed */ 875 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 876 val |= LXCR_LEN; 877 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 878 LXCR_LEN | LXCR_CLUTEN, val); 879 880 ldev->plane_fpsi[plane->index].counter++; 881 882 mutex_lock(&ldev->err_lock); 883 if (ldev->error_status & ISR_FUIF) { 884 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 885 ldev->error_status &= ~ISR_FUIF; 886 } 887 if (ldev->error_status & ISR_TERRIF) { 888 DRM_WARN("ltdc transfer error\n"); 889 ldev->error_status &= ~ISR_TERRIF; 890 } 891 mutex_unlock(&ldev->err_lock); 892 } 893 894 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 895 struct drm_atomic_state *state) 896 { 897 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 898 plane); 899 struct ltdc_device *ldev = plane_to_ltdc(plane); 900 u32 lofs = plane->index * LAY_OFS; 901 902 /* disable layer */ 903 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 904 905 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 906 oldstate->crtc->base.id, plane->base.id); 907 } 908 909 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 910 const struct drm_plane_state *state) 911 { 912 struct drm_plane *plane = state->plane; 913 struct ltdc_device *ldev = plane_to_ltdc(plane); 914 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 915 int ms_since_last; 916 ktime_t now; 917 918 now = ktime_get(); 919 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 920 921 drm_printf(p, "\tuser_updates=%dfps\n", 922 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 923 924 fpsi->last_timestamp = now; 925 fpsi->counter = 0; 926 } 927 928 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 929 u32 format, 930 u64 modifier) 931 { 932 if (modifier == DRM_FORMAT_MOD_LINEAR) 933 return true; 934 935 return false; 936 } 937 938 static const struct drm_plane_funcs ltdc_plane_funcs = { 939 .update_plane = drm_atomic_helper_update_plane, 940 .disable_plane = drm_atomic_helper_disable_plane, 941 .destroy = drm_plane_cleanup, 942 .reset = drm_atomic_helper_plane_reset, 943 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 944 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 945 .atomic_print_state = ltdc_plane_atomic_print_state, 946 .format_mod_supported = ltdc_plane_format_mod_supported, 947 }; 948 949 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 950 .atomic_check = ltdc_plane_atomic_check, 951 .atomic_update = ltdc_plane_atomic_update, 952 .atomic_disable = ltdc_plane_atomic_disable, 953 }; 954 955 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 956 enum drm_plane_type type) 957 { 958 unsigned long possible_crtcs = CRTC_MASK; 959 struct ltdc_device *ldev = ddev->dev_private; 960 struct device *dev = ddev->dev; 961 struct drm_plane *plane; 962 unsigned int i, nb_fmt = 0; 963 u32 formats[NB_PF * 2]; 964 u32 drm_fmt, drm_fmt_no_alpha; 965 const u64 *modifiers = ltdc_format_modifiers; 966 int ret; 967 968 /* Get supported pixel formats */ 969 for (i = 0; i < NB_PF; i++) { 970 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 971 if (!drm_fmt) 972 continue; 973 formats[nb_fmt++] = drm_fmt; 974 975 /* Add the no-alpha related format if any & supported */ 976 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 977 if (!drm_fmt_no_alpha) 978 continue; 979 980 /* Manage hw-specific capabilities */ 981 if (ldev->caps.non_alpha_only_l1 && 982 type != DRM_PLANE_TYPE_PRIMARY) 983 continue; 984 985 formats[nb_fmt++] = drm_fmt_no_alpha; 986 } 987 988 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 989 if (!plane) 990 return NULL; 991 992 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 993 <dc_plane_funcs, formats, nb_fmt, 994 modifiers, type, NULL); 995 if (ret < 0) 996 return NULL; 997 998 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 999 1000 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 1001 1002 return plane; 1003 } 1004 1005 static void ltdc_plane_destroy_all(struct drm_device *ddev) 1006 { 1007 struct drm_plane *plane, *plane_temp; 1008 1009 list_for_each_entry_safe(plane, plane_temp, 1010 &ddev->mode_config.plane_list, head) 1011 drm_plane_cleanup(plane); 1012 } 1013 1014 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1015 { 1016 struct ltdc_device *ldev = ddev->dev_private; 1017 struct drm_plane *primary, *overlay; 1018 unsigned int i; 1019 int ret; 1020 1021 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 1022 if (!primary) { 1023 DRM_ERROR("Can not create primary plane\n"); 1024 return -EINVAL; 1025 } 1026 1027 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1028 <dc_crtc_funcs, NULL); 1029 if (ret) { 1030 DRM_ERROR("Can not initialize CRTC\n"); 1031 goto cleanup; 1032 } 1033 1034 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1035 1036 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1037 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1038 1039 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1040 1041 /* Add planes. Note : the first layer is used by primary plane */ 1042 for (i = 1; i < ldev->caps.nb_layers; i++) { 1043 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1044 if (!overlay) { 1045 ret = -ENOMEM; 1046 DRM_ERROR("Can not create overlay plane %d\n", i); 1047 goto cleanup; 1048 } 1049 } 1050 1051 return 0; 1052 1053 cleanup: 1054 ltdc_plane_destroy_all(ddev); 1055 return ret; 1056 } 1057 1058 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1059 { 1060 struct drm_device *ddev = encoder->dev; 1061 struct ltdc_device *ldev = ddev->dev_private; 1062 1063 DRM_DEBUG_DRIVER("\n"); 1064 1065 /* Disable LTDC */ 1066 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1067 1068 /* Set to sleep state the pinctrl whatever type of encoder */ 1069 pinctrl_pm_select_sleep_state(ddev->dev); 1070 } 1071 1072 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1073 { 1074 struct drm_device *ddev = encoder->dev; 1075 struct ltdc_device *ldev = ddev->dev_private; 1076 1077 DRM_DEBUG_DRIVER("\n"); 1078 1079 /* Enable LTDC */ 1080 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1081 } 1082 1083 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1084 struct drm_display_mode *mode, 1085 struct drm_display_mode *adjusted_mode) 1086 { 1087 struct drm_device *ddev = encoder->dev; 1088 1089 DRM_DEBUG_DRIVER("\n"); 1090 1091 /* 1092 * Set to default state the pinctrl only with DPI type. 1093 * Others types like DSI, don't need pinctrl due to 1094 * internal bridge (the signals do not come out of the chipset). 1095 */ 1096 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1097 pinctrl_pm_select_default_state(ddev->dev); 1098 } 1099 1100 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1101 .disable = ltdc_encoder_disable, 1102 .enable = ltdc_encoder_enable, 1103 .mode_set = ltdc_encoder_mode_set, 1104 }; 1105 1106 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1107 { 1108 struct drm_encoder *encoder; 1109 int ret; 1110 1111 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1112 if (!encoder) 1113 return -ENOMEM; 1114 1115 encoder->possible_crtcs = CRTC_MASK; 1116 encoder->possible_clones = 0; /* No cloning support */ 1117 1118 drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI); 1119 1120 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1121 1122 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1123 if (ret) { 1124 if (ret != -EPROBE_DEFER) 1125 drm_encoder_cleanup(encoder); 1126 return ret; 1127 } 1128 1129 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1130 1131 return 0; 1132 } 1133 1134 static int ltdc_get_caps(struct drm_device *ddev) 1135 { 1136 struct ltdc_device *ldev = ddev->dev_private; 1137 u32 bus_width_log2, lcr, gc2r; 1138 1139 /* 1140 * at least 1 layer must be managed & the number of layers 1141 * must not exceed LTDC_MAX_LAYER 1142 */ 1143 lcr = reg_read(ldev->regs, LTDC_LCR); 1144 1145 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1146 1147 /* set data bus width */ 1148 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1149 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1150 ldev->caps.bus_width = 8 << bus_width_log2; 1151 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1152 1153 switch (ldev->caps.hw_version) { 1154 case HWVER_10200: 1155 case HWVER_10300: 1156 ldev->caps.reg_ofs = REG_OFS_NONE; 1157 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1158 /* 1159 * Hw older versions support non-alpha color formats derived 1160 * from native alpha color formats only on the primary layer. 1161 * For instance, RG16 native format without alpha works fine 1162 * on 2nd layer but XR24 (derived color format from AR24) 1163 * does not work on 2nd layer. 1164 */ 1165 ldev->caps.non_alpha_only_l1 = true; 1166 ldev->caps.pad_max_freq_hz = 90000000; 1167 if (ldev->caps.hw_version == HWVER_10200) 1168 ldev->caps.pad_max_freq_hz = 65000000; 1169 ldev->caps.nb_irq = 2; 1170 break; 1171 case HWVER_20101: 1172 ldev->caps.reg_ofs = REG_OFS_4; 1173 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1174 ldev->caps.non_alpha_only_l1 = false; 1175 ldev->caps.pad_max_freq_hz = 150000000; 1176 ldev->caps.nb_irq = 4; 1177 break; 1178 default: 1179 return -ENODEV; 1180 } 1181 1182 return 0; 1183 } 1184 1185 void ltdc_suspend(struct drm_device *ddev) 1186 { 1187 struct ltdc_device *ldev = ddev->dev_private; 1188 1189 DRM_DEBUG_DRIVER("\n"); 1190 clk_disable_unprepare(ldev->pixel_clk); 1191 } 1192 1193 int ltdc_resume(struct drm_device *ddev) 1194 { 1195 struct ltdc_device *ldev = ddev->dev_private; 1196 int ret; 1197 1198 DRM_DEBUG_DRIVER("\n"); 1199 1200 ret = clk_prepare_enable(ldev->pixel_clk); 1201 if (ret) { 1202 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1203 return ret; 1204 } 1205 1206 return 0; 1207 } 1208 1209 int ltdc_load(struct drm_device *ddev) 1210 { 1211 struct platform_device *pdev = to_platform_device(ddev->dev); 1212 struct ltdc_device *ldev = ddev->dev_private; 1213 struct device *dev = ddev->dev; 1214 struct device_node *np = dev->of_node; 1215 struct drm_bridge *bridge; 1216 struct drm_panel *panel; 1217 struct drm_crtc *crtc; 1218 struct reset_control *rstc; 1219 struct resource *res; 1220 int irq, i, nb_endpoints; 1221 int ret = -ENODEV; 1222 1223 DRM_DEBUG_DRIVER("\n"); 1224 1225 /* Get number of endpoints */ 1226 nb_endpoints = of_graph_get_endpoint_count(np); 1227 if (!nb_endpoints) 1228 return -ENODEV; 1229 1230 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1231 if (IS_ERR(ldev->pixel_clk)) { 1232 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1233 DRM_ERROR("Unable to get lcd clock\n"); 1234 return PTR_ERR(ldev->pixel_clk); 1235 } 1236 1237 if (clk_prepare_enable(ldev->pixel_clk)) { 1238 DRM_ERROR("Unable to prepare pixel clock\n"); 1239 return -ENODEV; 1240 } 1241 1242 /* Get endpoints if any */ 1243 for (i = 0; i < nb_endpoints; i++) { 1244 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1245 1246 /* 1247 * If at least one endpoint is -ENODEV, continue probing, 1248 * else if at least one endpoint returned an error 1249 * (ie -EPROBE_DEFER) then stop probing. 1250 */ 1251 if (ret == -ENODEV) 1252 continue; 1253 else if (ret) 1254 goto err; 1255 1256 if (panel) { 1257 bridge = drm_panel_bridge_add_typed(panel, 1258 DRM_MODE_CONNECTOR_DPI); 1259 if (IS_ERR(bridge)) { 1260 DRM_ERROR("panel-bridge endpoint %d\n", i); 1261 ret = PTR_ERR(bridge); 1262 goto err; 1263 } 1264 } 1265 1266 if (bridge) { 1267 ret = ltdc_encoder_init(ddev, bridge); 1268 if (ret) { 1269 if (ret != -EPROBE_DEFER) 1270 DRM_ERROR("init encoder endpoint %d\n", i); 1271 goto err; 1272 } 1273 } 1274 } 1275 1276 rstc = devm_reset_control_get_exclusive(dev, NULL); 1277 1278 mutex_init(&ldev->err_lock); 1279 1280 if (!IS_ERR(rstc)) { 1281 reset_control_assert(rstc); 1282 usleep_range(10, 20); 1283 reset_control_deassert(rstc); 1284 } 1285 1286 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1287 ldev->regs = devm_ioremap_resource(dev, res); 1288 if (IS_ERR(ldev->regs)) { 1289 DRM_ERROR("Unable to get ltdc registers\n"); 1290 ret = PTR_ERR(ldev->regs); 1291 goto err; 1292 } 1293 1294 /* Disable interrupts */ 1295 reg_clear(ldev->regs, LTDC_IER, 1296 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1297 1298 ret = ltdc_get_caps(ddev); 1299 if (ret) { 1300 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1301 ldev->caps.hw_version); 1302 goto err; 1303 } 1304 1305 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1306 1307 for (i = 0; i < ldev->caps.nb_irq; i++) { 1308 irq = platform_get_irq(pdev, i); 1309 if (irq < 0) { 1310 ret = irq; 1311 goto err; 1312 } 1313 1314 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1315 ltdc_irq_thread, IRQF_ONESHOT, 1316 dev_name(dev), ddev); 1317 if (ret) { 1318 DRM_ERROR("Failed to register LTDC interrupt\n"); 1319 goto err; 1320 } 1321 1322 } 1323 1324 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1325 if (!crtc) { 1326 DRM_ERROR("Failed to allocate crtc\n"); 1327 ret = -ENOMEM; 1328 goto err; 1329 } 1330 1331 ret = ltdc_crtc_init(ddev, crtc); 1332 if (ret) { 1333 DRM_ERROR("Failed to init crtc\n"); 1334 goto err; 1335 } 1336 1337 ret = drm_vblank_init(ddev, NB_CRTC); 1338 if (ret) { 1339 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1340 goto err; 1341 } 1342 1343 clk_disable_unprepare(ldev->pixel_clk); 1344 1345 pinctrl_pm_select_sleep_state(ddev->dev); 1346 1347 pm_runtime_enable(ddev->dev); 1348 1349 return 0; 1350 err: 1351 for (i = 0; i < nb_endpoints; i++) 1352 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1353 1354 clk_disable_unprepare(ldev->pixel_clk); 1355 1356 return ret; 1357 } 1358 1359 void ltdc_unload(struct drm_device *ddev) 1360 { 1361 struct device *dev = ddev->dev; 1362 int nb_endpoints, i; 1363 1364 DRM_DEBUG_DRIVER("\n"); 1365 1366 nb_endpoints = of_graph_get_endpoint_count(dev->of_node); 1367 1368 for (i = 0; i < nb_endpoints; i++) 1369 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1370 1371 pm_runtime_disable(ddev->dev); 1372 } 1373 1374 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1375 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1376 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1377 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1378 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1379 MODULE_LICENSE("GPL v2"); 1380