1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/media-bus-format.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_graph.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #include <drm/drm_atomic.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_blend.h> 28 #include <drm/drm_bridge.h> 29 #include <drm/drm_device.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_fb_dma_helper.h> 32 #include <drm/drm_fourcc.h> 33 #include <drm/drm_framebuffer.h> 34 #include <drm/drm_gem_atomic_helper.h> 35 #include <drm/drm_gem_dma_helper.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_panel.h> 38 #include <drm/drm_print.h> 39 #include <drm/drm_probe_helper.h> 40 #include <drm/drm_simple_kms_helper.h> 41 #include <drm/drm_vblank.h> 42 #include <drm/drm_managed.h> 43 44 #include <video/videomode.h> 45 46 #include "ltdc.h" 47 48 #define NB_CRTC 1 49 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 50 51 #define MAX_IRQ 4 52 53 #define HWVER_10200 0x010200 54 #define HWVER_10300 0x010300 55 #define HWVER_20101 0x020101 56 #define HWVER_40100 0x040100 57 #define HWVER_40101 0x040101 58 59 /* 60 * The address of some registers depends on the HW version: such registers have 61 * an extra offset specified with layer_ofs. 62 */ 63 #define LAY_OFS_0 0x80 64 #define LAY_OFS_1 0x100 65 #define LAY_OFS (ldev->caps.layer_ofs) 66 67 /* Global register offsets */ 68 #define LTDC_IDR 0x0000 /* IDentification */ 69 #define LTDC_LCR 0x0004 /* Layer Count */ 70 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 71 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 72 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 73 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 74 #define LTDC_GCR 0x0018 /* Global Control */ 75 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 76 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 77 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 78 #define LTDC_GACR 0x0028 /* GAmma Correction */ 79 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 80 #define LTDC_IER 0x0034 /* Interrupt Enable */ 81 #define LTDC_ISR 0x0038 /* Interrupt Status */ 82 #define LTDC_ICR 0x003C /* Interrupt Clear */ 83 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 84 #define LTDC_CPSR 0x0044 /* Current Position Status */ 85 #define LTDC_CDSR 0x0048 /* Current Display Status */ 86 #define LTDC_EDCR 0x0060 /* External Display Control */ 87 #define LTDC_CCRCR 0x007C /* Computed CRC value */ 88 #define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ 89 90 /* Layer register offsets */ 91 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ 92 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ 93 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ 94 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ 95 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ 96 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ 97 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ 98 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ 99 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ 100 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ 101 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ 102 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ 103 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ 104 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ 105 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ 106 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ 107 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ 108 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ 109 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ 110 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ 111 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ 112 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ 113 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ 114 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ 115 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ 116 117 /* Bit definitions */ 118 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 119 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 120 121 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 122 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 123 124 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 125 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 126 127 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 128 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 129 130 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 131 #define GCR_DEN BIT(16) /* Dither ENable */ 132 #define GCR_CRCEN BIT(19) /* CRC ENable */ 133 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 134 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 135 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 136 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 137 138 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 139 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 140 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 141 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 142 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 143 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 144 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 145 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 146 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 147 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 148 #define GC1R_TP BIT(25) /* Timing Programmable */ 149 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 150 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 151 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 152 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 153 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 154 155 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 156 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 157 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 158 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 159 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 160 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 161 162 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 163 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 164 165 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 166 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 167 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 168 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 169 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 170 171 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 172 #define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */ 173 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 174 #define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */ 175 #define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */ 176 #define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */ 177 #define IER_MASK (IER_LIE | IER_FUWIE | IER_TERRIE | IER_RRIE | IER_FUEIE | IER_CRCIE) 178 179 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 180 181 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 182 #define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */ 183 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 184 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 185 #define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */ 186 #define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */ 187 188 #define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ 189 #define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ 190 #define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */ 191 192 #define LXCR_LEN BIT(0) /* Layer ENable */ 193 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 194 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 195 #define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */ 196 #define LXCR_MASK (LXCR_LEN | LXCR_COLKEN | LXCR_CLUTEN | LXCR_HMEN) 197 198 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 199 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 200 201 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 202 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 203 204 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 205 #define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */ 206 207 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 208 209 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 210 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 211 #define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ 212 213 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 214 #define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */ 215 216 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 217 218 #define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */ 219 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */ 220 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */ 221 #define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/ 222 223 #define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */ 224 #define LxPCR_OF BIT(8) /* Odd pixel First */ 225 #define LxPCR_CBF BIT(7) /* CB component First */ 226 #define LxPCR_YF BIT(6) /* Y component First */ 227 #define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */ 228 #define YCM_I 0x0 /* Interleaved 422 */ 229 #define YCM_SP 0x1 /* Semi-Planar 420 */ 230 #define YCM_FP 0x2 /* Full-Planar 420 */ 231 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */ 232 233 #define LXRCR_IMR BIT(0) /* IMmediate Reload */ 234 #define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */ 235 #define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */ 236 237 #define CLUT_SIZE 256 238 239 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 240 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 241 #define BF1_CA 0x400 /* Constant Alpha */ 242 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 243 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 244 245 #define NB_PF 8 /* Max nb of HW pixel format */ 246 247 #define FUT_DFT 128 /* Default value of fifo underrun threshold */ 248 249 /* 250 * Skip the first value and the second in case CRC was enabled during 251 * the thread irq. This is to be sure CRC value is relevant for the 252 * frame. 253 */ 254 #define CRC_SKIP_FRAMES 2 255 256 enum ltdc_pix_fmt { 257 PF_NONE, 258 /* RGB formats */ 259 PF_ARGB8888, /* ARGB [32 bits] */ 260 PF_RGBA8888, /* RGBA [32 bits] */ 261 PF_ABGR8888, /* ABGR [32 bits] */ 262 PF_BGRA8888, /* BGRA [32 bits] */ 263 PF_RGB888, /* RGB [24 bits] */ 264 PF_BGR888, /* BGR [24 bits] */ 265 PF_RGB565, /* RGB [16 bits] */ 266 PF_BGR565, /* BGR [16 bits] */ 267 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 268 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 269 /* Indexed formats */ 270 PF_L8, /* Indexed 8 bits [8 bits] */ 271 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 272 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 273 }; 274 275 /* The index gives the encoding of the pixel format for an HW version */ 276 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 277 PF_ARGB8888, /* 0x00 */ 278 PF_RGB888, /* 0x01 */ 279 PF_RGB565, /* 0x02 */ 280 PF_ARGB1555, /* 0x03 */ 281 PF_ARGB4444, /* 0x04 */ 282 PF_L8, /* 0x05 */ 283 PF_AL44, /* 0x06 */ 284 PF_AL88 /* 0x07 */ 285 }; 286 287 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 288 PF_ARGB8888, /* 0x00 */ 289 PF_RGB888, /* 0x01 */ 290 PF_RGB565, /* 0x02 */ 291 PF_RGBA8888, /* 0x03 */ 292 PF_AL44, /* 0x04 */ 293 PF_L8, /* 0x05 */ 294 PF_ARGB1555, /* 0x06 */ 295 PF_ARGB4444 /* 0x07 */ 296 }; 297 298 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { 299 PF_ARGB8888, /* 0x00 */ 300 PF_ABGR8888, /* 0x01 */ 301 PF_RGBA8888, /* 0x02 */ 302 PF_BGRA8888, /* 0x03 */ 303 PF_RGB565, /* 0x04 */ 304 PF_BGR565, /* 0x05 */ 305 PF_RGB888, /* 0x06 */ 306 PF_NONE /* 0x07 */ 307 }; 308 309 static const u32 ltdc_drm_fmt_a0[] = { 310 DRM_FORMAT_ARGB8888, 311 DRM_FORMAT_XRGB8888, 312 DRM_FORMAT_RGB888, 313 DRM_FORMAT_RGB565, 314 DRM_FORMAT_ARGB1555, 315 DRM_FORMAT_XRGB1555, 316 DRM_FORMAT_ARGB4444, 317 DRM_FORMAT_XRGB4444, 318 DRM_FORMAT_C8 319 }; 320 321 static const u32 ltdc_drm_fmt_a1[] = { 322 DRM_FORMAT_ARGB8888, 323 DRM_FORMAT_XRGB8888, 324 DRM_FORMAT_RGB888, 325 DRM_FORMAT_RGB565, 326 DRM_FORMAT_RGBA8888, 327 DRM_FORMAT_RGBX8888, 328 DRM_FORMAT_ARGB1555, 329 DRM_FORMAT_XRGB1555, 330 DRM_FORMAT_ARGB4444, 331 DRM_FORMAT_XRGB4444, 332 DRM_FORMAT_C8 333 }; 334 335 static const u32 ltdc_drm_fmt_a2[] = { 336 DRM_FORMAT_ARGB8888, 337 DRM_FORMAT_XRGB8888, 338 DRM_FORMAT_ABGR8888, 339 DRM_FORMAT_XBGR8888, 340 DRM_FORMAT_RGBA8888, 341 DRM_FORMAT_RGBX8888, 342 DRM_FORMAT_BGRA8888, 343 DRM_FORMAT_BGRX8888, 344 DRM_FORMAT_RGB565, 345 DRM_FORMAT_BGR565, 346 DRM_FORMAT_RGB888, 347 DRM_FORMAT_BGR888, 348 DRM_FORMAT_ARGB1555, 349 DRM_FORMAT_XRGB1555, 350 DRM_FORMAT_ARGB4444, 351 DRM_FORMAT_XRGB4444, 352 DRM_FORMAT_C8 353 }; 354 355 static const u32 ltdc_drm_fmt_ycbcr_cp[] = { 356 DRM_FORMAT_YUYV, 357 DRM_FORMAT_YVYU, 358 DRM_FORMAT_UYVY, 359 DRM_FORMAT_VYUY 360 }; 361 362 static const u32 ltdc_drm_fmt_ycbcr_sp[] = { 363 DRM_FORMAT_NV12, 364 DRM_FORMAT_NV21 365 }; 366 367 static const u32 ltdc_drm_fmt_ycbcr_fp[] = { 368 DRM_FORMAT_YUV420, 369 DRM_FORMAT_YVU420 370 }; 371 372 /* Layer register offsets */ 373 static const u32 ltdc_layer_regs_a0[] = { 374 0x80, /* L1 configuration 0 */ 375 0x00, /* not available */ 376 0x00, /* not available */ 377 0x84, /* L1 control register */ 378 0x88, /* L1 window horizontal position configuration */ 379 0x8c, /* L1 window vertical position configuration */ 380 0x90, /* L1 color keying configuration */ 381 0x94, /* L1 pixel format configuration */ 382 0x98, /* L1 constant alpha configuration */ 383 0x9c, /* L1 default color configuration */ 384 0xa0, /* L1 blending factors configuration */ 385 0x00, /* not available */ 386 0x00, /* not available */ 387 0xac, /* L1 color frame buffer address */ 388 0xb0, /* L1 color frame buffer length */ 389 0xb4, /* L1 color frame buffer line number */ 390 0x00, /* not available */ 391 0x00, /* not available */ 392 0x00, /* not available */ 393 0x00, /* not available */ 394 0xc4, /* L1 CLUT write */ 395 0x00, /* not available */ 396 0x00, /* not available */ 397 0x00, /* not available */ 398 0x00 /* not available */ 399 }; 400 401 static const u32 ltdc_layer_regs_a1[] = { 402 0x80, /* L1 configuration 0 */ 403 0x84, /* L1 configuration 1 */ 404 0x00, /* L1 reload control */ 405 0x88, /* L1 control register */ 406 0x8c, /* L1 window horizontal position configuration */ 407 0x90, /* L1 window vertical position configuration */ 408 0x94, /* L1 color keying configuration */ 409 0x98, /* L1 pixel format configuration */ 410 0x9c, /* L1 constant alpha configuration */ 411 0xa0, /* L1 default color configuration */ 412 0xa4, /* L1 blending factors configuration */ 413 0xa8, /* L1 burst length configuration */ 414 0x00, /* not available */ 415 0xac, /* L1 color frame buffer address */ 416 0xb0, /* L1 color frame buffer length */ 417 0xb4, /* L1 color frame buffer line number */ 418 0xb8, /* L1 auxiliary frame buffer address 0 */ 419 0xbc, /* L1 auxiliary frame buffer address 1 */ 420 0xc0, /* L1 auxiliary frame buffer length */ 421 0xc4, /* L1 auxiliary frame buffer line number */ 422 0xc8, /* L1 CLUT write */ 423 0x00, /* not available */ 424 0x00, /* not available */ 425 0x00, /* not available */ 426 0x00 /* not available */ 427 }; 428 429 static const u32 ltdc_layer_regs_a2[] = { 430 0x100, /* L1 configuration 0 */ 431 0x104, /* L1 configuration 1 */ 432 0x108, /* L1 reload control */ 433 0x10c, /* L1 control register */ 434 0x110, /* L1 window horizontal position configuration */ 435 0x114, /* L1 window vertical position configuration */ 436 0x118, /* L1 color keying configuration */ 437 0x11c, /* L1 pixel format configuration */ 438 0x120, /* L1 constant alpha configuration */ 439 0x124, /* L1 default color configuration */ 440 0x128, /* L1 blending factors configuration */ 441 0x12c, /* L1 burst length configuration */ 442 0x130, /* L1 planar configuration */ 443 0x134, /* L1 color frame buffer address */ 444 0x138, /* L1 color frame buffer length */ 445 0x13c, /* L1 color frame buffer line number */ 446 0x140, /* L1 auxiliary frame buffer address 0 */ 447 0x144, /* L1 auxiliary frame buffer address 1 */ 448 0x148, /* L1 auxiliary frame buffer length */ 449 0x14c, /* L1 auxiliary frame buffer line number */ 450 0x150, /* L1 CLUT write */ 451 0x16c, /* L1 Conversion YCbCr RGB 0 */ 452 0x170, /* L1 Conversion YCbCr RGB 1 */ 453 0x174, /* L1 Flexible Pixel Format 0 */ 454 0x178 /* L1 Flexible Pixel Format 1 */ 455 }; 456 457 static const u64 ltdc_format_modifiers[] = { 458 DRM_FORMAT_MOD_LINEAR, 459 DRM_FORMAT_MOD_INVALID 460 }; 461 462 static const struct regmap_config stm32_ltdc_regmap_cfg = { 463 .reg_bits = 32, 464 .val_bits = 32, 465 .reg_stride = sizeof(u32), 466 .max_register = 0x400, 467 .use_relaxed_mmio = true, 468 .cache_type = REGCACHE_NONE, 469 }; 470 471 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = { 472 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 473 0x02040199, /* (b_cb = 516 / r_cr = 409) */ 474 0x006400D0 /* (g_cb = 100 / g_cr = 208) */ 475 }, 476 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 477 0x01C60167, /* (b_cb = 454 / r_cr = 359) */ 478 0x005800B7 /* (g_cb = 88 / g_cr = 183) */ 479 }, 480 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 481 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */ 482 0x00370089 /* (g_cb = 55 / g_cr = 137) */ 483 }, 484 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 485 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */ 486 0x00300078 /* (g_cb = 48 / g_cr = 120) */ 487 } 488 /* BT2020 not supported */ 489 }; 490 491 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 492 { 493 return (struct ltdc_device *)crtc->dev->dev_private; 494 } 495 496 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 497 { 498 return (struct ltdc_device *)plane->dev->dev_private; 499 } 500 501 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 502 { 503 enum ltdc_pix_fmt pf; 504 505 switch (drm_fmt) { 506 case DRM_FORMAT_ARGB8888: 507 case DRM_FORMAT_XRGB8888: 508 pf = PF_ARGB8888; 509 break; 510 case DRM_FORMAT_ABGR8888: 511 case DRM_FORMAT_XBGR8888: 512 pf = PF_ABGR8888; 513 break; 514 case DRM_FORMAT_RGBA8888: 515 case DRM_FORMAT_RGBX8888: 516 pf = PF_RGBA8888; 517 break; 518 case DRM_FORMAT_BGRA8888: 519 case DRM_FORMAT_BGRX8888: 520 pf = PF_BGRA8888; 521 break; 522 case DRM_FORMAT_RGB888: 523 pf = PF_RGB888; 524 break; 525 case DRM_FORMAT_BGR888: 526 pf = PF_BGR888; 527 break; 528 case DRM_FORMAT_RGB565: 529 pf = PF_RGB565; 530 break; 531 case DRM_FORMAT_BGR565: 532 pf = PF_BGR565; 533 break; 534 case DRM_FORMAT_ARGB1555: 535 case DRM_FORMAT_XRGB1555: 536 pf = PF_ARGB1555; 537 break; 538 case DRM_FORMAT_ARGB4444: 539 case DRM_FORMAT_XRGB4444: 540 pf = PF_ARGB4444; 541 break; 542 case DRM_FORMAT_C8: 543 pf = PF_L8; 544 break; 545 default: 546 pf = PF_NONE; 547 break; 548 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 549 } 550 551 return pf; 552 } 553 554 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) 555 { 556 struct ltdc_device *ldev = plane_to_ltdc(plane); 557 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; 558 int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos; 559 560 switch (pix_fmt) { 561 case PF_BGR888: 562 psize = 3; 563 alen = 0; apos = 0; rlen = 8; rpos = 0; 564 glen = 8; gpos = 8; blen = 8; bpos = 16; 565 break; 566 case PF_ARGB1555: 567 psize = 2; 568 alen = 1; apos = 15; rlen = 5; rpos = 10; 569 glen = 5; gpos = 5; blen = 5; bpos = 0; 570 break; 571 case PF_ARGB4444: 572 psize = 2; 573 alen = 4; apos = 12; rlen = 4; rpos = 8; 574 glen = 4; gpos = 4; blen = 4; bpos = 0; 575 break; 576 case PF_L8: 577 psize = 1; 578 alen = 0; apos = 0; rlen = 8; rpos = 0; 579 glen = 8; gpos = 0; blen = 8; bpos = 0; 580 break; 581 case PF_AL44: 582 psize = 1; 583 alen = 4; apos = 4; rlen = 4; rpos = 0; 584 glen = 4; gpos = 0; blen = 4; bpos = 0; 585 break; 586 case PF_AL88: 587 psize = 2; 588 alen = 8; apos = 8; rlen = 8; rpos = 0; 589 glen = 8; gpos = 0; blen = 8; bpos = 0; 590 break; 591 default: 592 ret = NB_PF; /* error case, trace msg is handled by the caller */ 593 break; 594 } 595 596 if (ret == PF_FLEXIBLE) { 597 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, 598 (rlen << 14) + (rpos << 9) + (alen << 5) + apos); 599 600 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, 601 (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos); 602 } 603 604 return ret; 605 } 606 607 /* 608 * All non-alpha color formats derived from native alpha color formats are 609 * either characterized by a FourCC format code 610 */ 611 static inline u32 is_xrgb(u32 drm) 612 { 613 return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X'); 614 } 615 616 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) 617 { 618 struct ltdc_device *ldev = plane_to_ltdc(plane); 619 struct drm_plane_state *state = plane->state; 620 u32 lofs = plane->index * LAY_OFS; 621 u32 val; 622 623 switch (drm_pix_fmt) { 624 case DRM_FORMAT_YUYV: 625 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF; 626 break; 627 case DRM_FORMAT_YVYU: 628 val = (YCM_I << 4) | LxPCR_YF; 629 break; 630 case DRM_FORMAT_UYVY: 631 val = (YCM_I << 4) | LxPCR_CBF; 632 break; 633 case DRM_FORMAT_VYUY: 634 val = (YCM_I << 4); 635 break; 636 case DRM_FORMAT_NV12: 637 val = (YCM_SP << 4) | LxPCR_CBF; 638 break; 639 case DRM_FORMAT_NV21: 640 val = (YCM_SP << 4); 641 break; 642 case DRM_FORMAT_YUV420: 643 case DRM_FORMAT_YVU420: 644 val = (YCM_FP << 4); 645 break; 646 default: 647 /* RGB or not a YCbCr supported format */ 648 drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt); 649 return; 650 } 651 652 /* Enable limited range */ 653 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) 654 val |= LxPCR_YREN; 655 656 /* enable ycbcr conversion */ 657 val |= LxPCR_YCEN; 658 659 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); 660 } 661 662 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) 663 { 664 struct ltdc_device *ldev = plane_to_ltdc(plane); 665 struct drm_plane_state *state = plane->state; 666 enum drm_color_encoding enc = state->color_encoding; 667 enum drm_color_range ran = state->color_range; 668 u32 lofs = plane->index * LAY_OFS; 669 670 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 671 drm_err(plane->dev, "color encoding %d not supported, use bt601 by default\n", enc); 672 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 673 enc = DRM_COLOR_YCBCR_BT601; 674 } 675 676 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 677 drm_err(plane->dev, 678 "color range %d not supported, use limited range by default\n", ran); 679 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 680 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 681 } 682 683 drm_err(plane->dev, "Color encoding=%d, range=%d\n", enc, ran); 684 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 685 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 686 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, 687 ltdc_ycbcr2rgb_coeffs[enc][ran][1]); 688 } 689 690 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev, 691 struct drm_crtc *crtc) 692 { 693 u32 crc; 694 int ret; 695 696 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { 697 ldev->crc_skip_count++; 698 return; 699 } 700 701 /* Get the CRC of the frame */ 702 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); 703 if (ret) 704 return; 705 706 /* Report to DRM the CRC (hw dependent feature) */ 707 drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc); 708 } 709 710 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 711 { 712 struct drm_device *ddev = arg; 713 struct ltdc_device *ldev = ddev->dev_private; 714 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 715 716 /* Line IRQ : trigger the vblank event */ 717 if (ldev->irq_status & ISR_LIF) { 718 drm_crtc_handle_vblank(crtc); 719 720 /* Early return if CRC is not active */ 721 if (ldev->crc_active) 722 ltdc_irq_crc_handle(ldev, crtc); 723 } 724 725 mutex_lock(&ldev->err_lock); 726 if (ldev->irq_status & ISR_TERRIF) 727 ldev->transfer_err++; 728 if (ldev->irq_status & ISR_FUEIF) 729 ldev->fifo_err++; 730 if (ldev->irq_status & ISR_FUWIF) 731 ldev->fifo_warn++; 732 mutex_unlock(&ldev->err_lock); 733 734 return IRQ_HANDLED; 735 } 736 737 static irqreturn_t ltdc_irq(int irq, void *arg) 738 { 739 struct drm_device *ddev = arg; 740 struct ltdc_device *ldev = ddev->dev_private; 741 742 /* 743 * Read & Clear the interrupt status 744 * In order to write / read registers in this critical section 745 * very quickly, the regmap functions are not used. 746 */ 747 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); 748 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); 749 750 return IRQ_WAKE_THREAD; 751 } 752 753 /* 754 * DRM_CRTC 755 */ 756 757 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 758 { 759 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 760 struct drm_color_lut *lut; 761 u32 val; 762 int i; 763 764 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 765 return; 766 767 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 768 769 for (i = 0; i < CLUT_SIZE; i++, lut++) { 770 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 771 (lut->blue >> 8) | (i << 24); 772 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); 773 } 774 } 775 776 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 777 struct drm_atomic_commit *state) 778 { 779 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 780 struct drm_device *ddev = crtc->dev; 781 782 drm_dbg_driver(crtc->dev, "\n"); 783 784 pm_runtime_get_sync(ddev->dev); 785 786 /* Sets the background color value */ 787 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); 788 789 /* Enable IRQ */ 790 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 791 792 /* Commit shadow registers = update planes at next vblank */ 793 if (!ldev->caps.plane_reg_shadow) 794 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 795 796 drm_crtc_vblank_on(crtc); 797 } 798 799 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 800 struct drm_atomic_commit *state) 801 { 802 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 803 struct drm_device *ddev = crtc->dev; 804 int layer_index = 0; 805 806 drm_dbg_driver(crtc->dev, "\n"); 807 808 drm_crtc_vblank_off(crtc); 809 810 /* Disable all layers */ 811 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) 812 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, LXCR_MASK, 0); 813 814 /* Disable IRQ */ 815 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 816 817 /* immediately commit disable of layers before switching off LTDC */ 818 if (!ldev->caps.plane_reg_shadow) 819 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); 820 821 pm_runtime_put_sync(ddev->dev); 822 823 /* clear interrupt error counters */ 824 mutex_lock(&ldev->err_lock); 825 ldev->transfer_err = 0; 826 ldev->fifo_err = 0; 827 ldev->fifo_warn = 0; 828 mutex_unlock(&ldev->err_lock); 829 } 830 831 #define CLK_TOLERANCE_HZ 50 832 833 static enum drm_mode_status 834 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 835 const struct drm_display_mode *mode) 836 { 837 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 838 int target = mode->clock * 1000; 839 int target_min = target - CLK_TOLERANCE_HZ; 840 int target_max = target + CLK_TOLERANCE_HZ; 841 int result; 842 843 if (ldev->lvds_clk) { 844 result = clk_round_rate(ldev->lvds_clk, target); 845 drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", 846 target, result); 847 } 848 849 result = clk_round_rate(ldev->pixel_clk, target); 850 851 drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, result); 852 853 /* Filter modes according to the max frequency supported by the pads */ 854 if (result > ldev->caps.pad_max_freq_hz) 855 return MODE_CLOCK_HIGH; 856 857 /* 858 * Accept all "preferred" modes: 859 * - this is important for panels because panel clock tolerances are 860 * bigger than hdmi ones and there is no reason to not accept them 861 * (the fps may vary a little but it is not a problem). 862 * - the hdmi preferred mode will be accepted too, but userland will 863 * be able to use others hdmi "valid" modes if necessary. 864 */ 865 if (mode->type & DRM_MODE_TYPE_PREFERRED) 866 return MODE_OK; 867 868 /* 869 * Filter modes according to the clock value, particularly useful for 870 * hdmi modes that require precise pixel clocks. 871 */ 872 if (result < target_min || result > target_max) 873 return MODE_CLOCK_RANGE; 874 875 return MODE_OK; 876 } 877 878 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 879 const struct drm_display_mode *mode, 880 struct drm_display_mode *adjusted_mode) 881 { 882 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 883 int rate = mode->clock * 1000; 884 885 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 886 drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate); 887 return false; 888 } 889 890 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 891 892 drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n", 893 mode->clock, adjusted_mode->clock); 894 895 return true; 896 } 897 898 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 899 { 900 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 901 struct drm_device *ddev = crtc->dev; 902 struct drm_connector_list_iter iter; 903 struct drm_connector *connector = NULL; 904 struct drm_encoder *encoder = NULL, *en_iter; 905 struct drm_bridge *bridge = NULL, *br_iter; 906 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 907 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 908 u32 total_width, total_height; 909 u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24; 910 u32 bus_flags = 0; 911 u32 val; 912 int ret; 913 914 /* get encoder from crtc */ 915 drm_for_each_encoder(en_iter, ddev) 916 if (en_iter->crtc == crtc) { 917 encoder = en_iter; 918 break; 919 } 920 921 if (encoder) { 922 /* get bridge from encoder */ 923 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) 924 if (br_iter->encoder == encoder) { 925 bridge = br_iter; 926 break; 927 } 928 929 /* Get the connector from encoder */ 930 drm_connector_list_iter_begin(ddev, &iter); 931 drm_for_each_connector_iter(connector, &iter) 932 if (connector->encoder == encoder) 933 break; 934 drm_connector_list_iter_end(&iter); 935 } 936 937 if (bridge && bridge->timings) { 938 bus_flags = bridge->timings->input_bus_flags; 939 } else if (connector) { 940 bus_flags = connector->display_info.bus_flags; 941 if (connector->display_info.num_bus_formats) 942 bus_formats = connector->display_info.bus_formats[0]; 943 } 944 945 if (!pm_runtime_active(ddev->dev)) { 946 ret = pm_runtime_get_sync(ddev->dev); 947 if (ret) { 948 drm_err(crtc->dev, "Failed to set mode, cannot get sync\n"); 949 return; 950 } 951 } 952 953 drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name); 954 drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 955 drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 956 mode->hsync_start - mode->hdisplay, 957 mode->htotal - mode->hsync_end, 958 mode->hsync_end - mode->hsync_start, 959 mode->vsync_start - mode->vdisplay, 960 mode->vtotal - mode->vsync_end, 961 mode->vsync_end - mode->vsync_start); 962 963 /* Convert video timings to ltdc timings */ 964 hsync = mode->hsync_end - mode->hsync_start - 1; 965 vsync = mode->vsync_end - mode->vsync_start - 1; 966 accum_hbp = mode->htotal - mode->hsync_start - 1; 967 accum_vbp = mode->vtotal - mode->vsync_start - 1; 968 accum_act_w = accum_hbp + mode->hdisplay; 969 accum_act_h = accum_vbp + mode->vdisplay; 970 total_width = mode->htotal - 1; 971 total_height = mode->vtotal - 1; 972 973 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 974 val = 0; 975 976 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 977 val |= GCR_HSPOL; 978 979 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 980 val |= GCR_VSPOL; 981 982 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 983 val |= GCR_DEPOL; 984 985 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 986 val |= GCR_PCPOL; 987 988 regmap_update_bits(ldev->regmap, LTDC_GCR, 989 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 990 991 /* Set Synchronization size */ 992 val = (hsync << 16) | vsync; 993 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 994 995 /* Set Accumulated Back porch */ 996 val = (accum_hbp << 16) | accum_vbp; 997 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 998 999 /* Set Accumulated Active Width */ 1000 val = (accum_act_w << 16) | accum_act_h; 1001 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 1002 1003 /* Set total width & height */ 1004 val = (total_width << 16) | total_height; 1005 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 1006 1007 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); 1008 1009 /* Configure the output format (hw version dependent) */ 1010 if (ldev->caps.ycbcr_output) { 1011 /* Input video dynamic_range & colorimetry */ 1012 int vic = drm_match_cea_mode(mode); 1013 u32 val; 1014 1015 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 1016 vic == 2 || vic == 3 || vic == 17 || vic == 18) 1017 /* ITU-R BT.601 */ 1018 val = 0; 1019 else 1020 /* ITU-R BT.709 */ 1021 val = EDCR_OCYSEL; 1022 1023 switch (bus_formats) { 1024 case MEDIA_BUS_FMT_YUYV8_1X16: 1025 /* enable ycbcr output converter */ 1026 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); 1027 break; 1028 case MEDIA_BUS_FMT_YVYU8_1X16: 1029 /* enable ycbcr output converter & invert chrominance order */ 1030 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); 1031 break; 1032 default: 1033 /* disable ycbcr output converter */ 1034 regmap_write(ldev->regmap, LTDC_EDCR, 0); 1035 break; 1036 } 1037 } 1038 } 1039 1040 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 1041 struct drm_atomic_commit *state) 1042 { 1043 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1044 struct drm_device *ddev = crtc->dev; 1045 struct drm_pending_vblank_event *event = crtc->state->event; 1046 1047 drm_dbg_atomic(crtc->dev, "\n"); 1048 1049 ltdc_crtc_update_clut(crtc); 1050 1051 /* Commit shadow registers = update planes at next vblank */ 1052 if (!ldev->caps.plane_reg_shadow) 1053 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 1054 1055 if (event) { 1056 crtc->state->event = NULL; 1057 1058 spin_lock_irq(&ddev->event_lock); 1059 if (drm_crtc_vblank_get(crtc) == 0) 1060 drm_crtc_arm_vblank_event(crtc, event); 1061 else 1062 drm_crtc_send_vblank_event(crtc, event); 1063 spin_unlock_irq(&ddev->event_lock); 1064 } 1065 } 1066 1067 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 1068 bool in_vblank_irq, 1069 int *vpos, int *hpos, 1070 ktime_t *stime, ktime_t *etime, 1071 const struct drm_display_mode *mode) 1072 { 1073 struct drm_device *ddev = crtc->dev; 1074 struct ltdc_device *ldev = ddev->dev_private; 1075 int line, vactive_start, vactive_end, vtotal; 1076 1077 if (stime) 1078 *stime = ktime_get(); 1079 1080 /* The active area starts after vsync + front porch and ends 1081 * at vsync + front porc + display size. 1082 * The total height also include back porch. 1083 * We have 3 possible cases to handle: 1084 * - line < vactive_start: vpos = line - vactive_start and will be 1085 * negative 1086 * - vactive_start < line < vactive_end: vpos = line - vactive_start 1087 * and will be positive 1088 * - line > vactive_end: vpos = line - vtotal - vactive_start 1089 * and will negative 1090 * 1091 * Computation for the two first cases are identical so we can 1092 * simplify the code and only test if line > vactive_end 1093 */ 1094 if (pm_runtime_active(ddev->dev)) { 1095 regmap_read(ldev->regmap, LTDC_CPSR, &line); 1096 line &= CPSR_CYPOS; 1097 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); 1098 vactive_start &= BPCR_AVBP; 1099 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); 1100 vactive_end &= AWCR_AAH; 1101 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); 1102 vtotal &= TWCR_TOTALH; 1103 1104 if (line > vactive_end) 1105 *vpos = line - vtotal - vactive_start; 1106 else 1107 *vpos = line - vactive_start; 1108 } else { 1109 *vpos = 0; 1110 } 1111 1112 *hpos = 0; 1113 1114 if (etime) 1115 *etime = ktime_get(); 1116 1117 return true; 1118 } 1119 1120 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 1121 .mode_valid = ltdc_crtc_mode_valid, 1122 .mode_fixup = ltdc_crtc_mode_fixup, 1123 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 1124 .atomic_flush = ltdc_crtc_atomic_flush, 1125 .atomic_enable = ltdc_crtc_atomic_enable, 1126 .atomic_disable = ltdc_crtc_atomic_disable, 1127 .get_scanout_position = ltdc_crtc_get_scanout_position, 1128 }; 1129 1130 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 1131 { 1132 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1133 struct drm_crtc_state *state = crtc->state; 1134 1135 drm_dbg_driver(crtc->dev, "\n"); 1136 1137 if (state->enable) 1138 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); 1139 else 1140 return -EPERM; 1141 1142 return 0; 1143 } 1144 1145 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 1146 { 1147 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1148 1149 drm_dbg_driver(crtc->dev, "\n"); 1150 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1151 } 1152 1153 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source) 1154 { 1155 struct ltdc_device *ldev; 1156 int ret; 1157 1158 if (!crtc) 1159 return -ENODEV; 1160 1161 drm_dbg_driver(crtc->dev, "\n"); 1162 1163 ldev = crtc_to_ltdc(crtc); 1164 1165 if (source && strcmp(source, "auto") == 0) { 1166 ldev->crc_active = true; 1167 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1168 } else if (!source) { 1169 ldev->crc_active = false; 1170 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1171 } else { 1172 ret = -EINVAL; 1173 } 1174 1175 ldev->crc_skip_count = 0; 1176 return ret; 1177 } 1178 1179 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, 1180 const char *source, size_t *values_cnt) 1181 { 1182 if (!crtc) 1183 return -ENODEV; 1184 1185 drm_dbg_driver(crtc->dev, "\n"); 1186 1187 if (source && strcmp(source, "auto") != 0) { 1188 drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n", 1189 source, crtc->name); 1190 return -EINVAL; 1191 } 1192 1193 *values_cnt = 1; 1194 return 0; 1195 } 1196 1197 static void ltdc_crtc_atomic_print_state(struct drm_printer *p, 1198 const struct drm_crtc_state *state) 1199 { 1200 struct drm_crtc *crtc = state->crtc; 1201 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1202 1203 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); 1204 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); 1205 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); 1206 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); 1207 } 1208 1209 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 1210 .set_config = drm_atomic_helper_set_config, 1211 .page_flip = drm_atomic_helper_page_flip, 1212 .reset = drm_atomic_helper_crtc_reset, 1213 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1214 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1215 .enable_vblank = ltdc_crtc_enable_vblank, 1216 .disable_vblank = ltdc_crtc_disable_vblank, 1217 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1218 .atomic_print_state = ltdc_crtc_atomic_print_state, 1219 }; 1220 1221 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { 1222 .set_config = drm_atomic_helper_set_config, 1223 .page_flip = drm_atomic_helper_page_flip, 1224 .reset = drm_atomic_helper_crtc_reset, 1225 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1226 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1227 .enable_vblank = ltdc_crtc_enable_vblank, 1228 .disable_vblank = ltdc_crtc_disable_vblank, 1229 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1230 .set_crc_source = ltdc_crtc_set_crc_source, 1231 .verify_crc_source = ltdc_crtc_verify_crc_source, 1232 .atomic_print_state = ltdc_crtc_atomic_print_state, 1233 }; 1234 1235 /* 1236 * DRM_PLANE 1237 */ 1238 1239 static int ltdc_plane_atomic_check(struct drm_plane *plane, 1240 struct drm_atomic_commit *state) 1241 { 1242 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1243 plane); 1244 struct drm_framebuffer *fb = new_plane_state->fb; 1245 u32 src_w, src_h; 1246 1247 drm_dbg_driver(plane->dev, "\n"); 1248 1249 if (!fb) 1250 return 0; 1251 1252 /* convert src_ from 16:16 format */ 1253 src_w = new_plane_state->src_w >> 16; 1254 src_h = new_plane_state->src_h >> 16; 1255 1256 /* Reject scaling */ 1257 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1258 drm_dbg_driver(plane->dev, "Scaling is not supported"); 1259 1260 return -EINVAL; 1261 } 1262 1263 return 0; 1264 } 1265 1266 static void ltdc_plane_atomic_update(struct drm_plane *plane, 1267 struct drm_atomic_commit *state) 1268 { 1269 struct ltdc_device *ldev = plane_to_ltdc(plane); 1270 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 1271 plane); 1272 struct drm_framebuffer *fb = newstate->fb; 1273 u32 lofs = plane->index * LAY_OFS; 1274 u32 x0 = newstate->crtc_x; 1275 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 1276 u32 y0 = newstate->crtc_y; 1277 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 1278 u32 src_x, src_y, src_w, src_h; 1279 u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr; 1280 u32 paddr, paddr1, paddr2; 1281 enum ltdc_pix_fmt pf; 1282 1283 if (!newstate->crtc || !fb) { 1284 drm_dbg_driver(plane->dev, "fb or crtc NULL"); 1285 return; 1286 } 1287 1288 /* convert src_ from 16:16 format */ 1289 src_x = newstate->src_x >> 16; 1290 src_y = newstate->src_y >> 16; 1291 src_w = newstate->src_w >> 16; 1292 src_h = newstate->src_h >> 16; 1293 1294 drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1295 plane->base.id, fb->base.id, 1296 src_w, src_h, src_x, src_y, 1297 newstate->crtc_w, newstate->crtc_h, 1298 newstate->crtc_x, newstate->crtc_y); 1299 1300 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1301 1302 ahbp = (bpcr & BPCR_AHBP) >> 16; 1303 avbp = bpcr & BPCR_AVBP; 1304 1305 /* Configures the horizontal start and stop position */ 1306 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 1307 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, 1308 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 1309 1310 /* Configures the vertical start and stop position */ 1311 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 1312 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, 1313 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 1314 1315 /* Specifies the pixel format */ 1316 pf = to_ltdc_pixelformat(fb->format->format); 1317 for (val = 0; val < NB_PF; val++) 1318 if (ldev->caps.pix_fmt_hw[val] == pf) 1319 break; 1320 1321 /* Use the flexible color format feature if necessary and available */ 1322 if (ldev->caps.pix_fmt_flex && val == NB_PF) 1323 val = ltdc_set_flexible_pixel_format(plane, pf); 1324 1325 if (val == NB_PF) { 1326 drm_err(fb->dev, "Pixel format %.4s not supported\n", 1327 (char *)&fb->format->format); 1328 val = 0; /* set by default ARGB 32 bits */ 1329 } 1330 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 1331 1332 /* Specifies the constant alpha value */ 1333 val = newstate->alpha >> 8; 1334 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 1335 1336 /* Specifies the blending factors */ 1337 val = BF1_PAXCA | BF2_1PAXCA; 1338 if (!fb->format->has_alpha) 1339 val = BF1_CA | BF2_1CA; 1340 1341 /* Manage hw-specific capabilities */ 1342 if (ldev->caps.non_alpha_only_l1 && 1343 plane->type != DRM_PLANE_TYPE_PRIMARY) 1344 val = BF1_PAXCA | BF2_1PAXCA; 1345 1346 if (ldev->caps.dynamic_zorder) { 1347 val |= (newstate->normalized_zpos << 16); 1348 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1349 LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val); 1350 } else { 1351 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1352 LXBFCR_BF2 | LXBFCR_BF1, val); 1353 } 1354 1355 /* Sets the FB address */ 1356 paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0); 1357 1358 if (newstate->rotation & DRM_MODE_REFLECT_X) 1359 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; 1360 1361 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1362 paddr += (fb->pitches[0] * (y1 - y0)); 1363 1364 drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr); 1365 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1366 1367 /* Configures the color frame buffer pitch in bytes & line length */ 1368 line_length = fb->format->cpp[0] * 1369 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 1370 1371 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1372 /* Compute negative value (signed on 16 bits) for the picth */ 1373 pitch_in_bytes = 0x10000 - fb->pitches[0]; 1374 else 1375 pitch_in_bytes = fb->pitches[0]; 1376 1377 val = (pitch_in_bytes << 16) | line_length; 1378 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 1379 1380 /* Configures the frame buffer line number */ 1381 line_number = y1 - y0 + 1; 1382 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); 1383 1384 if (ldev->caps.ycbcr_input) { 1385 if (fb->format->is_yuv) { 1386 switch (fb->format->format) { 1387 case DRM_FORMAT_NV12: 1388 case DRM_FORMAT_NV21: 1389 /* Configure the auxiliary frame buffer address 0 */ 1390 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1391 1392 if (newstate->rotation & DRM_MODE_REFLECT_X) 1393 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1394 1395 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1396 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1397 1398 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1399 break; 1400 case DRM_FORMAT_YUV420: 1401 /* Configure the auxiliary frame buffer address 0 & 1 */ 1402 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1403 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1404 1405 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1406 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1407 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1408 } 1409 1410 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1411 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1412 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1413 } 1414 1415 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1416 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1417 break; 1418 case DRM_FORMAT_YVU420: 1419 /* Configure the auxiliary frame buffer address 0 & 1 */ 1420 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1421 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1422 1423 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1424 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1425 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1426 } 1427 1428 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1429 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1430 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1431 } 1432 1433 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1434 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1435 break; 1436 } 1437 1438 /* 1439 * Set the length and the number of lines of the auxiliary 1440 * buffers if the framebuffer contains more than one plane. 1441 */ 1442 if (fb->format->num_planes > 1) { 1443 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1444 /* 1445 * Compute negative value (signed on 16 bits) 1446 * for the picth 1447 */ 1448 pitch_in_bytes = 0x10000 - fb->pitches[1]; 1449 else 1450 pitch_in_bytes = fb->pitches[1]; 1451 1452 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + 1453 (ldev->caps.bus_width >> 3) - 1; 1454 1455 /* Configure the auxiliary buffer length */ 1456 val = (pitch_in_bytes << 16) | line_length; 1457 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1458 1459 /* Configure the auxiliary frame buffer line number */ 1460 val = line_number >> 1; 1461 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1462 } 1463 1464 /* Configure YCbC conversion coefficient */ 1465 ltdc_set_ycbcr_coeffs(plane); 1466 1467 /* Configure YCbCr format and enable/disable conversion */ 1468 ltdc_set_ycbcr_config(plane, fb->format->format); 1469 } else { 1470 /* disable ycbcr conversion */ 1471 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); 1472 } 1473 } 1474 1475 /* Enable layer and CLUT if needed */ 1476 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 1477 val |= LXCR_LEN; 1478 1479 /* Enable horizontal mirroring if requested */ 1480 if (newstate->rotation & DRM_MODE_REFLECT_X) 1481 val |= LXCR_HMEN; 1482 1483 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, val); 1484 1485 /* Commit shadow registers = update plane at next vblank */ 1486 if (ldev->caps.plane_reg_shadow) 1487 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1488 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1489 1490 ldev->plane_fpsi[plane->index].counter++; 1491 1492 mutex_lock(&ldev->err_lock); 1493 if (ldev->transfer_err) { 1494 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); 1495 ldev->transfer_err = 0; 1496 } 1497 1498 if (ldev->caps.fifo_threshold) { 1499 if (ldev->fifo_err) { 1500 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1501 ldev->fifo_err = 0; 1502 } 1503 } else { 1504 if (ldev->fifo_warn >= ldev->fifo_threshold) { 1505 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1506 ldev->fifo_warn = 0; 1507 } 1508 } 1509 mutex_unlock(&ldev->err_lock); 1510 } 1511 1512 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 1513 struct drm_atomic_commit *state) 1514 { 1515 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 1516 plane); 1517 struct ltdc_device *ldev = plane_to_ltdc(plane); 1518 u32 lofs = plane->index * LAY_OFS; 1519 1520 /* Disable layer */ 1521 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, 0); 1522 1523 /* Reset the layer transparency to hide any related background color */ 1524 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00); 1525 1526 /* Commit shadow registers = update plane at next vblank */ 1527 if (ldev->caps.plane_reg_shadow) 1528 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1529 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1530 1531 drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n", 1532 oldstate->crtc->base.id, plane->base.id); 1533 } 1534 1535 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 1536 const struct drm_plane_state *state) 1537 { 1538 struct drm_plane *plane = state->plane; 1539 struct ltdc_device *ldev = plane_to_ltdc(plane); 1540 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 1541 int ms_since_last; 1542 ktime_t now; 1543 1544 now = ktime_get(); 1545 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 1546 1547 drm_printf(p, "\tuser_updates=%dfps\n", 1548 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 1549 1550 fpsi->last_timestamp = now; 1551 fpsi->counter = 0; 1552 } 1553 1554 static const struct drm_plane_funcs ltdc_plane_funcs = { 1555 .update_plane = drm_atomic_helper_update_plane, 1556 .disable_plane = drm_atomic_helper_disable_plane, 1557 .reset = drm_atomic_helper_plane_reset, 1558 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1559 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1560 .atomic_print_state = ltdc_plane_atomic_print_state, 1561 }; 1562 1563 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 1564 .atomic_check = ltdc_plane_atomic_check, 1565 .atomic_update = ltdc_plane_atomic_update, 1566 .atomic_disable = ltdc_plane_atomic_disable, 1567 }; 1568 1569 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 1570 enum drm_plane_type type, 1571 int index) 1572 { 1573 unsigned long possible_crtcs = CRTC_MASK; 1574 struct ltdc_device *ldev = ddev->dev_private; 1575 struct device *dev = ddev->dev; 1576 struct drm_plane *plane; 1577 unsigned int i, nb_fmt = 0; 1578 u32 *formats; 1579 u32 drm_fmt; 1580 const u64 *modifiers = ltdc_format_modifiers; 1581 u32 lofs = index * LAY_OFS; 1582 u32 val; 1583 1584 /* Allocate the biggest size according to supported color formats */ 1585 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + 1586 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) + 1587 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) + 1588 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) * 1589 sizeof(*formats), GFP_KERNEL); 1590 if (!formats) 1591 return NULL; 1592 1593 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { 1594 drm_fmt = ldev->caps.pix_fmt_drm[i]; 1595 1596 /* Manage hw-specific capabilities */ 1597 if (ldev->caps.non_alpha_only_l1) 1598 /* XR24 & RX24 like formats supported only on primary layer */ 1599 if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt)) 1600 continue; 1601 1602 formats[nb_fmt++] = drm_fmt; 1603 } 1604 1605 /* Add YCbCr supported pixel formats */ 1606 if (ldev->caps.ycbcr_input) { 1607 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); 1608 if (val & LXCR_C1R_YIA) { 1609 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp, 1610 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats)); 1611 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp); 1612 } 1613 if (val & LXCR_C1R_YSPA) { 1614 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp, 1615 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats)); 1616 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp); 1617 } 1618 if (val & LXCR_C1R_YFPA) { 1619 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp, 1620 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats)); 1621 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp); 1622 } 1623 } 1624 1625 plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev, 1626 possible_crtcs, <dc_plane_funcs, formats, 1627 nb_fmt, modifiers, type, NULL); 1628 if (IS_ERR(plane)) 1629 return NULL; 1630 1631 if (ldev->caps.ycbcr_input) { 1632 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA)) 1633 drm_plane_create_color_properties(plane, 1634 BIT(DRM_COLOR_YCBCR_BT601) | 1635 BIT(DRM_COLOR_YCBCR_BT709), 1636 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1637 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1638 DRM_COLOR_YCBCR_BT601, 1639 DRM_COLOR_YCBCR_LIMITED_RANGE); 1640 } 1641 1642 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 1643 1644 drm_plane_create_alpha_property(plane); 1645 1646 drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id); 1647 1648 return plane; 1649 } 1650 1651 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1652 { 1653 struct ltdc_device *ldev = ddev->dev_private; 1654 struct drm_plane *primary, *overlay; 1655 int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 1656 unsigned int i; 1657 int ret; 1658 1659 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1660 if (!primary) { 1661 drm_err(ddev, "Can not create primary plane\n"); 1662 return -EINVAL; 1663 } 1664 1665 if (ldev->caps.dynamic_zorder) 1666 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); 1667 else 1668 drm_plane_create_zpos_immutable_property(primary, 0); 1669 1670 if (ldev->caps.plane_rotation) 1671 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, 1672 supported_rotations); 1673 1674 /* Init CRTC according to its hardware features */ 1675 if (ldev->caps.crc) 1676 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1677 <dc_crtc_with_crc_support_funcs, NULL); 1678 else 1679 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1680 <dc_crtc_funcs, NULL); 1681 if (ret) { 1682 drm_err(ddev, "Can not initialize CRTC\n"); 1683 return ret; 1684 } 1685 1686 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1687 1688 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1689 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1690 1691 drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id); 1692 1693 /* Add planes. Note : the first layer is used by primary plane */ 1694 for (i = 1; i < ldev->caps.nb_layers; i++) { 1695 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1696 if (!overlay) { 1697 drm_err(ddev, "Can not create overlay plane %d\n", i); 1698 return -ENOMEM; 1699 } 1700 if (ldev->caps.dynamic_zorder) 1701 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); 1702 else 1703 drm_plane_create_zpos_immutable_property(overlay, i); 1704 1705 if (ldev->caps.plane_rotation) 1706 drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0, 1707 supported_rotations); 1708 } 1709 1710 return 0; 1711 } 1712 1713 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1714 { 1715 struct drm_device *ddev = encoder->dev; 1716 struct ltdc_device *ldev = ddev->dev_private; 1717 1718 drm_dbg_driver(encoder->dev, "\n"); 1719 1720 /* Disable LTDC */ 1721 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1722 1723 /* Set to sleep state the pinctrl whatever type of encoder */ 1724 pinctrl_pm_select_sleep_state(ddev->dev); 1725 } 1726 1727 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1728 { 1729 struct drm_device *ddev = encoder->dev; 1730 struct ltdc_device *ldev = ddev->dev_private; 1731 1732 drm_dbg_driver(encoder->dev, "\n"); 1733 1734 /* set fifo underrun threshold register */ 1735 if (ldev->caps.fifo_threshold) 1736 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); 1737 1738 /* Enable LTDC */ 1739 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1740 } 1741 1742 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1743 struct drm_display_mode *mode, 1744 struct drm_display_mode *adjusted_mode) 1745 { 1746 struct drm_device *ddev = encoder->dev; 1747 1748 drm_dbg_driver(encoder->dev, "\n"); 1749 1750 /* 1751 * Set to default state the pinctrl only with DPI type. 1752 * Others types like DSI, don't need pinctrl due to 1753 * internal bridge (the signals do not come out of the chipset). 1754 */ 1755 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1756 pinctrl_pm_select_default_state(ddev->dev); 1757 } 1758 1759 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1760 .disable = ltdc_encoder_disable, 1761 .enable = ltdc_encoder_enable, 1762 .mode_set = ltdc_encoder_mode_set, 1763 }; 1764 1765 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1766 { 1767 struct drm_encoder *encoder; 1768 int ret; 1769 1770 encoder = drmm_simple_encoder_alloc(ddev, struct drm_encoder, dev, 1771 DRM_MODE_ENCODER_DPI); 1772 if (IS_ERR(encoder)) 1773 return PTR_ERR(encoder); 1774 1775 encoder->possible_crtcs = CRTC_MASK; 1776 encoder->possible_clones = 0; /* No cloning support */ 1777 1778 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1779 1780 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1781 if (ret) 1782 return ret; 1783 1784 drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base.id); 1785 1786 return 0; 1787 } 1788 1789 static int ltdc_get_caps(struct drm_device *ddev) 1790 { 1791 struct ltdc_device *ldev = ddev->dev_private; 1792 u32 bus_width_log2, lcr, gc2r; 1793 const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev); 1794 1795 /* 1796 * at least 1 layer must be managed & the number of layers 1797 * must not exceed LTDC_MAX_LAYER 1798 */ 1799 regmap_read(ldev->regmap, LTDC_LCR, &lcr); 1800 1801 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1802 1803 /* set data bus width */ 1804 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); 1805 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1806 ldev->caps.bus_width = 8 << bus_width_log2; 1807 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); 1808 1809 ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz; 1810 1811 switch (ldev->caps.hw_version) { 1812 case HWVER_10200: 1813 case HWVER_10300: 1814 ldev->caps.layer_ofs = LAY_OFS_0; 1815 ldev->caps.layer_regs = ltdc_layer_regs_a0; 1816 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1817 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; 1818 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); 1819 ldev->caps.pix_fmt_flex = false; 1820 /* 1821 * Hw older versions support non-alpha color formats derived 1822 * from native alpha color formats only on the primary layer. 1823 * For instance, RG16 native format without alpha works fine 1824 * on 2nd layer but XR24 (derived color format from AR24) 1825 * does not work on 2nd layer. 1826 */ 1827 ldev->caps.non_alpha_only_l1 = true; 1828 if (ldev->caps.hw_version == HWVER_10200) 1829 ldev->caps.pad_max_freq_hz = 65000000; 1830 ldev->caps.nb_irq = 2; 1831 ldev->caps.ycbcr_input = false; 1832 ldev->caps.ycbcr_output = false; 1833 ldev->caps.plane_reg_shadow = false; 1834 ldev->caps.crc = false; 1835 ldev->caps.dynamic_zorder = false; 1836 ldev->caps.plane_rotation = false; 1837 ldev->caps.fifo_threshold = false; 1838 break; 1839 case HWVER_20101: 1840 ldev->caps.layer_ofs = LAY_OFS_0; 1841 ldev->caps.layer_regs = ltdc_layer_regs_a1; 1842 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1843 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; 1844 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); 1845 ldev->caps.pix_fmt_flex = false; 1846 ldev->caps.non_alpha_only_l1 = false; 1847 ldev->caps.pad_max_freq_hz = 150000000; 1848 ldev->caps.nb_irq = 4; 1849 ldev->caps.ycbcr_input = false; 1850 ldev->caps.ycbcr_output = false; 1851 ldev->caps.plane_reg_shadow = false; 1852 ldev->caps.crc = false; 1853 ldev->caps.dynamic_zorder = false; 1854 ldev->caps.plane_rotation = false; 1855 ldev->caps.fifo_threshold = false; 1856 break; 1857 case HWVER_40100: 1858 case HWVER_40101: 1859 ldev->caps.layer_ofs = LAY_OFS_1; 1860 ldev->caps.layer_regs = ltdc_layer_regs_a2; 1861 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; 1862 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; 1863 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); 1864 ldev->caps.pix_fmt_flex = true; 1865 ldev->caps.non_alpha_only_l1 = false; 1866 ldev->caps.nb_irq = 2; 1867 ldev->caps.ycbcr_input = true; 1868 ldev->caps.ycbcr_output = true; 1869 ldev->caps.plane_reg_shadow = true; 1870 ldev->caps.crc = true; 1871 ldev->caps.dynamic_zorder = true; 1872 ldev->caps.plane_rotation = true; 1873 ldev->caps.fifo_threshold = true; 1874 break; 1875 default: 1876 return -ENODEV; 1877 } 1878 1879 return 0; 1880 } 1881 1882 void ltdc_suspend(struct drm_device *ddev) 1883 { 1884 struct ltdc_device *ldev = ddev->dev_private; 1885 1886 drm_dbg_driver(ddev, "\n"); 1887 clk_disable_unprepare(ldev->pixel_clk); 1888 if (ldev->bus_clk) 1889 clk_disable_unprepare(ldev->bus_clk); 1890 if (ldev->lvds_clk) 1891 clk_disable_unprepare(ldev->lvds_clk); 1892 } 1893 1894 int ltdc_resume(struct drm_device *ddev) 1895 { 1896 struct ltdc_device *ldev = ddev->dev_private; 1897 int ret; 1898 1899 drm_dbg_driver(ddev, "\n"); 1900 1901 ret = clk_prepare_enable(ldev->pixel_clk); 1902 if (ret) { 1903 drm_err(ddev, "failed to enable pixel clock (%d)\n", ret); 1904 return ret; 1905 } 1906 1907 if (ldev->bus_clk) { 1908 ret = clk_prepare_enable(ldev->bus_clk); 1909 if (ret) { 1910 drm_err(ddev, "failed to enable bus clock (%d)\n", ret); 1911 return ret; 1912 } 1913 } 1914 1915 if (ldev->lvds_clk) { 1916 ret = clk_prepare_enable(ldev->lvds_clk); 1917 if (ret) 1918 drm_err(ddev, "failed to prepare lvds clock\n"); 1919 } 1920 1921 return ret; 1922 } 1923 1924 int ltdc_load(struct drm_device *ddev) 1925 { 1926 struct platform_device *pdev = to_platform_device(ddev->dev); 1927 struct ltdc_device *ldev = ddev->dev_private; 1928 struct device *dev = ddev->dev; 1929 struct device_node *np = dev->of_node; 1930 struct drm_bridge *bridge; 1931 struct drm_panel *panel; 1932 struct drm_crtc *crtc; 1933 struct reset_control *rstc; 1934 int irq, i, nb_endpoints; 1935 int ret = -ENODEV; 1936 1937 drm_dbg_driver(ddev, "\n"); 1938 1939 /* Get number of endpoints */ 1940 nb_endpoints = of_graph_get_endpoint_count(np); 1941 if (!nb_endpoints) 1942 return -ENODEV; 1943 1944 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1945 if (IS_ERR(ldev->pixel_clk)) { 1946 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1947 drm_err(ddev, "Unable to get lcd clock\n"); 1948 return PTR_ERR(ldev->pixel_clk); 1949 } 1950 1951 if (clk_prepare_enable(ldev->pixel_clk)) { 1952 drm_err(ddev, "Unable to prepare pixel clock\n"); 1953 return -ENODEV; 1954 } 1955 1956 if (of_device_is_compatible(np, "st,stm32mp251-ltdc") || 1957 of_device_is_compatible(np, "st,stm32mp255-ltdc")) { 1958 ldev->bus_clk = devm_clk_get(dev, "bus"); 1959 if (IS_ERR(ldev->bus_clk)) 1960 return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), 1961 "Unable to get bus clock\n"); 1962 1963 ret = clk_prepare_enable(ldev->bus_clk); 1964 if (ret) { 1965 drm_err(ddev, "Unable to prepare bus clock\n"); 1966 return ret; 1967 } 1968 } 1969 1970 /* Get endpoints if any */ 1971 for (i = 0; i < nb_endpoints; i++) { 1972 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1973 1974 /* 1975 * If at least one endpoint is -ENODEV, continue probing, 1976 * else if at least one endpoint returned an error 1977 * (ie -EPROBE_DEFER) then stop probing. 1978 */ 1979 if (ret == -ENODEV) 1980 continue; 1981 else if (ret) 1982 goto err; 1983 1984 if (panel) { 1985 bridge = drmm_panel_bridge_add(ddev, panel); 1986 drm_panel_put(panel); 1987 if (IS_ERR(bridge)) { 1988 drm_err(ddev, "panel-bridge endpoint %d\n", i); 1989 ret = PTR_ERR(bridge); 1990 goto err; 1991 } 1992 } 1993 1994 if (bridge) { 1995 ret = ltdc_encoder_init(ddev, bridge); 1996 if (ret) { 1997 if (ret != -EPROBE_DEFER) 1998 drm_err(ddev, "init encoder endpoint %d\n", i); 1999 goto err; 2000 } 2001 } 2002 } 2003 2004 ldev->lvds_clk = devm_clk_get(dev, "lvds"); 2005 if (IS_ERR(ldev->lvds_clk)) 2006 ldev->lvds_clk = NULL; 2007 2008 rstc = devm_reset_control_get_exclusive(dev, NULL); 2009 2010 mutex_init(&ldev->err_lock); 2011 2012 if (!IS_ERR(rstc)) { 2013 reset_control_assert(rstc); 2014 usleep_range(10, 20); 2015 reset_control_deassert(rstc); 2016 } 2017 2018 ldev->regs = devm_platform_ioremap_resource(pdev, 0); 2019 if (IS_ERR(ldev->regs)) { 2020 drm_err(ddev, "Unable to get ltdc registers\n"); 2021 ret = PTR_ERR(ldev->regs); 2022 goto err; 2023 } 2024 2025 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 2026 if (IS_ERR(ldev->regmap)) { 2027 drm_err(ddev, "Unable to regmap ltdc registers\n"); 2028 ret = PTR_ERR(ldev->regmap); 2029 goto err; 2030 } 2031 2032 ret = ltdc_get_caps(ddev); 2033 if (ret) { 2034 drm_err(ddev, "hardware identifier (0x%08x) not supported!\n", 2035 ldev->caps.hw_version); 2036 goto err; 2037 } 2038 2039 /* Disable all interrupts */ 2040 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); 2041 2042 drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version); 2043 2044 /* initialize default value for fifo underrun threshold & clear interrupt error counters */ 2045 ldev->transfer_err = 0; 2046 ldev->fifo_err = 0; 2047 ldev->fifo_warn = 0; 2048 ldev->fifo_threshold = FUT_DFT; 2049 2050 for (i = 0; i < ldev->caps.nb_irq; i++) { 2051 irq = platform_get_irq(pdev, i); 2052 if (irq < 0) { 2053 ret = irq; 2054 goto err; 2055 } 2056 2057 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 2058 ltdc_irq_thread, IRQF_ONESHOT, 2059 dev_name(dev), ddev); 2060 if (ret) { 2061 drm_err(ddev, "Failed to register LTDC interrupt\n"); 2062 goto err; 2063 } 2064 } 2065 2066 crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); 2067 if (!crtc) { 2068 drm_err(ddev, "Failed to allocate crtc\n"); 2069 ret = -ENOMEM; 2070 goto err; 2071 } 2072 2073 ret = ltdc_crtc_init(ddev, crtc); 2074 if (ret) { 2075 drm_err(ddev, "Failed to init crtc\n"); 2076 goto err; 2077 } 2078 2079 ret = drm_vblank_init(ddev, NB_CRTC); 2080 if (ret) { 2081 drm_err(ddev, "Failed calling drm_vblank_init()\n"); 2082 goto err; 2083 } 2084 2085 clk_disable_unprepare(ldev->pixel_clk); 2086 2087 if (ldev->bus_clk) 2088 clk_disable_unprepare(ldev->bus_clk); 2089 2090 pinctrl_pm_select_sleep_state(ddev->dev); 2091 2092 pm_runtime_enable(ddev->dev); 2093 2094 return 0; 2095 err: 2096 clk_disable_unprepare(ldev->pixel_clk); 2097 2098 if (ldev->bus_clk) 2099 clk_disable_unprepare(ldev->bus_clk); 2100 2101 return ret; 2102 } 2103 2104 void ltdc_unload(struct drm_device *ddev) 2105 { 2106 drm_dbg_driver(ddev, "\n"); 2107 2108 pm_runtime_disable(ddev->dev); 2109 } 2110 2111 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 2112 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2113 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 2114 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 2115 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 2116 MODULE_LICENSE("GPL v2"); 2117