1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/media-bus-format.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_graph.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #include <drm/drm_atomic.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_blend.h> 28 #include <drm/drm_bridge.h> 29 #include <drm/drm_device.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_fb_dma_helper.h> 32 #include <drm/drm_fourcc.h> 33 #include <drm/drm_framebuffer.h> 34 #include <drm/drm_gem_atomic_helper.h> 35 #include <drm/drm_gem_dma_helper.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_simple_kms_helper.h> 39 #include <drm/drm_vblank.h> 40 #include <drm/drm_managed.h> 41 42 #include <video/videomode.h> 43 44 #include "ltdc.h" 45 46 #define NB_CRTC 1 47 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 48 49 #define MAX_IRQ 4 50 51 #define HWVER_10200 0x010200 52 #define HWVER_10300 0x010300 53 #define HWVER_20101 0x020101 54 #define HWVER_40100 0x040100 55 #define HWVER_40101 0x040101 56 57 /* 58 * The address of some registers depends on the HW version: such registers have 59 * an extra offset specified with layer_ofs. 60 */ 61 #define LAY_OFS_0 0x80 62 #define LAY_OFS_1 0x100 63 #define LAY_OFS (ldev->caps.layer_ofs) 64 65 /* Global register offsets */ 66 #define LTDC_IDR 0x0000 /* IDentification */ 67 #define LTDC_LCR 0x0004 /* Layer Count */ 68 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 69 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 70 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 71 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 72 #define LTDC_GCR 0x0018 /* Global Control */ 73 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 74 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 75 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 76 #define LTDC_GACR 0x0028 /* GAmma Correction */ 77 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 78 #define LTDC_IER 0x0034 /* Interrupt Enable */ 79 #define LTDC_ISR 0x0038 /* Interrupt Status */ 80 #define LTDC_ICR 0x003C /* Interrupt Clear */ 81 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 82 #define LTDC_CPSR 0x0044 /* Current Position Status */ 83 #define LTDC_CDSR 0x0048 /* Current Display Status */ 84 #define LTDC_EDCR 0x0060 /* External Display Control */ 85 #define LTDC_CCRCR 0x007C /* Computed CRC value */ 86 #define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ 87 88 /* Layer register offsets */ 89 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ 90 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ 91 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ 92 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ 93 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ 94 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ 95 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ 96 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ 97 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ 98 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ 99 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ 100 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ 101 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ 102 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ 103 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ 104 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ 105 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ 106 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ 107 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ 108 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ 109 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ 110 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ 111 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ 112 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ 113 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ 114 115 /* Bit definitions */ 116 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 117 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 118 119 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 120 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 121 122 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 123 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 124 125 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 126 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 127 128 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 129 #define GCR_DEN BIT(16) /* Dither ENable */ 130 #define GCR_CRCEN BIT(19) /* CRC ENable */ 131 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 132 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 133 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 134 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 135 136 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 137 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 138 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 139 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 140 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 141 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 142 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 143 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 144 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 145 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 146 #define GC1R_TP BIT(25) /* Timing Programmable */ 147 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 148 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 149 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 150 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 151 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 152 153 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 154 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 155 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 156 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 157 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 158 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 159 160 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 161 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 162 163 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 164 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 165 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 166 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 167 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 168 169 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 170 #define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */ 171 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 172 #define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */ 173 #define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */ 174 #define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */ 175 #define IER_MASK (IER_LIE | IER_FUWIE | IER_TERRIE | IER_RRIE | IER_FUEIE | IER_CRCIE) 176 177 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 178 179 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 180 #define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */ 181 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 182 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 183 #define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */ 184 #define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */ 185 186 #define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ 187 #define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ 188 #define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */ 189 190 #define LXCR_LEN BIT(0) /* Layer ENable */ 191 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 192 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 193 #define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */ 194 #define LXCR_MASK (LXCR_LEN | LXCR_COLKEN | LXCR_CLUTEN | LXCR_HMEN) 195 196 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 197 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 198 199 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 200 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 201 202 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 203 #define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */ 204 205 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 206 207 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 208 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 209 #define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ 210 211 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 212 #define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */ 213 214 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 215 216 #define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */ 217 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */ 218 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */ 219 #define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/ 220 221 #define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */ 222 #define LxPCR_OF BIT(8) /* Odd pixel First */ 223 #define LxPCR_CBF BIT(7) /* CB component First */ 224 #define LxPCR_YF BIT(6) /* Y component First */ 225 #define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */ 226 #define YCM_I 0x0 /* Interleaved 422 */ 227 #define YCM_SP 0x1 /* Semi-Planar 420 */ 228 #define YCM_FP 0x2 /* Full-Planar 420 */ 229 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */ 230 231 #define LXRCR_IMR BIT(0) /* IMmediate Reload */ 232 #define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */ 233 #define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */ 234 235 #define CLUT_SIZE 256 236 237 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 238 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 239 #define BF1_CA 0x400 /* Constant Alpha */ 240 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 241 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 242 243 #define NB_PF 8 /* Max nb of HW pixel format */ 244 245 #define FUT_DFT 128 /* Default value of fifo underrun threshold */ 246 247 /* 248 * Skip the first value and the second in case CRC was enabled during 249 * the thread irq. This is to be sure CRC value is relevant for the 250 * frame. 251 */ 252 #define CRC_SKIP_FRAMES 2 253 254 enum ltdc_pix_fmt { 255 PF_NONE, 256 /* RGB formats */ 257 PF_ARGB8888, /* ARGB [32 bits] */ 258 PF_RGBA8888, /* RGBA [32 bits] */ 259 PF_ABGR8888, /* ABGR [32 bits] */ 260 PF_BGRA8888, /* BGRA [32 bits] */ 261 PF_RGB888, /* RGB [24 bits] */ 262 PF_BGR888, /* BGR [24 bits] */ 263 PF_RGB565, /* RGB [16 bits] */ 264 PF_BGR565, /* BGR [16 bits] */ 265 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 266 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 267 /* Indexed formats */ 268 PF_L8, /* Indexed 8 bits [8 bits] */ 269 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 270 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 271 }; 272 273 /* The index gives the encoding of the pixel format for an HW version */ 274 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 275 PF_ARGB8888, /* 0x00 */ 276 PF_RGB888, /* 0x01 */ 277 PF_RGB565, /* 0x02 */ 278 PF_ARGB1555, /* 0x03 */ 279 PF_ARGB4444, /* 0x04 */ 280 PF_L8, /* 0x05 */ 281 PF_AL44, /* 0x06 */ 282 PF_AL88 /* 0x07 */ 283 }; 284 285 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 286 PF_ARGB8888, /* 0x00 */ 287 PF_RGB888, /* 0x01 */ 288 PF_RGB565, /* 0x02 */ 289 PF_RGBA8888, /* 0x03 */ 290 PF_AL44, /* 0x04 */ 291 PF_L8, /* 0x05 */ 292 PF_ARGB1555, /* 0x06 */ 293 PF_ARGB4444 /* 0x07 */ 294 }; 295 296 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { 297 PF_ARGB8888, /* 0x00 */ 298 PF_ABGR8888, /* 0x01 */ 299 PF_RGBA8888, /* 0x02 */ 300 PF_BGRA8888, /* 0x03 */ 301 PF_RGB565, /* 0x04 */ 302 PF_BGR565, /* 0x05 */ 303 PF_RGB888, /* 0x06 */ 304 PF_NONE /* 0x07 */ 305 }; 306 307 static const u32 ltdc_drm_fmt_a0[] = { 308 DRM_FORMAT_ARGB8888, 309 DRM_FORMAT_XRGB8888, 310 DRM_FORMAT_RGB888, 311 DRM_FORMAT_RGB565, 312 DRM_FORMAT_ARGB1555, 313 DRM_FORMAT_XRGB1555, 314 DRM_FORMAT_ARGB4444, 315 DRM_FORMAT_XRGB4444, 316 DRM_FORMAT_C8 317 }; 318 319 static const u32 ltdc_drm_fmt_a1[] = { 320 DRM_FORMAT_ARGB8888, 321 DRM_FORMAT_XRGB8888, 322 DRM_FORMAT_RGB888, 323 DRM_FORMAT_RGB565, 324 DRM_FORMAT_RGBA8888, 325 DRM_FORMAT_RGBX8888, 326 DRM_FORMAT_ARGB1555, 327 DRM_FORMAT_XRGB1555, 328 DRM_FORMAT_ARGB4444, 329 DRM_FORMAT_XRGB4444, 330 DRM_FORMAT_C8 331 }; 332 333 static const u32 ltdc_drm_fmt_a2[] = { 334 DRM_FORMAT_ARGB8888, 335 DRM_FORMAT_XRGB8888, 336 DRM_FORMAT_ABGR8888, 337 DRM_FORMAT_XBGR8888, 338 DRM_FORMAT_RGBA8888, 339 DRM_FORMAT_RGBX8888, 340 DRM_FORMAT_BGRA8888, 341 DRM_FORMAT_BGRX8888, 342 DRM_FORMAT_RGB565, 343 DRM_FORMAT_BGR565, 344 DRM_FORMAT_RGB888, 345 DRM_FORMAT_BGR888, 346 DRM_FORMAT_ARGB1555, 347 DRM_FORMAT_XRGB1555, 348 DRM_FORMAT_ARGB4444, 349 DRM_FORMAT_XRGB4444, 350 DRM_FORMAT_C8 351 }; 352 353 static const u32 ltdc_drm_fmt_ycbcr_cp[] = { 354 DRM_FORMAT_YUYV, 355 DRM_FORMAT_YVYU, 356 DRM_FORMAT_UYVY, 357 DRM_FORMAT_VYUY 358 }; 359 360 static const u32 ltdc_drm_fmt_ycbcr_sp[] = { 361 DRM_FORMAT_NV12, 362 DRM_FORMAT_NV21 363 }; 364 365 static const u32 ltdc_drm_fmt_ycbcr_fp[] = { 366 DRM_FORMAT_YUV420, 367 DRM_FORMAT_YVU420 368 }; 369 370 /* Layer register offsets */ 371 static const u32 ltdc_layer_regs_a0[] = { 372 0x80, /* L1 configuration 0 */ 373 0x00, /* not available */ 374 0x00, /* not available */ 375 0x84, /* L1 control register */ 376 0x88, /* L1 window horizontal position configuration */ 377 0x8c, /* L1 window vertical position configuration */ 378 0x90, /* L1 color keying configuration */ 379 0x94, /* L1 pixel format configuration */ 380 0x98, /* L1 constant alpha configuration */ 381 0x9c, /* L1 default color configuration */ 382 0xa0, /* L1 blending factors configuration */ 383 0x00, /* not available */ 384 0x00, /* not available */ 385 0xac, /* L1 color frame buffer address */ 386 0xb0, /* L1 color frame buffer length */ 387 0xb4, /* L1 color frame buffer line number */ 388 0x00, /* not available */ 389 0x00, /* not available */ 390 0x00, /* not available */ 391 0x00, /* not available */ 392 0xc4, /* L1 CLUT write */ 393 0x00, /* not available */ 394 0x00, /* not available */ 395 0x00, /* not available */ 396 0x00 /* not available */ 397 }; 398 399 static const u32 ltdc_layer_regs_a1[] = { 400 0x80, /* L1 configuration 0 */ 401 0x84, /* L1 configuration 1 */ 402 0x00, /* L1 reload control */ 403 0x88, /* L1 control register */ 404 0x8c, /* L1 window horizontal position configuration */ 405 0x90, /* L1 window vertical position configuration */ 406 0x94, /* L1 color keying configuration */ 407 0x98, /* L1 pixel format configuration */ 408 0x9c, /* L1 constant alpha configuration */ 409 0xa0, /* L1 default color configuration */ 410 0xa4, /* L1 blending factors configuration */ 411 0xa8, /* L1 burst length configuration */ 412 0x00, /* not available */ 413 0xac, /* L1 color frame buffer address */ 414 0xb0, /* L1 color frame buffer length */ 415 0xb4, /* L1 color frame buffer line number */ 416 0xb8, /* L1 auxiliary frame buffer address 0 */ 417 0xbc, /* L1 auxiliary frame buffer address 1 */ 418 0xc0, /* L1 auxiliary frame buffer length */ 419 0xc4, /* L1 auxiliary frame buffer line number */ 420 0xc8, /* L1 CLUT write */ 421 0x00, /* not available */ 422 0x00, /* not available */ 423 0x00, /* not available */ 424 0x00 /* not available */ 425 }; 426 427 static const u32 ltdc_layer_regs_a2[] = { 428 0x100, /* L1 configuration 0 */ 429 0x104, /* L1 configuration 1 */ 430 0x108, /* L1 reload control */ 431 0x10c, /* L1 control register */ 432 0x110, /* L1 window horizontal position configuration */ 433 0x114, /* L1 window vertical position configuration */ 434 0x118, /* L1 color keying configuration */ 435 0x11c, /* L1 pixel format configuration */ 436 0x120, /* L1 constant alpha configuration */ 437 0x124, /* L1 default color configuration */ 438 0x128, /* L1 blending factors configuration */ 439 0x12c, /* L1 burst length configuration */ 440 0x130, /* L1 planar configuration */ 441 0x134, /* L1 color frame buffer address */ 442 0x138, /* L1 color frame buffer length */ 443 0x13c, /* L1 color frame buffer line number */ 444 0x140, /* L1 auxiliary frame buffer address 0 */ 445 0x144, /* L1 auxiliary frame buffer address 1 */ 446 0x148, /* L1 auxiliary frame buffer length */ 447 0x14c, /* L1 auxiliary frame buffer line number */ 448 0x150, /* L1 CLUT write */ 449 0x16c, /* L1 Conversion YCbCr RGB 0 */ 450 0x170, /* L1 Conversion YCbCr RGB 1 */ 451 0x174, /* L1 Flexible Pixel Format 0 */ 452 0x178 /* L1 Flexible Pixel Format 1 */ 453 }; 454 455 static const u64 ltdc_format_modifiers[] = { 456 DRM_FORMAT_MOD_LINEAR, 457 DRM_FORMAT_MOD_INVALID 458 }; 459 460 static const struct regmap_config stm32_ltdc_regmap_cfg = { 461 .reg_bits = 32, 462 .val_bits = 32, 463 .reg_stride = sizeof(u32), 464 .max_register = 0x400, 465 .use_relaxed_mmio = true, 466 .cache_type = REGCACHE_NONE, 467 }; 468 469 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = { 470 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 471 0x02040199, /* (b_cb = 516 / r_cr = 409) */ 472 0x006400D0 /* (g_cb = 100 / g_cr = 208) */ 473 }, 474 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 475 0x01C60167, /* (b_cb = 454 / r_cr = 359) */ 476 0x005800B7 /* (g_cb = 88 / g_cr = 183) */ 477 }, 478 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 479 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */ 480 0x00370089 /* (g_cb = 55 / g_cr = 137) */ 481 }, 482 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 483 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */ 484 0x00300078 /* (g_cb = 48 / g_cr = 120) */ 485 } 486 /* BT2020 not supported */ 487 }; 488 489 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 490 { 491 return (struct ltdc_device *)crtc->dev->dev_private; 492 } 493 494 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 495 { 496 return (struct ltdc_device *)plane->dev->dev_private; 497 } 498 499 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 500 { 501 enum ltdc_pix_fmt pf; 502 503 switch (drm_fmt) { 504 case DRM_FORMAT_ARGB8888: 505 case DRM_FORMAT_XRGB8888: 506 pf = PF_ARGB8888; 507 break; 508 case DRM_FORMAT_ABGR8888: 509 case DRM_FORMAT_XBGR8888: 510 pf = PF_ABGR8888; 511 break; 512 case DRM_FORMAT_RGBA8888: 513 case DRM_FORMAT_RGBX8888: 514 pf = PF_RGBA8888; 515 break; 516 case DRM_FORMAT_BGRA8888: 517 case DRM_FORMAT_BGRX8888: 518 pf = PF_BGRA8888; 519 break; 520 case DRM_FORMAT_RGB888: 521 pf = PF_RGB888; 522 break; 523 case DRM_FORMAT_BGR888: 524 pf = PF_BGR888; 525 break; 526 case DRM_FORMAT_RGB565: 527 pf = PF_RGB565; 528 break; 529 case DRM_FORMAT_BGR565: 530 pf = PF_BGR565; 531 break; 532 case DRM_FORMAT_ARGB1555: 533 case DRM_FORMAT_XRGB1555: 534 pf = PF_ARGB1555; 535 break; 536 case DRM_FORMAT_ARGB4444: 537 case DRM_FORMAT_XRGB4444: 538 pf = PF_ARGB4444; 539 break; 540 case DRM_FORMAT_C8: 541 pf = PF_L8; 542 break; 543 default: 544 pf = PF_NONE; 545 break; 546 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 547 } 548 549 return pf; 550 } 551 552 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) 553 { 554 struct ltdc_device *ldev = plane_to_ltdc(plane); 555 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; 556 int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos; 557 558 switch (pix_fmt) { 559 case PF_BGR888: 560 psize = 3; 561 alen = 0; apos = 0; rlen = 8; rpos = 0; 562 glen = 8; gpos = 8; blen = 8; bpos = 16; 563 break; 564 case PF_ARGB1555: 565 psize = 2; 566 alen = 1; apos = 15; rlen = 5; rpos = 10; 567 glen = 5; gpos = 5; blen = 5; bpos = 0; 568 break; 569 case PF_ARGB4444: 570 psize = 2; 571 alen = 4; apos = 12; rlen = 4; rpos = 8; 572 glen = 4; gpos = 4; blen = 4; bpos = 0; 573 break; 574 case PF_L8: 575 psize = 1; 576 alen = 0; apos = 0; rlen = 8; rpos = 0; 577 glen = 8; gpos = 0; blen = 8; bpos = 0; 578 break; 579 case PF_AL44: 580 psize = 1; 581 alen = 4; apos = 4; rlen = 4; rpos = 0; 582 glen = 4; gpos = 0; blen = 4; bpos = 0; 583 break; 584 case PF_AL88: 585 psize = 2; 586 alen = 8; apos = 8; rlen = 8; rpos = 0; 587 glen = 8; gpos = 0; blen = 8; bpos = 0; 588 break; 589 default: 590 ret = NB_PF; /* error case, trace msg is handled by the caller */ 591 break; 592 } 593 594 if (ret == PF_FLEXIBLE) { 595 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, 596 (rlen << 14) + (rpos << 9) + (alen << 5) + apos); 597 598 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, 599 (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos); 600 } 601 602 return ret; 603 } 604 605 /* 606 * All non-alpha color formats derived from native alpha color formats are 607 * either characterized by a FourCC format code 608 */ 609 static inline u32 is_xrgb(u32 drm) 610 { 611 return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X'); 612 } 613 614 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) 615 { 616 struct ltdc_device *ldev = plane_to_ltdc(plane); 617 struct drm_plane_state *state = plane->state; 618 u32 lofs = plane->index * LAY_OFS; 619 u32 val; 620 621 switch (drm_pix_fmt) { 622 case DRM_FORMAT_YUYV: 623 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF; 624 break; 625 case DRM_FORMAT_YVYU: 626 val = (YCM_I << 4) | LxPCR_YF; 627 break; 628 case DRM_FORMAT_UYVY: 629 val = (YCM_I << 4) | LxPCR_CBF; 630 break; 631 case DRM_FORMAT_VYUY: 632 val = (YCM_I << 4); 633 break; 634 case DRM_FORMAT_NV12: 635 val = (YCM_SP << 4) | LxPCR_CBF; 636 break; 637 case DRM_FORMAT_NV21: 638 val = (YCM_SP << 4); 639 break; 640 case DRM_FORMAT_YUV420: 641 case DRM_FORMAT_YVU420: 642 val = (YCM_FP << 4); 643 break; 644 default: 645 /* RGB or not a YCbCr supported format */ 646 drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt); 647 return; 648 } 649 650 /* Enable limited range */ 651 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) 652 val |= LxPCR_YREN; 653 654 /* enable ycbcr conversion */ 655 val |= LxPCR_YCEN; 656 657 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); 658 } 659 660 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) 661 { 662 struct ltdc_device *ldev = plane_to_ltdc(plane); 663 struct drm_plane_state *state = plane->state; 664 enum drm_color_encoding enc = state->color_encoding; 665 enum drm_color_range ran = state->color_range; 666 u32 lofs = plane->index * LAY_OFS; 667 668 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 669 drm_err(plane->dev, "color encoding %d not supported, use bt601 by default\n", enc); 670 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 671 enc = DRM_COLOR_YCBCR_BT601; 672 } 673 674 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 675 drm_err(plane->dev, 676 "color range %d not supported, use limited range by default\n", ran); 677 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 678 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 679 } 680 681 drm_err(plane->dev, "Color encoding=%d, range=%d\n", enc, ran); 682 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 683 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 684 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, 685 ltdc_ycbcr2rgb_coeffs[enc][ran][1]); 686 } 687 688 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev, 689 struct drm_crtc *crtc) 690 { 691 u32 crc; 692 int ret; 693 694 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { 695 ldev->crc_skip_count++; 696 return; 697 } 698 699 /* Get the CRC of the frame */ 700 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); 701 if (ret) 702 return; 703 704 /* Report to DRM the CRC (hw dependent feature) */ 705 drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc); 706 } 707 708 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 709 { 710 struct drm_device *ddev = arg; 711 struct ltdc_device *ldev = ddev->dev_private; 712 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 713 714 /* Line IRQ : trigger the vblank event */ 715 if (ldev->irq_status & ISR_LIF) { 716 drm_crtc_handle_vblank(crtc); 717 718 /* Early return if CRC is not active */ 719 if (ldev->crc_active) 720 ltdc_irq_crc_handle(ldev, crtc); 721 } 722 723 mutex_lock(&ldev->err_lock); 724 if (ldev->irq_status & ISR_TERRIF) 725 ldev->transfer_err++; 726 if (ldev->irq_status & ISR_FUEIF) 727 ldev->fifo_err++; 728 if (ldev->irq_status & ISR_FUWIF) 729 ldev->fifo_warn++; 730 mutex_unlock(&ldev->err_lock); 731 732 return IRQ_HANDLED; 733 } 734 735 static irqreturn_t ltdc_irq(int irq, void *arg) 736 { 737 struct drm_device *ddev = arg; 738 struct ltdc_device *ldev = ddev->dev_private; 739 740 /* 741 * Read & Clear the interrupt status 742 * In order to write / read registers in this critical section 743 * very quickly, the regmap functions are not used. 744 */ 745 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); 746 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); 747 748 return IRQ_WAKE_THREAD; 749 } 750 751 /* 752 * DRM_CRTC 753 */ 754 755 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 756 { 757 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 758 struct drm_color_lut *lut; 759 u32 val; 760 int i; 761 762 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 763 return; 764 765 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 766 767 for (i = 0; i < CLUT_SIZE; i++, lut++) { 768 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 769 (lut->blue >> 8) | (i << 24); 770 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); 771 } 772 } 773 774 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 775 struct drm_atomic_state *state) 776 { 777 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 778 struct drm_device *ddev = crtc->dev; 779 780 drm_dbg_driver(crtc->dev, "\n"); 781 782 pm_runtime_get_sync(ddev->dev); 783 784 /* Sets the background color value */ 785 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); 786 787 /* Enable IRQ */ 788 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 789 790 /* Commit shadow registers = update planes at next vblank */ 791 if (!ldev->caps.plane_reg_shadow) 792 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 793 794 drm_crtc_vblank_on(crtc); 795 } 796 797 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 798 struct drm_atomic_state *state) 799 { 800 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 801 struct drm_device *ddev = crtc->dev; 802 int layer_index = 0; 803 804 drm_dbg_driver(crtc->dev, "\n"); 805 806 drm_crtc_vblank_off(crtc); 807 808 /* Disable all layers */ 809 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) 810 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, LXCR_MASK, 0); 811 812 /* Disable IRQ */ 813 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 814 815 /* immediately commit disable of layers before switching off LTDC */ 816 if (!ldev->caps.plane_reg_shadow) 817 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); 818 819 pm_runtime_put_sync(ddev->dev); 820 821 /* clear interrupt error counters */ 822 mutex_lock(&ldev->err_lock); 823 ldev->transfer_err = 0; 824 ldev->fifo_err = 0; 825 ldev->fifo_warn = 0; 826 mutex_unlock(&ldev->err_lock); 827 } 828 829 #define CLK_TOLERANCE_HZ 50 830 831 static enum drm_mode_status 832 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 833 const struct drm_display_mode *mode) 834 { 835 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 836 int target = mode->clock * 1000; 837 int target_min = target - CLK_TOLERANCE_HZ; 838 int target_max = target + CLK_TOLERANCE_HZ; 839 int result; 840 841 if (ldev->lvds_clk) { 842 result = clk_round_rate(ldev->lvds_clk, target); 843 drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", 844 target, result); 845 } 846 847 result = clk_round_rate(ldev->pixel_clk, target); 848 849 drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, result); 850 851 /* Filter modes according to the max frequency supported by the pads */ 852 if (result > ldev->caps.pad_max_freq_hz) 853 return MODE_CLOCK_HIGH; 854 855 /* 856 * Accept all "preferred" modes: 857 * - this is important for panels because panel clock tolerances are 858 * bigger than hdmi ones and there is no reason to not accept them 859 * (the fps may vary a little but it is not a problem). 860 * - the hdmi preferred mode will be accepted too, but userland will 861 * be able to use others hdmi "valid" modes if necessary. 862 */ 863 if (mode->type & DRM_MODE_TYPE_PREFERRED) 864 return MODE_OK; 865 866 /* 867 * Filter modes according to the clock value, particularly useful for 868 * hdmi modes that require precise pixel clocks. 869 */ 870 if (result < target_min || result > target_max) 871 return MODE_CLOCK_RANGE; 872 873 return MODE_OK; 874 } 875 876 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 877 const struct drm_display_mode *mode, 878 struct drm_display_mode *adjusted_mode) 879 { 880 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 881 int rate = mode->clock * 1000; 882 883 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 884 drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate); 885 return false; 886 } 887 888 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 889 890 drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n", 891 mode->clock, adjusted_mode->clock); 892 893 return true; 894 } 895 896 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 897 { 898 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 899 struct drm_device *ddev = crtc->dev; 900 struct drm_connector_list_iter iter; 901 struct drm_connector *connector = NULL; 902 struct drm_encoder *encoder = NULL, *en_iter; 903 struct drm_bridge *bridge = NULL, *br_iter; 904 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 905 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 906 u32 total_width, total_height; 907 u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24; 908 u32 bus_flags = 0; 909 u32 val; 910 int ret; 911 912 /* get encoder from crtc */ 913 drm_for_each_encoder(en_iter, ddev) 914 if (en_iter->crtc == crtc) { 915 encoder = en_iter; 916 break; 917 } 918 919 if (encoder) { 920 /* get bridge from encoder */ 921 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) 922 if (br_iter->encoder == encoder) { 923 bridge = br_iter; 924 break; 925 } 926 927 /* Get the connector from encoder */ 928 drm_connector_list_iter_begin(ddev, &iter); 929 drm_for_each_connector_iter(connector, &iter) 930 if (connector->encoder == encoder) 931 break; 932 drm_connector_list_iter_end(&iter); 933 } 934 935 if (bridge && bridge->timings) { 936 bus_flags = bridge->timings->input_bus_flags; 937 } else if (connector) { 938 bus_flags = connector->display_info.bus_flags; 939 if (connector->display_info.num_bus_formats) 940 bus_formats = connector->display_info.bus_formats[0]; 941 } 942 943 if (!pm_runtime_active(ddev->dev)) { 944 ret = pm_runtime_get_sync(ddev->dev); 945 if (ret) { 946 drm_err(crtc->dev, "Failed to set mode, cannot get sync\n"); 947 return; 948 } 949 } 950 951 drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name); 952 drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 953 drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 954 mode->hsync_start - mode->hdisplay, 955 mode->htotal - mode->hsync_end, 956 mode->hsync_end - mode->hsync_start, 957 mode->vsync_start - mode->vdisplay, 958 mode->vtotal - mode->vsync_end, 959 mode->vsync_end - mode->vsync_start); 960 961 /* Convert video timings to ltdc timings */ 962 hsync = mode->hsync_end - mode->hsync_start - 1; 963 vsync = mode->vsync_end - mode->vsync_start - 1; 964 accum_hbp = mode->htotal - mode->hsync_start - 1; 965 accum_vbp = mode->vtotal - mode->vsync_start - 1; 966 accum_act_w = accum_hbp + mode->hdisplay; 967 accum_act_h = accum_vbp + mode->vdisplay; 968 total_width = mode->htotal - 1; 969 total_height = mode->vtotal - 1; 970 971 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 972 val = 0; 973 974 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 975 val |= GCR_HSPOL; 976 977 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 978 val |= GCR_VSPOL; 979 980 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 981 val |= GCR_DEPOL; 982 983 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 984 val |= GCR_PCPOL; 985 986 regmap_update_bits(ldev->regmap, LTDC_GCR, 987 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 988 989 /* Set Synchronization size */ 990 val = (hsync << 16) | vsync; 991 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 992 993 /* Set Accumulated Back porch */ 994 val = (accum_hbp << 16) | accum_vbp; 995 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 996 997 /* Set Accumulated Active Width */ 998 val = (accum_act_w << 16) | accum_act_h; 999 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 1000 1001 /* Set total width & height */ 1002 val = (total_width << 16) | total_height; 1003 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 1004 1005 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); 1006 1007 /* Configure the output format (hw version dependent) */ 1008 if (ldev->caps.ycbcr_output) { 1009 /* Input video dynamic_range & colorimetry */ 1010 int vic = drm_match_cea_mode(mode); 1011 u32 val; 1012 1013 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 1014 vic == 2 || vic == 3 || vic == 17 || vic == 18) 1015 /* ITU-R BT.601 */ 1016 val = 0; 1017 else 1018 /* ITU-R BT.709 */ 1019 val = EDCR_OCYSEL; 1020 1021 switch (bus_formats) { 1022 case MEDIA_BUS_FMT_YUYV8_1X16: 1023 /* enable ycbcr output converter */ 1024 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); 1025 break; 1026 case MEDIA_BUS_FMT_YVYU8_1X16: 1027 /* enable ycbcr output converter & invert chrominance order */ 1028 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); 1029 break; 1030 default: 1031 /* disable ycbcr output converter */ 1032 regmap_write(ldev->regmap, LTDC_EDCR, 0); 1033 break; 1034 } 1035 } 1036 } 1037 1038 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 1039 struct drm_atomic_state *state) 1040 { 1041 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1042 struct drm_device *ddev = crtc->dev; 1043 struct drm_pending_vblank_event *event = crtc->state->event; 1044 1045 drm_dbg_atomic(crtc->dev, "\n"); 1046 1047 ltdc_crtc_update_clut(crtc); 1048 1049 /* Commit shadow registers = update planes at next vblank */ 1050 if (!ldev->caps.plane_reg_shadow) 1051 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 1052 1053 if (event) { 1054 crtc->state->event = NULL; 1055 1056 spin_lock_irq(&ddev->event_lock); 1057 if (drm_crtc_vblank_get(crtc) == 0) 1058 drm_crtc_arm_vblank_event(crtc, event); 1059 else 1060 drm_crtc_send_vblank_event(crtc, event); 1061 spin_unlock_irq(&ddev->event_lock); 1062 } 1063 } 1064 1065 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 1066 bool in_vblank_irq, 1067 int *vpos, int *hpos, 1068 ktime_t *stime, ktime_t *etime, 1069 const struct drm_display_mode *mode) 1070 { 1071 struct drm_device *ddev = crtc->dev; 1072 struct ltdc_device *ldev = ddev->dev_private; 1073 int line, vactive_start, vactive_end, vtotal; 1074 1075 if (stime) 1076 *stime = ktime_get(); 1077 1078 /* The active area starts after vsync + front porch and ends 1079 * at vsync + front porc + display size. 1080 * The total height also include back porch. 1081 * We have 3 possible cases to handle: 1082 * - line < vactive_start: vpos = line - vactive_start and will be 1083 * negative 1084 * - vactive_start < line < vactive_end: vpos = line - vactive_start 1085 * and will be positive 1086 * - line > vactive_end: vpos = line - vtotal - vactive_start 1087 * and will negative 1088 * 1089 * Computation for the two first cases are identical so we can 1090 * simplify the code and only test if line > vactive_end 1091 */ 1092 if (pm_runtime_active(ddev->dev)) { 1093 regmap_read(ldev->regmap, LTDC_CPSR, &line); 1094 line &= CPSR_CYPOS; 1095 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); 1096 vactive_start &= BPCR_AVBP; 1097 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); 1098 vactive_end &= AWCR_AAH; 1099 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); 1100 vtotal &= TWCR_TOTALH; 1101 1102 if (line > vactive_end) 1103 *vpos = line - vtotal - vactive_start; 1104 else 1105 *vpos = line - vactive_start; 1106 } else { 1107 *vpos = 0; 1108 } 1109 1110 *hpos = 0; 1111 1112 if (etime) 1113 *etime = ktime_get(); 1114 1115 return true; 1116 } 1117 1118 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 1119 .mode_valid = ltdc_crtc_mode_valid, 1120 .mode_fixup = ltdc_crtc_mode_fixup, 1121 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 1122 .atomic_flush = ltdc_crtc_atomic_flush, 1123 .atomic_enable = ltdc_crtc_atomic_enable, 1124 .atomic_disable = ltdc_crtc_atomic_disable, 1125 .get_scanout_position = ltdc_crtc_get_scanout_position, 1126 }; 1127 1128 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 1129 { 1130 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1131 struct drm_crtc_state *state = crtc->state; 1132 1133 drm_dbg_driver(crtc->dev, "\n"); 1134 1135 if (state->enable) 1136 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); 1137 else 1138 return -EPERM; 1139 1140 return 0; 1141 } 1142 1143 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 1144 { 1145 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1146 1147 drm_dbg_driver(crtc->dev, "\n"); 1148 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1149 } 1150 1151 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source) 1152 { 1153 struct ltdc_device *ldev; 1154 int ret; 1155 1156 if (!crtc) 1157 return -ENODEV; 1158 1159 drm_dbg_driver(crtc->dev, "\n"); 1160 1161 ldev = crtc_to_ltdc(crtc); 1162 1163 if (source && strcmp(source, "auto") == 0) { 1164 ldev->crc_active = true; 1165 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1166 } else if (!source) { 1167 ldev->crc_active = false; 1168 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1169 } else { 1170 ret = -EINVAL; 1171 } 1172 1173 ldev->crc_skip_count = 0; 1174 return ret; 1175 } 1176 1177 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, 1178 const char *source, size_t *values_cnt) 1179 { 1180 if (!crtc) 1181 return -ENODEV; 1182 1183 drm_dbg_driver(crtc->dev, "\n"); 1184 1185 if (source && strcmp(source, "auto") != 0) { 1186 drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n", 1187 source, crtc->name); 1188 return -EINVAL; 1189 } 1190 1191 *values_cnt = 1; 1192 return 0; 1193 } 1194 1195 static void ltdc_crtc_atomic_print_state(struct drm_printer *p, 1196 const struct drm_crtc_state *state) 1197 { 1198 struct drm_crtc *crtc = state->crtc; 1199 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1200 1201 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); 1202 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); 1203 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); 1204 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); 1205 } 1206 1207 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 1208 .set_config = drm_atomic_helper_set_config, 1209 .page_flip = drm_atomic_helper_page_flip, 1210 .reset = drm_atomic_helper_crtc_reset, 1211 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1212 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1213 .enable_vblank = ltdc_crtc_enable_vblank, 1214 .disable_vblank = ltdc_crtc_disable_vblank, 1215 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1216 .atomic_print_state = ltdc_crtc_atomic_print_state, 1217 }; 1218 1219 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { 1220 .set_config = drm_atomic_helper_set_config, 1221 .page_flip = drm_atomic_helper_page_flip, 1222 .reset = drm_atomic_helper_crtc_reset, 1223 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1224 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1225 .enable_vblank = ltdc_crtc_enable_vblank, 1226 .disable_vblank = ltdc_crtc_disable_vblank, 1227 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1228 .set_crc_source = ltdc_crtc_set_crc_source, 1229 .verify_crc_source = ltdc_crtc_verify_crc_source, 1230 .atomic_print_state = ltdc_crtc_atomic_print_state, 1231 }; 1232 1233 /* 1234 * DRM_PLANE 1235 */ 1236 1237 static int ltdc_plane_atomic_check(struct drm_plane *plane, 1238 struct drm_atomic_state *state) 1239 { 1240 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1241 plane); 1242 struct drm_framebuffer *fb = new_plane_state->fb; 1243 u32 src_w, src_h; 1244 1245 drm_dbg_driver(plane->dev, "\n"); 1246 1247 if (!fb) 1248 return 0; 1249 1250 /* convert src_ from 16:16 format */ 1251 src_w = new_plane_state->src_w >> 16; 1252 src_h = new_plane_state->src_h >> 16; 1253 1254 /* Reject scaling */ 1255 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1256 drm_dbg_driver(plane->dev, "Scaling is not supported"); 1257 1258 return -EINVAL; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static void ltdc_plane_atomic_update(struct drm_plane *plane, 1265 struct drm_atomic_state *state) 1266 { 1267 struct ltdc_device *ldev = plane_to_ltdc(plane); 1268 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 1269 plane); 1270 struct drm_framebuffer *fb = newstate->fb; 1271 u32 lofs = plane->index * LAY_OFS; 1272 u32 x0 = newstate->crtc_x; 1273 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 1274 u32 y0 = newstate->crtc_y; 1275 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 1276 u32 src_x, src_y, src_w, src_h; 1277 u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr; 1278 u32 paddr, paddr1, paddr2; 1279 enum ltdc_pix_fmt pf; 1280 1281 if (!newstate->crtc || !fb) { 1282 drm_dbg_driver(plane->dev, "fb or crtc NULL"); 1283 return; 1284 } 1285 1286 /* convert src_ from 16:16 format */ 1287 src_x = newstate->src_x >> 16; 1288 src_y = newstate->src_y >> 16; 1289 src_w = newstate->src_w >> 16; 1290 src_h = newstate->src_h >> 16; 1291 1292 drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1293 plane->base.id, fb->base.id, 1294 src_w, src_h, src_x, src_y, 1295 newstate->crtc_w, newstate->crtc_h, 1296 newstate->crtc_x, newstate->crtc_y); 1297 1298 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1299 1300 ahbp = (bpcr & BPCR_AHBP) >> 16; 1301 avbp = bpcr & BPCR_AVBP; 1302 1303 /* Configures the horizontal start and stop position */ 1304 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 1305 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, 1306 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 1307 1308 /* Configures the vertical start and stop position */ 1309 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 1310 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, 1311 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 1312 1313 /* Specifies the pixel format */ 1314 pf = to_ltdc_pixelformat(fb->format->format); 1315 for (val = 0; val < NB_PF; val++) 1316 if (ldev->caps.pix_fmt_hw[val] == pf) 1317 break; 1318 1319 /* Use the flexible color format feature if necessary and available */ 1320 if (ldev->caps.pix_fmt_flex && val == NB_PF) 1321 val = ltdc_set_flexible_pixel_format(plane, pf); 1322 1323 if (val == NB_PF) { 1324 drm_err(fb->dev, "Pixel format %.4s not supported\n", 1325 (char *)&fb->format->format); 1326 val = 0; /* set by default ARGB 32 bits */ 1327 } 1328 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 1329 1330 /* Specifies the constant alpha value */ 1331 val = newstate->alpha >> 8; 1332 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 1333 1334 /* Specifies the blending factors */ 1335 val = BF1_PAXCA | BF2_1PAXCA; 1336 if (!fb->format->has_alpha) 1337 val = BF1_CA | BF2_1CA; 1338 1339 /* Manage hw-specific capabilities */ 1340 if (ldev->caps.non_alpha_only_l1 && 1341 plane->type != DRM_PLANE_TYPE_PRIMARY) 1342 val = BF1_PAXCA | BF2_1PAXCA; 1343 1344 if (ldev->caps.dynamic_zorder) { 1345 val |= (newstate->normalized_zpos << 16); 1346 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1347 LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val); 1348 } else { 1349 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1350 LXBFCR_BF2 | LXBFCR_BF1, val); 1351 } 1352 1353 /* Sets the FB address */ 1354 paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0); 1355 1356 if (newstate->rotation & DRM_MODE_REFLECT_X) 1357 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; 1358 1359 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1360 paddr += (fb->pitches[0] * (y1 - y0)); 1361 1362 drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr); 1363 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1364 1365 /* Configures the color frame buffer pitch in bytes & line length */ 1366 line_length = fb->format->cpp[0] * 1367 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 1368 1369 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1370 /* Compute negative value (signed on 16 bits) for the picth */ 1371 pitch_in_bytes = 0x10000 - fb->pitches[0]; 1372 else 1373 pitch_in_bytes = fb->pitches[0]; 1374 1375 val = (pitch_in_bytes << 16) | line_length; 1376 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 1377 1378 /* Configures the frame buffer line number */ 1379 line_number = y1 - y0 + 1; 1380 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); 1381 1382 if (ldev->caps.ycbcr_input) { 1383 if (fb->format->is_yuv) { 1384 switch (fb->format->format) { 1385 case DRM_FORMAT_NV12: 1386 case DRM_FORMAT_NV21: 1387 /* Configure the auxiliary frame buffer address 0 */ 1388 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1389 1390 if (newstate->rotation & DRM_MODE_REFLECT_X) 1391 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1392 1393 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1394 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1395 1396 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1397 break; 1398 case DRM_FORMAT_YUV420: 1399 /* Configure the auxiliary frame buffer address 0 & 1 */ 1400 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1401 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1402 1403 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1404 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1405 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1406 } 1407 1408 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1409 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1410 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1411 } 1412 1413 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1414 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1415 break; 1416 case DRM_FORMAT_YVU420: 1417 /* Configure the auxiliary frame buffer address 0 & 1 */ 1418 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1419 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1420 1421 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1422 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1423 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1424 } 1425 1426 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1427 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1428 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1429 } 1430 1431 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1432 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1433 break; 1434 } 1435 1436 /* 1437 * Set the length and the number of lines of the auxiliary 1438 * buffers if the framebuffer contains more than one plane. 1439 */ 1440 if (fb->format->num_planes > 1) { 1441 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1442 /* 1443 * Compute negative value (signed on 16 bits) 1444 * for the picth 1445 */ 1446 pitch_in_bytes = 0x10000 - fb->pitches[1]; 1447 else 1448 pitch_in_bytes = fb->pitches[1]; 1449 1450 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + 1451 (ldev->caps.bus_width >> 3) - 1; 1452 1453 /* Configure the auxiliary buffer length */ 1454 val = (pitch_in_bytes << 16) | line_length; 1455 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1456 1457 /* Configure the auxiliary frame buffer line number */ 1458 val = line_number >> 1; 1459 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1460 } 1461 1462 /* Configure YCbC conversion coefficient */ 1463 ltdc_set_ycbcr_coeffs(plane); 1464 1465 /* Configure YCbCr format and enable/disable conversion */ 1466 ltdc_set_ycbcr_config(plane, fb->format->format); 1467 } else { 1468 /* disable ycbcr conversion */ 1469 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); 1470 } 1471 } 1472 1473 /* Enable layer and CLUT if needed */ 1474 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 1475 val |= LXCR_LEN; 1476 1477 /* Enable horizontal mirroring if requested */ 1478 if (newstate->rotation & DRM_MODE_REFLECT_X) 1479 val |= LXCR_HMEN; 1480 1481 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, val); 1482 1483 /* Commit shadow registers = update plane at next vblank */ 1484 if (ldev->caps.plane_reg_shadow) 1485 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1486 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1487 1488 ldev->plane_fpsi[plane->index].counter++; 1489 1490 mutex_lock(&ldev->err_lock); 1491 if (ldev->transfer_err) { 1492 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); 1493 ldev->transfer_err = 0; 1494 } 1495 1496 if (ldev->caps.fifo_threshold) { 1497 if (ldev->fifo_err) { 1498 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1499 ldev->fifo_err = 0; 1500 } 1501 } else { 1502 if (ldev->fifo_warn >= ldev->fifo_threshold) { 1503 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1504 ldev->fifo_warn = 0; 1505 } 1506 } 1507 mutex_unlock(&ldev->err_lock); 1508 } 1509 1510 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 1511 struct drm_atomic_state *state) 1512 { 1513 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 1514 plane); 1515 struct ltdc_device *ldev = plane_to_ltdc(plane); 1516 u32 lofs = plane->index * LAY_OFS; 1517 1518 /* Disable layer */ 1519 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, 0); 1520 1521 /* Reset the layer transparency to hide any related background color */ 1522 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00); 1523 1524 /* Commit shadow registers = update plane at next vblank */ 1525 if (ldev->caps.plane_reg_shadow) 1526 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1527 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1528 1529 drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n", 1530 oldstate->crtc->base.id, plane->base.id); 1531 } 1532 1533 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 1534 const struct drm_plane_state *state) 1535 { 1536 struct drm_plane *plane = state->plane; 1537 struct ltdc_device *ldev = plane_to_ltdc(plane); 1538 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 1539 int ms_since_last; 1540 ktime_t now; 1541 1542 now = ktime_get(); 1543 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 1544 1545 drm_printf(p, "\tuser_updates=%dfps\n", 1546 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 1547 1548 fpsi->last_timestamp = now; 1549 fpsi->counter = 0; 1550 } 1551 1552 static const struct drm_plane_funcs ltdc_plane_funcs = { 1553 .update_plane = drm_atomic_helper_update_plane, 1554 .disable_plane = drm_atomic_helper_disable_plane, 1555 .reset = drm_atomic_helper_plane_reset, 1556 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1557 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1558 .atomic_print_state = ltdc_plane_atomic_print_state, 1559 }; 1560 1561 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 1562 .atomic_check = ltdc_plane_atomic_check, 1563 .atomic_update = ltdc_plane_atomic_update, 1564 .atomic_disable = ltdc_plane_atomic_disable, 1565 }; 1566 1567 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 1568 enum drm_plane_type type, 1569 int index) 1570 { 1571 unsigned long possible_crtcs = CRTC_MASK; 1572 struct ltdc_device *ldev = ddev->dev_private; 1573 struct device *dev = ddev->dev; 1574 struct drm_plane *plane; 1575 unsigned int i, nb_fmt = 0; 1576 u32 *formats; 1577 u32 drm_fmt; 1578 const u64 *modifiers = ltdc_format_modifiers; 1579 u32 lofs = index * LAY_OFS; 1580 u32 val; 1581 1582 /* Allocate the biggest size according to supported color formats */ 1583 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + 1584 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) + 1585 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) + 1586 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) * 1587 sizeof(*formats), GFP_KERNEL); 1588 if (!formats) 1589 return NULL; 1590 1591 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { 1592 drm_fmt = ldev->caps.pix_fmt_drm[i]; 1593 1594 /* Manage hw-specific capabilities */ 1595 if (ldev->caps.non_alpha_only_l1) 1596 /* XR24 & RX24 like formats supported only on primary layer */ 1597 if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt)) 1598 continue; 1599 1600 formats[nb_fmt++] = drm_fmt; 1601 } 1602 1603 /* Add YCbCr supported pixel formats */ 1604 if (ldev->caps.ycbcr_input) { 1605 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); 1606 if (val & LXCR_C1R_YIA) { 1607 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp, 1608 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats)); 1609 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp); 1610 } 1611 if (val & LXCR_C1R_YSPA) { 1612 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp, 1613 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats)); 1614 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp); 1615 } 1616 if (val & LXCR_C1R_YFPA) { 1617 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp, 1618 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats)); 1619 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp); 1620 } 1621 } 1622 1623 plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev, 1624 possible_crtcs, <dc_plane_funcs, formats, 1625 nb_fmt, modifiers, type, NULL); 1626 if (IS_ERR(plane)) 1627 return NULL; 1628 1629 if (ldev->caps.ycbcr_input) { 1630 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA)) 1631 drm_plane_create_color_properties(plane, 1632 BIT(DRM_COLOR_YCBCR_BT601) | 1633 BIT(DRM_COLOR_YCBCR_BT709), 1634 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1635 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1636 DRM_COLOR_YCBCR_BT601, 1637 DRM_COLOR_YCBCR_LIMITED_RANGE); 1638 } 1639 1640 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 1641 1642 drm_plane_create_alpha_property(plane); 1643 1644 drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id); 1645 1646 return plane; 1647 } 1648 1649 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1650 { 1651 struct ltdc_device *ldev = ddev->dev_private; 1652 struct drm_plane *primary, *overlay; 1653 int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 1654 unsigned int i; 1655 int ret; 1656 1657 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1658 if (!primary) { 1659 drm_err(ddev, "Can not create primary plane\n"); 1660 return -EINVAL; 1661 } 1662 1663 if (ldev->caps.dynamic_zorder) 1664 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); 1665 else 1666 drm_plane_create_zpos_immutable_property(primary, 0); 1667 1668 if (ldev->caps.plane_rotation) 1669 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, 1670 supported_rotations); 1671 1672 /* Init CRTC according to its hardware features */ 1673 if (ldev->caps.crc) 1674 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1675 <dc_crtc_with_crc_support_funcs, NULL); 1676 else 1677 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1678 <dc_crtc_funcs, NULL); 1679 if (ret) { 1680 drm_err(ddev, "Can not initialize CRTC\n"); 1681 return ret; 1682 } 1683 1684 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1685 1686 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1687 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1688 1689 drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id); 1690 1691 /* Add planes. Note : the first layer is used by primary plane */ 1692 for (i = 1; i < ldev->caps.nb_layers; i++) { 1693 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1694 if (!overlay) { 1695 drm_err(ddev, "Can not create overlay plane %d\n", i); 1696 return -ENOMEM; 1697 } 1698 if (ldev->caps.dynamic_zorder) 1699 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); 1700 else 1701 drm_plane_create_zpos_immutable_property(overlay, i); 1702 1703 if (ldev->caps.plane_rotation) 1704 drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0, 1705 supported_rotations); 1706 } 1707 1708 return 0; 1709 } 1710 1711 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1712 { 1713 struct drm_device *ddev = encoder->dev; 1714 struct ltdc_device *ldev = ddev->dev_private; 1715 1716 drm_dbg_driver(encoder->dev, "\n"); 1717 1718 /* Disable LTDC */ 1719 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1720 1721 /* Set to sleep state the pinctrl whatever type of encoder */ 1722 pinctrl_pm_select_sleep_state(ddev->dev); 1723 } 1724 1725 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1726 { 1727 struct drm_device *ddev = encoder->dev; 1728 struct ltdc_device *ldev = ddev->dev_private; 1729 1730 drm_dbg_driver(encoder->dev, "\n"); 1731 1732 /* set fifo underrun threshold register */ 1733 if (ldev->caps.fifo_threshold) 1734 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); 1735 1736 /* Enable LTDC */ 1737 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1738 } 1739 1740 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1741 struct drm_display_mode *mode, 1742 struct drm_display_mode *adjusted_mode) 1743 { 1744 struct drm_device *ddev = encoder->dev; 1745 1746 drm_dbg_driver(encoder->dev, "\n"); 1747 1748 /* 1749 * Set to default state the pinctrl only with DPI type. 1750 * Others types like DSI, don't need pinctrl due to 1751 * internal bridge (the signals do not come out of the chipset). 1752 */ 1753 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1754 pinctrl_pm_select_default_state(ddev->dev); 1755 } 1756 1757 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1758 .disable = ltdc_encoder_disable, 1759 .enable = ltdc_encoder_enable, 1760 .mode_set = ltdc_encoder_mode_set, 1761 }; 1762 1763 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1764 { 1765 struct drm_encoder *encoder; 1766 int ret; 1767 1768 encoder = drmm_simple_encoder_alloc(ddev, struct drm_encoder, dev, 1769 DRM_MODE_ENCODER_DPI); 1770 if (IS_ERR(encoder)) 1771 return PTR_ERR(encoder); 1772 1773 encoder->possible_crtcs = CRTC_MASK; 1774 encoder->possible_clones = 0; /* No cloning support */ 1775 1776 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1777 1778 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1779 if (ret) 1780 return ret; 1781 1782 drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base.id); 1783 1784 return 0; 1785 } 1786 1787 static int ltdc_get_caps(struct drm_device *ddev) 1788 { 1789 struct ltdc_device *ldev = ddev->dev_private; 1790 u32 bus_width_log2, lcr, gc2r; 1791 const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev); 1792 1793 /* 1794 * at least 1 layer must be managed & the number of layers 1795 * must not exceed LTDC_MAX_LAYER 1796 */ 1797 regmap_read(ldev->regmap, LTDC_LCR, &lcr); 1798 1799 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1800 1801 /* set data bus width */ 1802 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); 1803 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1804 ldev->caps.bus_width = 8 << bus_width_log2; 1805 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); 1806 1807 ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz; 1808 1809 switch (ldev->caps.hw_version) { 1810 case HWVER_10200: 1811 case HWVER_10300: 1812 ldev->caps.layer_ofs = LAY_OFS_0; 1813 ldev->caps.layer_regs = ltdc_layer_regs_a0; 1814 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1815 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; 1816 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); 1817 ldev->caps.pix_fmt_flex = false; 1818 /* 1819 * Hw older versions support non-alpha color formats derived 1820 * from native alpha color formats only on the primary layer. 1821 * For instance, RG16 native format without alpha works fine 1822 * on 2nd layer but XR24 (derived color format from AR24) 1823 * does not work on 2nd layer. 1824 */ 1825 ldev->caps.non_alpha_only_l1 = true; 1826 if (ldev->caps.hw_version == HWVER_10200) 1827 ldev->caps.pad_max_freq_hz = 65000000; 1828 ldev->caps.nb_irq = 2; 1829 ldev->caps.ycbcr_input = false; 1830 ldev->caps.ycbcr_output = false; 1831 ldev->caps.plane_reg_shadow = false; 1832 ldev->caps.crc = false; 1833 ldev->caps.dynamic_zorder = false; 1834 ldev->caps.plane_rotation = false; 1835 ldev->caps.fifo_threshold = false; 1836 break; 1837 case HWVER_20101: 1838 ldev->caps.layer_ofs = LAY_OFS_0; 1839 ldev->caps.layer_regs = ltdc_layer_regs_a1; 1840 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1841 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; 1842 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); 1843 ldev->caps.pix_fmt_flex = false; 1844 ldev->caps.non_alpha_only_l1 = false; 1845 ldev->caps.pad_max_freq_hz = 150000000; 1846 ldev->caps.nb_irq = 4; 1847 ldev->caps.ycbcr_input = false; 1848 ldev->caps.ycbcr_output = false; 1849 ldev->caps.plane_reg_shadow = false; 1850 ldev->caps.crc = false; 1851 ldev->caps.dynamic_zorder = false; 1852 ldev->caps.plane_rotation = false; 1853 ldev->caps.fifo_threshold = false; 1854 break; 1855 case HWVER_40100: 1856 case HWVER_40101: 1857 ldev->caps.layer_ofs = LAY_OFS_1; 1858 ldev->caps.layer_regs = ltdc_layer_regs_a2; 1859 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; 1860 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; 1861 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); 1862 ldev->caps.pix_fmt_flex = true; 1863 ldev->caps.non_alpha_only_l1 = false; 1864 ldev->caps.nb_irq = 2; 1865 ldev->caps.ycbcr_input = true; 1866 ldev->caps.ycbcr_output = true; 1867 ldev->caps.plane_reg_shadow = true; 1868 ldev->caps.crc = true; 1869 ldev->caps.dynamic_zorder = true; 1870 ldev->caps.plane_rotation = true; 1871 ldev->caps.fifo_threshold = true; 1872 break; 1873 default: 1874 return -ENODEV; 1875 } 1876 1877 return 0; 1878 } 1879 1880 void ltdc_suspend(struct drm_device *ddev) 1881 { 1882 struct ltdc_device *ldev = ddev->dev_private; 1883 1884 drm_dbg_driver(ddev, "\n"); 1885 clk_disable_unprepare(ldev->pixel_clk); 1886 if (ldev->bus_clk) 1887 clk_disable_unprepare(ldev->bus_clk); 1888 if (ldev->lvds_clk) 1889 clk_disable_unprepare(ldev->lvds_clk); 1890 } 1891 1892 int ltdc_resume(struct drm_device *ddev) 1893 { 1894 struct ltdc_device *ldev = ddev->dev_private; 1895 int ret; 1896 1897 drm_dbg_driver(ddev, "\n"); 1898 1899 ret = clk_prepare_enable(ldev->pixel_clk); 1900 if (ret) { 1901 drm_err(ddev, "failed to enable pixel clock (%d)\n", ret); 1902 return ret; 1903 } 1904 1905 if (ldev->bus_clk) { 1906 ret = clk_prepare_enable(ldev->bus_clk); 1907 if (ret) { 1908 drm_err(ddev, "failed to enable bus clock (%d)\n", ret); 1909 return ret; 1910 } 1911 } 1912 1913 if (ldev->lvds_clk) { 1914 ret = clk_prepare_enable(ldev->lvds_clk); 1915 if (ret) 1916 drm_err(ddev, "failed to prepare lvds clock\n"); 1917 } 1918 1919 return ret; 1920 } 1921 1922 int ltdc_load(struct drm_device *ddev) 1923 { 1924 struct platform_device *pdev = to_platform_device(ddev->dev); 1925 struct ltdc_device *ldev = ddev->dev_private; 1926 struct device *dev = ddev->dev; 1927 struct device_node *np = dev->of_node; 1928 struct drm_bridge *bridge; 1929 struct drm_panel *panel; 1930 struct drm_crtc *crtc; 1931 struct reset_control *rstc; 1932 int irq, i, nb_endpoints; 1933 int ret = -ENODEV; 1934 1935 drm_dbg_driver(ddev, "\n"); 1936 1937 /* Get number of endpoints */ 1938 nb_endpoints = of_graph_get_endpoint_count(np); 1939 if (!nb_endpoints) 1940 return -ENODEV; 1941 1942 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1943 if (IS_ERR(ldev->pixel_clk)) { 1944 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1945 drm_err(ddev, "Unable to get lcd clock\n"); 1946 return PTR_ERR(ldev->pixel_clk); 1947 } 1948 1949 if (clk_prepare_enable(ldev->pixel_clk)) { 1950 drm_err(ddev, "Unable to prepare pixel clock\n"); 1951 return -ENODEV; 1952 } 1953 1954 if (of_device_is_compatible(np, "st,stm32mp251-ltdc") || 1955 of_device_is_compatible(np, "st,stm32mp255-ltdc")) { 1956 ldev->bus_clk = devm_clk_get(dev, "bus"); 1957 if (IS_ERR(ldev->bus_clk)) 1958 return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), 1959 "Unable to get bus clock\n"); 1960 1961 ret = clk_prepare_enable(ldev->bus_clk); 1962 if (ret) { 1963 drm_err(ddev, "Unable to prepare bus clock\n"); 1964 return ret; 1965 } 1966 } 1967 1968 /* Get endpoints if any */ 1969 for (i = 0; i < nb_endpoints; i++) { 1970 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1971 1972 /* 1973 * If at least one endpoint is -ENODEV, continue probing, 1974 * else if at least one endpoint returned an error 1975 * (ie -EPROBE_DEFER) then stop probing. 1976 */ 1977 if (ret == -ENODEV) 1978 continue; 1979 else if (ret) 1980 goto err; 1981 1982 if (panel) { 1983 bridge = drmm_panel_bridge_add(ddev, panel); 1984 if (IS_ERR(bridge)) { 1985 drm_err(ddev, "panel-bridge endpoint %d\n", i); 1986 ret = PTR_ERR(bridge); 1987 goto err; 1988 } 1989 } 1990 1991 if (bridge) { 1992 ret = ltdc_encoder_init(ddev, bridge); 1993 if (ret) { 1994 if (ret != -EPROBE_DEFER) 1995 drm_err(ddev, "init encoder endpoint %d\n", i); 1996 goto err; 1997 } 1998 } 1999 } 2000 2001 ldev->lvds_clk = devm_clk_get(dev, "lvds"); 2002 if (IS_ERR(ldev->lvds_clk)) 2003 ldev->lvds_clk = NULL; 2004 2005 rstc = devm_reset_control_get_exclusive(dev, NULL); 2006 2007 mutex_init(&ldev->err_lock); 2008 2009 if (!IS_ERR(rstc)) { 2010 reset_control_assert(rstc); 2011 usleep_range(10, 20); 2012 reset_control_deassert(rstc); 2013 } 2014 2015 ldev->regs = devm_platform_ioremap_resource(pdev, 0); 2016 if (IS_ERR(ldev->regs)) { 2017 drm_err(ddev, "Unable to get ltdc registers\n"); 2018 ret = PTR_ERR(ldev->regs); 2019 goto err; 2020 } 2021 2022 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 2023 if (IS_ERR(ldev->regmap)) { 2024 drm_err(ddev, "Unable to regmap ltdc registers\n"); 2025 ret = PTR_ERR(ldev->regmap); 2026 goto err; 2027 } 2028 2029 ret = ltdc_get_caps(ddev); 2030 if (ret) { 2031 drm_err(ddev, "hardware identifier (0x%08x) not supported!\n", 2032 ldev->caps.hw_version); 2033 goto err; 2034 } 2035 2036 /* Disable all interrupts */ 2037 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); 2038 2039 drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version); 2040 2041 /* initialize default value for fifo underrun threshold & clear interrupt error counters */ 2042 ldev->transfer_err = 0; 2043 ldev->fifo_err = 0; 2044 ldev->fifo_warn = 0; 2045 ldev->fifo_threshold = FUT_DFT; 2046 2047 for (i = 0; i < ldev->caps.nb_irq; i++) { 2048 irq = platform_get_irq(pdev, i); 2049 if (irq < 0) { 2050 ret = irq; 2051 goto err; 2052 } 2053 2054 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 2055 ltdc_irq_thread, IRQF_ONESHOT, 2056 dev_name(dev), ddev); 2057 if (ret) { 2058 drm_err(ddev, "Failed to register LTDC interrupt\n"); 2059 goto err; 2060 } 2061 } 2062 2063 crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); 2064 if (!crtc) { 2065 drm_err(ddev, "Failed to allocate crtc\n"); 2066 ret = -ENOMEM; 2067 goto err; 2068 } 2069 2070 ret = ltdc_crtc_init(ddev, crtc); 2071 if (ret) { 2072 drm_err(ddev, "Failed to init crtc\n"); 2073 goto err; 2074 } 2075 2076 ret = drm_vblank_init(ddev, NB_CRTC); 2077 if (ret) { 2078 drm_err(ddev, "Failed calling drm_vblank_init()\n"); 2079 goto err; 2080 } 2081 2082 clk_disable_unprepare(ldev->pixel_clk); 2083 2084 if (ldev->bus_clk) 2085 clk_disable_unprepare(ldev->bus_clk); 2086 2087 pinctrl_pm_select_sleep_state(ddev->dev); 2088 2089 pm_runtime_enable(ddev->dev); 2090 2091 return 0; 2092 err: 2093 clk_disable_unprepare(ldev->pixel_clk); 2094 2095 if (ldev->bus_clk) 2096 clk_disable_unprepare(ldev->bus_clk); 2097 2098 return ret; 2099 } 2100 2101 void ltdc_unload(struct drm_device *ddev) 2102 { 2103 drm_dbg_driver(ddev, "\n"); 2104 2105 pm_runtime_disable(ddev->dev); 2106 } 2107 2108 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 2109 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2110 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 2111 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 2112 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 2113 MODULE_LICENSE("GPL v2"); 2114