1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <video/mipi_display.h> 17 18 #include <drm/bridge/dw_mipi_dsi.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_print.h> 21 22 #define HWVER_130 0x31333000 /* IP version 1.30 */ 23 #define HWVER_131 0x31333100 /* IP version 1.31 */ 24 25 /* DSI digital registers & bit definitions */ 26 #define DSI_VERSION 0x00 27 #define VERSION GENMASK(31, 8) 28 29 /* DSI wrapper registers & bit definitions */ 30 /* Note: registers are named as in the Reference Manual */ 31 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ 32 #define WCFGR_DSIM BIT(0) /* DSI Mode */ 33 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ 34 35 #define DSI_WCR 0x0404 /* Wrapper Control Reg */ 36 #define WCR_DSIEN BIT(3) /* DSI ENable */ 37 38 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ 39 #define WISR_PLLLS BIT(8) /* PLL Lock Status */ 40 #define WISR_RRS BIT(12) /* Regulator Ready Status */ 41 42 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ 43 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ 44 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ 45 46 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ 47 #define WRPCR_PLLEN BIT(0) /* PLL ENable */ 48 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ 49 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ 50 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ 51 #define WRPCR_REGEN BIT(24) /* REGulator ENable */ 52 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ 53 #define IDF_MIN 1 54 #define IDF_MAX 7 55 #define NDIV_MIN 10 56 #define NDIV_MAX 125 57 #define ODF_MIN 1 58 #define ODF_MAX 8 59 60 /* dsi color format coding according to the datasheet */ 61 enum dsi_color { 62 DSI_RGB565_CONF1, 63 DSI_RGB565_CONF2, 64 DSI_RGB565_CONF3, 65 DSI_RGB666_CONF1, 66 DSI_RGB666_CONF2, 67 DSI_RGB888, 68 }; 69 70 #define LANE_MIN_KBPS 31250 71 #define LANE_MAX_KBPS 500000 72 73 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */ 74 #define SLEEP_US 1000 75 #define TIMEOUT_US 200000 76 77 struct dw_mipi_dsi_stm { 78 void __iomem *base; 79 struct clk *pllref_clk; 80 struct dw_mipi_dsi *dsi; 81 u32 hw_version; 82 int lane_min_kbps; 83 int lane_max_kbps; 84 struct regulator *vdd_supply; 85 }; 86 87 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) 88 { 89 writel(val, dsi->base + reg); 90 } 91 92 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) 93 { 94 return readl(dsi->base + reg); 95 } 96 97 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 98 { 99 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 100 } 101 102 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 103 { 104 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); 105 } 106 107 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg, 108 u32 mask, u32 val) 109 { 110 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 111 } 112 113 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt) 114 { 115 switch (fmt) { 116 case MIPI_DSI_FMT_RGB888: 117 return DSI_RGB888; 118 case MIPI_DSI_FMT_RGB666: 119 return DSI_RGB666_CONF2; 120 case MIPI_DSI_FMT_RGB666_PACKED: 121 return DSI_RGB666_CONF1; 122 case MIPI_DSI_FMT_RGB565: 123 return DSI_RGB565_CONF1; 124 default: 125 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n"); 126 } 127 return DSI_RGB888; 128 } 129 130 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) 131 { 132 int divisor = idf * odf; 133 134 /* prevent from division by 0 */ 135 if (!divisor) 136 return 0; 137 138 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); 139 } 140 141 static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi, 142 int clkin_khz, int clkout_khz, 143 int *idf, int *ndiv, int *odf) 144 { 145 int i, o, n, n_min, n_max; 146 int fvco_min, fvco_max, delta, best_delta; /* all in khz */ 147 148 /* Early checks preventing division by 0 & odd results */ 149 if (clkin_khz <= 0 || clkout_khz <= 0) 150 return -EINVAL; 151 152 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX; 153 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN; 154 155 best_delta = 1000000; /* big started value (1000000khz) */ 156 157 for (i = IDF_MIN; i <= IDF_MAX; i++) { 158 /* Compute ndiv range according to Fvco */ 159 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1; 160 n_max = (fvco_max * i) / (2 * clkin_khz); 161 162 /* No need to continue idf loop if we reach ndiv max */ 163 if (n_min >= NDIV_MAX) 164 break; 165 166 /* Clamp ndiv to valid values */ 167 if (n_min < NDIV_MIN) 168 n_min = NDIV_MIN; 169 if (n_max > NDIV_MAX) 170 n_max = NDIV_MAX; 171 172 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) { 173 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); 174 /* Check ndiv according to vco range */ 175 if (n < n_min || n > n_max) 176 continue; 177 /* Check if new delta is better & saves parameters */ 178 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - 179 clkout_khz; 180 if (delta < 0) 181 delta = -delta; 182 if (delta < best_delta) { 183 *idf = i; 184 *ndiv = n; 185 *odf = o; 186 best_delta = delta; 187 } 188 /* fast return in case of "perfect result" */ 189 if (!delta) 190 return 0; 191 } 192 } 193 194 return 0; 195 } 196 197 static int dw_mipi_dsi_phy_init(void *priv_data) 198 { 199 struct dw_mipi_dsi_stm *dsi = priv_data; 200 u32 val; 201 int ret; 202 203 /* Enable the regulator */ 204 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); 205 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, 206 SLEEP_US, TIMEOUT_US); 207 if (ret) 208 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n"); 209 210 /* Enable the DSI PLL & wait for its lock */ 211 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); 212 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, 213 SLEEP_US, TIMEOUT_US); 214 if (ret) 215 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n"); 216 217 return 0; 218 } 219 220 static void dw_mipi_dsi_phy_power_on(void *priv_data) 221 { 222 struct dw_mipi_dsi_stm *dsi = priv_data; 223 224 DRM_DEBUG_DRIVER("\n"); 225 226 /* Enable the DSI wrapper */ 227 dsi_set(dsi, DSI_WCR, WCR_DSIEN); 228 } 229 230 static void dw_mipi_dsi_phy_power_off(void *priv_data) 231 { 232 struct dw_mipi_dsi_stm *dsi = priv_data; 233 234 DRM_DEBUG_DRIVER("\n"); 235 236 /* Disable the DSI wrapper */ 237 dsi_clear(dsi, DSI_WCR, WCR_DSIEN); 238 } 239 240 static int 241 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 242 unsigned long mode_flags, u32 lanes, u32 format, 243 unsigned int *lane_mbps) 244 { 245 struct dw_mipi_dsi_stm *dsi = priv_data; 246 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; 247 int ret, bpp; 248 u32 val; 249 250 /* Update lane capabilities according to hw version */ 251 dsi->lane_min_kbps = LANE_MIN_KBPS; 252 dsi->lane_max_kbps = LANE_MAX_KBPS; 253 if (dsi->hw_version == HWVER_131) { 254 dsi->lane_min_kbps *= 2; 255 dsi->lane_max_kbps *= 2; 256 } 257 258 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000); 259 260 /* Compute requested pll out */ 261 bpp = mipi_dsi_pixel_format_to_bpp(format); 262 pll_out_khz = mode->clock * bpp / lanes; 263 264 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ 265 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 266 pll_out_khz = (pll_out_khz * 12) / 10; 267 268 if (pll_out_khz > dsi->lane_max_kbps) { 269 pll_out_khz = dsi->lane_max_kbps; 270 DRM_WARN("Warning max phy mbps is used\n"); 271 } 272 if (pll_out_khz < dsi->lane_min_kbps) { 273 pll_out_khz = dsi->lane_min_kbps; 274 DRM_WARN("Warning min phy mbps is used\n"); 275 } 276 277 /* Compute best pll parameters */ 278 idf = 0; 279 ndiv = 0; 280 odf = 0; 281 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, 282 &idf, &ndiv, &odf); 283 if (ret) 284 DRM_WARN("Warning dsi_pll_get_params(): bad params\n"); 285 286 /* Get the adjusted pll out value */ 287 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 288 289 /* Set the PLL division factors */ 290 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, 291 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 292 293 /* Compute uix4 & set the bit period in high-speed mode */ 294 val = 4000000 / pll_out_khz; 295 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); 296 297 /* Select video mode by resetting DSIM bit */ 298 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); 299 300 /* Select the color coding */ 301 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, 302 dsi_color_from_mipi(format) << 1); 303 304 *lane_mbps = pll_out_khz / 1000; 305 306 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 307 pll_in_khz, pll_out_khz, *lane_mbps); 308 309 return 0; 310 } 311 312 #define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000) 313 314 static int 315 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 316 struct dw_mipi_dsi_dphy_timing *timing) 317 { 318 /* 319 * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747 320 * phy_clkhs2lp_time = (272+136*UI)/(8*UI) 321 * phy_clklp2hs_time = (512+40*UI)/(8*UI) 322 * phy_hs2lp_time = (192+64*UI)/(8*UI) 323 * phy_lp2hs_time = (256+32*UI)/(8*UI) 324 */ 325 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps); 326 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps); 327 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps); 328 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps); 329 330 return 0; 331 } 332 333 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = { 334 .init = dw_mipi_dsi_phy_init, 335 .power_on = dw_mipi_dsi_phy_power_on, 336 .power_off = dw_mipi_dsi_phy_power_off, 337 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 338 .get_timing = dw_mipi_dsi_phy_get_timing, 339 }; 340 341 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = { 342 .max_data_lanes = 2, 343 .phy_ops = &dw_mipi_dsi_stm_phy_ops, 344 }; 345 346 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = { 347 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, }, 348 { }, 349 }; 350 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids); 351 352 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) 353 { 354 struct device *dev = &pdev->dev; 355 struct dw_mipi_dsi_stm *dsi; 356 struct clk *pclk; 357 struct resource *res; 358 int ret; 359 360 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 361 if (!dsi) 362 return -ENOMEM; 363 364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 365 dsi->base = devm_ioremap_resource(dev, res); 366 if (IS_ERR(dsi->base)) { 367 ret = PTR_ERR(dsi->base); 368 DRM_ERROR("Unable to get dsi registers %d\n", ret); 369 return ret; 370 } 371 372 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi"); 373 if (IS_ERR(dsi->vdd_supply)) { 374 ret = PTR_ERR(dsi->vdd_supply); 375 dev_err_probe(dev, ret, "Failed to request regulator\n"); 376 return ret; 377 } 378 379 ret = regulator_enable(dsi->vdd_supply); 380 if (ret) { 381 DRM_ERROR("Failed to enable regulator: %d\n", ret); 382 return ret; 383 } 384 385 dsi->pllref_clk = devm_clk_get(dev, "ref"); 386 if (IS_ERR(dsi->pllref_clk)) { 387 ret = PTR_ERR(dsi->pllref_clk); 388 dev_err_probe(dev, ret, "Unable to get pll reference clock\n"); 389 goto err_clk_get; 390 } 391 392 ret = clk_prepare_enable(dsi->pllref_clk); 393 if (ret) { 394 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 395 goto err_clk_get; 396 } 397 398 pclk = devm_clk_get(dev, "pclk"); 399 if (IS_ERR(pclk)) { 400 ret = PTR_ERR(pclk); 401 DRM_ERROR("Unable to get peripheral clock: %d\n", ret); 402 goto err_dsi_probe; 403 } 404 405 ret = clk_prepare_enable(pclk); 406 if (ret) { 407 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__); 408 goto err_dsi_probe; 409 } 410 411 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 412 clk_disable_unprepare(pclk); 413 414 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) { 415 ret = -ENODEV; 416 DRM_ERROR("bad dsi hardware version\n"); 417 goto err_dsi_probe; 418 } 419 420 dw_mipi_dsi_stm_plat_data.base = dsi->base; 421 dw_mipi_dsi_stm_plat_data.priv_data = dsi; 422 423 platform_set_drvdata(pdev, dsi); 424 425 dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); 426 if (IS_ERR(dsi->dsi)) { 427 ret = PTR_ERR(dsi->dsi); 428 dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n"); 429 goto err_dsi_probe; 430 } 431 432 return 0; 433 434 err_dsi_probe: 435 clk_disable_unprepare(dsi->pllref_clk); 436 err_clk_get: 437 regulator_disable(dsi->vdd_supply); 438 439 return ret; 440 } 441 442 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev) 443 { 444 struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev); 445 446 dw_mipi_dsi_remove(dsi->dsi); 447 clk_disable_unprepare(dsi->pllref_clk); 448 regulator_disable(dsi->vdd_supply); 449 450 return 0; 451 } 452 453 static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev) 454 { 455 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 456 457 DRM_DEBUG_DRIVER("\n"); 458 459 clk_disable_unprepare(dsi->pllref_clk); 460 regulator_disable(dsi->vdd_supply); 461 462 return 0; 463 } 464 465 static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev) 466 { 467 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 468 int ret; 469 470 DRM_DEBUG_DRIVER("\n"); 471 472 ret = regulator_enable(dsi->vdd_supply); 473 if (ret) { 474 DRM_ERROR("Failed to enable regulator: %d\n", ret); 475 return ret; 476 } 477 478 ret = clk_prepare_enable(dsi->pllref_clk); 479 if (ret) { 480 regulator_disable(dsi->vdd_supply); 481 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 482 return ret; 483 } 484 485 return 0; 486 } 487 488 static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = { 489 SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend, 490 dw_mipi_dsi_stm_resume) 491 }; 492 493 static struct platform_driver dw_mipi_dsi_stm_driver = { 494 .probe = dw_mipi_dsi_stm_probe, 495 .remove = dw_mipi_dsi_stm_remove, 496 .driver = { 497 .of_match_table = dw_mipi_dsi_stm_dt_ids, 498 .name = "stm32-display-dsi", 499 .pm = &dw_mipi_dsi_stm_pm_ops, 500 }, 501 }; 502 503 module_platform_driver(dw_mipi_dsi_stm_driver); 504 505 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 506 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 507 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver"); 508 MODULE_LICENSE("GPL v2"); 509