1ec17f034SBenjamin Gaignard // SPDX-License-Identifier: GPL-2.0 2c1c026dbSPhilippe CORNU /* 3c1c026dbSPhilippe CORNU * Copyright (C) STMicroelectronics SA 2017 4c1c026dbSPhilippe CORNU * 5c1c026dbSPhilippe CORNU * Authors: Philippe Cornu <philippe.cornu@st.com> 6c1c026dbSPhilippe CORNU * Yannick Fertre <yannick.fertre@st.com> 7c1c026dbSPhilippe CORNU */ 8c1c026dbSPhilippe CORNU 9c1c026dbSPhilippe CORNU #include <linux/clk.h> 10c1c026dbSPhilippe CORNU #include <linux/iopoll.h> 1199a93888SSam Ravnborg #include <linux/mod_devicetable.h> 12c1c026dbSPhilippe CORNU #include <linux/module.h> 1399a93888SSam Ravnborg #include <linux/platform_device.h> 14f569aa9bSYannick Fertré #include <linux/regulator/consumer.h> 1599a93888SSam Ravnborg 16c1c026dbSPhilippe CORNU #include <video/mipi_display.h> 17c1c026dbSPhilippe CORNU 1899a93888SSam Ravnborg #include <drm/bridge/dw_mipi_dsi.h> 1999a93888SSam Ravnborg #include <drm/drm_mipi_dsi.h> 2099a93888SSam Ravnborg #include <drm/drm_print.h> 2199a93888SSam Ravnborg 22023f3489SPhilippe CORNU #define HWVER_130 0x31333000 /* IP version 1.30 */ 23023f3489SPhilippe CORNU #define HWVER_131 0x31333100 /* IP version 1.31 */ 24023f3489SPhilippe CORNU 25023f3489SPhilippe CORNU /* DSI digital registers & bit definitions */ 26023f3489SPhilippe CORNU #define DSI_VERSION 0x00 27023f3489SPhilippe CORNU #define VERSION GENMASK(31, 8) 28023f3489SPhilippe CORNU 29023f3489SPhilippe CORNU /* DSI wrapper registers & bit definitions */ 30c1c026dbSPhilippe CORNU /* Note: registers are named as in the Reference Manual */ 31c1c026dbSPhilippe CORNU #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ 32c1c026dbSPhilippe CORNU #define WCFGR_DSIM BIT(0) /* DSI Mode */ 33c1c026dbSPhilippe CORNU #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ 34c1c026dbSPhilippe CORNU 35c1c026dbSPhilippe CORNU #define DSI_WCR 0x0404 /* Wrapper Control Reg */ 36c1c026dbSPhilippe CORNU #define WCR_DSIEN BIT(3) /* DSI ENable */ 37c1c026dbSPhilippe CORNU 38c1c026dbSPhilippe CORNU #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ 39c1c026dbSPhilippe CORNU #define WISR_PLLLS BIT(8) /* PLL Lock Status */ 40c1c026dbSPhilippe CORNU #define WISR_RRS BIT(12) /* Regulator Ready Status */ 41c1c026dbSPhilippe CORNU 42c1c026dbSPhilippe CORNU #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ 43c1c026dbSPhilippe CORNU #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ 44c1c026dbSPhilippe CORNU #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ 45c1c026dbSPhilippe CORNU 46c1c026dbSPhilippe CORNU #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ 47c1c026dbSPhilippe CORNU #define WRPCR_PLLEN BIT(0) /* PLL ENable */ 48c1c026dbSPhilippe CORNU #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ 49c1c026dbSPhilippe CORNU #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ 50c1c026dbSPhilippe CORNU #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ 51c1c026dbSPhilippe CORNU #define WRPCR_REGEN BIT(24) /* REGulator ENable */ 52c1c026dbSPhilippe CORNU #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ 53c1c026dbSPhilippe CORNU #define IDF_MIN 1 54c1c026dbSPhilippe CORNU #define IDF_MAX 7 55c1c026dbSPhilippe CORNU #define NDIV_MIN 10 56c1c026dbSPhilippe CORNU #define NDIV_MAX 125 57c1c026dbSPhilippe CORNU #define ODF_MIN 1 58c1c026dbSPhilippe CORNU #define ODF_MAX 8 59c1c026dbSPhilippe CORNU 60c1c026dbSPhilippe CORNU /* dsi color format coding according to the datasheet */ 61c1c026dbSPhilippe CORNU enum dsi_color { 62c1c026dbSPhilippe CORNU DSI_RGB565_CONF1, 63c1c026dbSPhilippe CORNU DSI_RGB565_CONF2, 64c1c026dbSPhilippe CORNU DSI_RGB565_CONF3, 65c1c026dbSPhilippe CORNU DSI_RGB666_CONF1, 66c1c026dbSPhilippe CORNU DSI_RGB666_CONF2, 67c1c026dbSPhilippe CORNU DSI_RGB888, 68c1c026dbSPhilippe CORNU }; 69c1c026dbSPhilippe CORNU 70c1c026dbSPhilippe CORNU #define LANE_MIN_KBPS 31250 71c1c026dbSPhilippe CORNU #define LANE_MAX_KBPS 500000 72c1c026dbSPhilippe CORNU 73c1c026dbSPhilippe CORNU /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */ 74c1c026dbSPhilippe CORNU #define SLEEP_US 1000 75c1c026dbSPhilippe CORNU #define TIMEOUT_US 200000 76c1c026dbSPhilippe CORNU 77c1c026dbSPhilippe CORNU struct dw_mipi_dsi_stm { 78c1c026dbSPhilippe CORNU void __iomem *base; 79c1c026dbSPhilippe CORNU struct clk *pllref_clk; 808242ecbdSBrian Norris struct dw_mipi_dsi *dsi; 81023f3489SPhilippe CORNU u32 hw_version; 82023f3489SPhilippe CORNU int lane_min_kbps; 83023f3489SPhilippe CORNU int lane_max_kbps; 84f569aa9bSYannick Fertré struct regulator *vdd_supply; 85c1c026dbSPhilippe CORNU }; 86c1c026dbSPhilippe CORNU 87c1c026dbSPhilippe CORNU static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) 88c1c026dbSPhilippe CORNU { 89c1c026dbSPhilippe CORNU writel(val, dsi->base + reg); 90c1c026dbSPhilippe CORNU } 91c1c026dbSPhilippe CORNU 92c1c026dbSPhilippe CORNU static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) 93c1c026dbSPhilippe CORNU { 94c1c026dbSPhilippe CORNU return readl(dsi->base + reg); 95c1c026dbSPhilippe CORNU } 96c1c026dbSPhilippe CORNU 97c1c026dbSPhilippe CORNU static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 98c1c026dbSPhilippe CORNU { 99c1c026dbSPhilippe CORNU dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 100c1c026dbSPhilippe CORNU } 101c1c026dbSPhilippe CORNU 102c1c026dbSPhilippe CORNU static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 103c1c026dbSPhilippe CORNU { 104c1c026dbSPhilippe CORNU dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); 105c1c026dbSPhilippe CORNU } 106c1c026dbSPhilippe CORNU 107c1c026dbSPhilippe CORNU static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg, 108c1c026dbSPhilippe CORNU u32 mask, u32 val) 109c1c026dbSPhilippe CORNU { 110c1c026dbSPhilippe CORNU dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 111c1c026dbSPhilippe CORNU } 112c1c026dbSPhilippe CORNU 113c1c026dbSPhilippe CORNU static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt) 114c1c026dbSPhilippe CORNU { 115c1c026dbSPhilippe CORNU switch (fmt) { 116c1c026dbSPhilippe CORNU case MIPI_DSI_FMT_RGB888: 117c1c026dbSPhilippe CORNU return DSI_RGB888; 118c1c026dbSPhilippe CORNU case MIPI_DSI_FMT_RGB666: 119c1c026dbSPhilippe CORNU return DSI_RGB666_CONF2; 120c1c026dbSPhilippe CORNU case MIPI_DSI_FMT_RGB666_PACKED: 121c1c026dbSPhilippe CORNU return DSI_RGB666_CONF1; 122c1c026dbSPhilippe CORNU case MIPI_DSI_FMT_RGB565: 123c1c026dbSPhilippe CORNU return DSI_RGB565_CONF1; 124c1c026dbSPhilippe CORNU default: 125c1c026dbSPhilippe CORNU DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n"); 126c1c026dbSPhilippe CORNU } 127c1c026dbSPhilippe CORNU return DSI_RGB888; 128c1c026dbSPhilippe CORNU } 129c1c026dbSPhilippe CORNU 130c1c026dbSPhilippe CORNU static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) 131c1c026dbSPhilippe CORNU { 1323ff558e7SArnd Bergmann int divisor = idf * odf; 133c1c026dbSPhilippe CORNU 1343ff558e7SArnd Bergmann /* prevent from division by 0 */ 1353ff558e7SArnd Bergmann if (!divisor) 136c1c026dbSPhilippe CORNU return 0; 1373ff558e7SArnd Bergmann 1383ff558e7SArnd Bergmann return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); 139c1c026dbSPhilippe CORNU } 140c1c026dbSPhilippe CORNU 141023f3489SPhilippe CORNU static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi, 142023f3489SPhilippe CORNU int clkin_khz, int clkout_khz, 143c1c026dbSPhilippe CORNU int *idf, int *ndiv, int *odf) 144c1c026dbSPhilippe CORNU { 145c1c026dbSPhilippe CORNU int i, o, n, n_min, n_max; 146c1c026dbSPhilippe CORNU int fvco_min, fvco_max, delta, best_delta; /* all in khz */ 147c1c026dbSPhilippe CORNU 148c1c026dbSPhilippe CORNU /* Early checks preventing division by 0 & odd results */ 1490163d1f6SPhilippe CORNU if (clkin_khz <= 0 || clkout_khz <= 0) 150c1c026dbSPhilippe CORNU return -EINVAL; 151c1c026dbSPhilippe CORNU 152023f3489SPhilippe CORNU fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX; 153023f3489SPhilippe CORNU fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN; 154c1c026dbSPhilippe CORNU 155c1c026dbSPhilippe CORNU best_delta = 1000000; /* big started value (1000000khz) */ 156c1c026dbSPhilippe CORNU 157c1c026dbSPhilippe CORNU for (i = IDF_MIN; i <= IDF_MAX; i++) { 158c1c026dbSPhilippe CORNU /* Compute ndiv range according to Fvco */ 159c1c026dbSPhilippe CORNU n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1; 160c1c026dbSPhilippe CORNU n_max = (fvco_max * i) / (2 * clkin_khz); 161c1c026dbSPhilippe CORNU 162c1c026dbSPhilippe CORNU /* No need to continue idf loop if we reach ndiv max */ 163c1c026dbSPhilippe CORNU if (n_min >= NDIV_MAX) 164c1c026dbSPhilippe CORNU break; 165c1c026dbSPhilippe CORNU 166c1c026dbSPhilippe CORNU /* Clamp ndiv to valid values */ 167c1c026dbSPhilippe CORNU if (n_min < NDIV_MIN) 168c1c026dbSPhilippe CORNU n_min = NDIV_MIN; 169c1c026dbSPhilippe CORNU if (n_max > NDIV_MAX) 170c1c026dbSPhilippe CORNU n_max = NDIV_MAX; 171c1c026dbSPhilippe CORNU 172c1c026dbSPhilippe CORNU for (o = ODF_MIN; o <= ODF_MAX; o *= 2) { 173c1c026dbSPhilippe CORNU n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); 174c1c026dbSPhilippe CORNU /* Check ndiv according to vco range */ 1750163d1f6SPhilippe CORNU if (n < n_min || n > n_max) 176c1c026dbSPhilippe CORNU continue; 177c1c026dbSPhilippe CORNU /* Check if new delta is better & saves parameters */ 178c1c026dbSPhilippe CORNU delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - 179c1c026dbSPhilippe CORNU clkout_khz; 180c1c026dbSPhilippe CORNU if (delta < 0) 181c1c026dbSPhilippe CORNU delta = -delta; 182c1c026dbSPhilippe CORNU if (delta < best_delta) { 183c1c026dbSPhilippe CORNU *idf = i; 184c1c026dbSPhilippe CORNU *ndiv = n; 185c1c026dbSPhilippe CORNU *odf = o; 186c1c026dbSPhilippe CORNU best_delta = delta; 187c1c026dbSPhilippe CORNU } 188c1c026dbSPhilippe CORNU /* fast return in case of "perfect result" */ 189c1c026dbSPhilippe CORNU if (!delta) 190c1c026dbSPhilippe CORNU return 0; 191c1c026dbSPhilippe CORNU } 192c1c026dbSPhilippe CORNU } 193c1c026dbSPhilippe CORNU 194c1c026dbSPhilippe CORNU return 0; 195c1c026dbSPhilippe CORNU } 196c1c026dbSPhilippe CORNU 197c1c026dbSPhilippe CORNU static int dw_mipi_dsi_phy_init(void *priv_data) 198c1c026dbSPhilippe CORNU { 199c1c026dbSPhilippe CORNU struct dw_mipi_dsi_stm *dsi = priv_data; 200c1c026dbSPhilippe CORNU u32 val; 201c1c026dbSPhilippe CORNU int ret; 202c1c026dbSPhilippe CORNU 203c1c026dbSPhilippe CORNU /* Enable the regulator */ 204c1c026dbSPhilippe CORNU dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); 205c1c026dbSPhilippe CORNU ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, 206c1c026dbSPhilippe CORNU SLEEP_US, TIMEOUT_US); 207c1c026dbSPhilippe CORNU if (ret) 208c1c026dbSPhilippe CORNU DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n"); 209c1c026dbSPhilippe CORNU 210c1c026dbSPhilippe CORNU /* Enable the DSI PLL & wait for its lock */ 211c1c026dbSPhilippe CORNU dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); 212c1c026dbSPhilippe CORNU ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, 213c1c026dbSPhilippe CORNU SLEEP_US, TIMEOUT_US); 214c1c026dbSPhilippe CORNU if (ret) 215c1c026dbSPhilippe CORNU DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n"); 216c1c026dbSPhilippe CORNU 217ee7668bcSYannick Fertré return 0; 218ee7668bcSYannick Fertré } 219ee7668bcSYannick Fertré 220ee7668bcSYannick Fertré static void dw_mipi_dsi_phy_power_on(void *priv_data) 221ee7668bcSYannick Fertré { 222ee7668bcSYannick Fertré struct dw_mipi_dsi_stm *dsi = priv_data; 223ee7668bcSYannick Fertré 224ee7668bcSYannick Fertré DRM_DEBUG_DRIVER("\n"); 225ee7668bcSYannick Fertré 226c1c026dbSPhilippe CORNU /* Enable the DSI wrapper */ 227c1c026dbSPhilippe CORNU dsi_set(dsi, DSI_WCR, WCR_DSIEN); 228ee7668bcSYannick Fertré } 229c1c026dbSPhilippe CORNU 230ee7668bcSYannick Fertré static void dw_mipi_dsi_phy_power_off(void *priv_data) 231ee7668bcSYannick Fertré { 232ee7668bcSYannick Fertré struct dw_mipi_dsi_stm *dsi = priv_data; 233ee7668bcSYannick Fertré 234ee7668bcSYannick Fertré DRM_DEBUG_DRIVER("\n"); 235ee7668bcSYannick Fertré 236ee7668bcSYannick Fertré /* Disable the DSI wrapper */ 237ee7668bcSYannick Fertré dsi_clear(dsi, DSI_WCR, WCR_DSIEN); 238c1c026dbSPhilippe CORNU } 239c1c026dbSPhilippe CORNU 240c1c026dbSPhilippe CORNU static int 24163f8f3baSLaurent Pinchart dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 242c1c026dbSPhilippe CORNU unsigned long mode_flags, u32 lanes, u32 format, 243c1c026dbSPhilippe CORNU unsigned int *lane_mbps) 244c1c026dbSPhilippe CORNU { 245c1c026dbSPhilippe CORNU struct dw_mipi_dsi_stm *dsi = priv_data; 246c1c026dbSPhilippe CORNU unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; 247c1c026dbSPhilippe CORNU int ret, bpp; 248c1c026dbSPhilippe CORNU u32 val; 249c1c026dbSPhilippe CORNU 250023f3489SPhilippe CORNU /* Update lane capabilities according to hw version */ 251023f3489SPhilippe CORNU dsi->lane_min_kbps = LANE_MIN_KBPS; 252023f3489SPhilippe CORNU dsi->lane_max_kbps = LANE_MAX_KBPS; 253023f3489SPhilippe CORNU if (dsi->hw_version == HWVER_131) { 254023f3489SPhilippe CORNU dsi->lane_min_kbps *= 2; 255023f3489SPhilippe CORNU dsi->lane_max_kbps *= 2; 256023f3489SPhilippe CORNU } 257023f3489SPhilippe CORNU 258c1c026dbSPhilippe CORNU pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000); 259c1c026dbSPhilippe CORNU 260c1c026dbSPhilippe CORNU /* Compute requested pll out */ 261c1c026dbSPhilippe CORNU bpp = mipi_dsi_pixel_format_to_bpp(format); 262c1c026dbSPhilippe CORNU pll_out_khz = mode->clock * bpp / lanes; 2631e696204SYannick Fertré 264c1c026dbSPhilippe CORNU /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ 2651e696204SYannick Fertré if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 266c1c026dbSPhilippe CORNU pll_out_khz = (pll_out_khz * 12) / 10; 2671e696204SYannick Fertré 268023f3489SPhilippe CORNU if (pll_out_khz > dsi->lane_max_kbps) { 269023f3489SPhilippe CORNU pll_out_khz = dsi->lane_max_kbps; 270c1c026dbSPhilippe CORNU DRM_WARN("Warning max phy mbps is used\n"); 271c1c026dbSPhilippe CORNU } 272023f3489SPhilippe CORNU if (pll_out_khz < dsi->lane_min_kbps) { 273023f3489SPhilippe CORNU pll_out_khz = dsi->lane_min_kbps; 274c1c026dbSPhilippe CORNU DRM_WARN("Warning min phy mbps is used\n"); 275c1c026dbSPhilippe CORNU } 276c1c026dbSPhilippe CORNU 277c1c026dbSPhilippe CORNU /* Compute best pll parameters */ 278c1c026dbSPhilippe CORNU idf = 0; 279c1c026dbSPhilippe CORNU ndiv = 0; 280c1c026dbSPhilippe CORNU odf = 0; 281023f3489SPhilippe CORNU ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, 282023f3489SPhilippe CORNU &idf, &ndiv, &odf); 283c1c026dbSPhilippe CORNU if (ret) 284c1c026dbSPhilippe CORNU DRM_WARN("Warning dsi_pll_get_params(): bad params\n"); 285c1c026dbSPhilippe CORNU 286c1c026dbSPhilippe CORNU /* Get the adjusted pll out value */ 287c1c026dbSPhilippe CORNU pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 288c1c026dbSPhilippe CORNU 289c1c026dbSPhilippe CORNU /* Set the PLL division factors */ 290c1c026dbSPhilippe CORNU dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, 291c1c026dbSPhilippe CORNU (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 292c1c026dbSPhilippe CORNU 293c1c026dbSPhilippe CORNU /* Compute uix4 & set the bit period in high-speed mode */ 294c1c026dbSPhilippe CORNU val = 4000000 / pll_out_khz; 295c1c026dbSPhilippe CORNU dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); 296c1c026dbSPhilippe CORNU 297c1c026dbSPhilippe CORNU /* Select video mode by resetting DSIM bit */ 298c1c026dbSPhilippe CORNU dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); 299c1c026dbSPhilippe CORNU 300c1c026dbSPhilippe CORNU /* Select the color coding */ 301c1c026dbSPhilippe CORNU dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, 302c1c026dbSPhilippe CORNU dsi_color_from_mipi(format) << 1); 303c1c026dbSPhilippe CORNU 304c1c026dbSPhilippe CORNU *lane_mbps = pll_out_khz / 1000; 305c1c026dbSPhilippe CORNU 306c1c026dbSPhilippe CORNU DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 307c1c026dbSPhilippe CORNU pll_in_khz, pll_out_khz, *lane_mbps); 308c1c026dbSPhilippe CORNU 309c1c026dbSPhilippe CORNU return 0; 310c1c026dbSPhilippe CORNU } 311c1c026dbSPhilippe CORNU 312*25ed8aebSHeiko Stuebner static int 313*25ed8aebSHeiko Stuebner dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 314*25ed8aebSHeiko Stuebner struct dw_mipi_dsi_dphy_timing *timing) 315*25ed8aebSHeiko Stuebner { 316*25ed8aebSHeiko Stuebner timing->clk_hs2lp = 0x40; 317*25ed8aebSHeiko Stuebner timing->clk_lp2hs = 0x40; 318*25ed8aebSHeiko Stuebner timing->data_hs2lp = 0x40; 319*25ed8aebSHeiko Stuebner timing->data_lp2hs = 0x40; 320*25ed8aebSHeiko Stuebner 321*25ed8aebSHeiko Stuebner return 0; 322*25ed8aebSHeiko Stuebner } 323*25ed8aebSHeiko Stuebner 32489a15e6fSPhilippe CORNU static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = { 325c1c026dbSPhilippe CORNU .init = dw_mipi_dsi_phy_init, 326ee7668bcSYannick Fertré .power_on = dw_mipi_dsi_phy_power_on, 327ee7668bcSYannick Fertré .power_off = dw_mipi_dsi_phy_power_off, 328c1c026dbSPhilippe CORNU .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 329*25ed8aebSHeiko Stuebner .get_timing = dw_mipi_dsi_phy_get_timing, 330c1c026dbSPhilippe CORNU }; 331c1c026dbSPhilippe CORNU 332c1c026dbSPhilippe CORNU static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = { 333c1c026dbSPhilippe CORNU .max_data_lanes = 2, 334c1c026dbSPhilippe CORNU .phy_ops = &dw_mipi_dsi_stm_phy_ops, 335c1c026dbSPhilippe CORNU }; 336c1c026dbSPhilippe CORNU 337c1c026dbSPhilippe CORNU static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = { 338c1c026dbSPhilippe CORNU { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, }, 339c1c026dbSPhilippe CORNU { }, 340c1c026dbSPhilippe CORNU }; 341c1c026dbSPhilippe CORNU MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids); 342c1c026dbSPhilippe CORNU 343c1c026dbSPhilippe CORNU static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) 344c1c026dbSPhilippe CORNU { 345c1c026dbSPhilippe CORNU struct device *dev = &pdev->dev; 346c1c026dbSPhilippe CORNU struct dw_mipi_dsi_stm *dsi; 347fa6251a7SYannick Fertré struct clk *pclk; 348c1c026dbSPhilippe CORNU struct resource *res; 349c1c026dbSPhilippe CORNU int ret; 350c1c026dbSPhilippe CORNU 351c1c026dbSPhilippe CORNU dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 352c1c026dbSPhilippe CORNU if (!dsi) 353c1c026dbSPhilippe CORNU return -ENOMEM; 354c1c026dbSPhilippe CORNU 355c1c026dbSPhilippe CORNU res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 356c1c026dbSPhilippe CORNU dsi->base = devm_ioremap_resource(dev, res); 357c1c026dbSPhilippe CORNU if (IS_ERR(dsi->base)) { 358f569aa9bSYannick Fertré ret = PTR_ERR(dsi->base); 359f569aa9bSYannick Fertré DRM_ERROR("Unable to get dsi registers %d\n", ret); 360f569aa9bSYannick Fertré return ret; 361f569aa9bSYannick Fertré } 362f569aa9bSYannick Fertré 363f569aa9bSYannick Fertré dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi"); 364f569aa9bSYannick Fertré if (IS_ERR(dsi->vdd_supply)) { 365f569aa9bSYannick Fertré ret = PTR_ERR(dsi->vdd_supply); 366f569aa9bSYannick Fertré if (ret != -EPROBE_DEFER) 367f569aa9bSYannick Fertré DRM_ERROR("Failed to request regulator: %d\n", ret); 368f569aa9bSYannick Fertré return ret; 369f569aa9bSYannick Fertré } 370f569aa9bSYannick Fertré 371f569aa9bSYannick Fertré ret = regulator_enable(dsi->vdd_supply); 372f569aa9bSYannick Fertré if (ret) { 373f569aa9bSYannick Fertré DRM_ERROR("Failed to enable regulator: %d\n", ret); 374f569aa9bSYannick Fertré return ret; 375c1c026dbSPhilippe CORNU } 376c1c026dbSPhilippe CORNU 377c1c026dbSPhilippe CORNU dsi->pllref_clk = devm_clk_get(dev, "ref"); 378c1c026dbSPhilippe CORNU if (IS_ERR(dsi->pllref_clk)) { 379c1c026dbSPhilippe CORNU ret = PTR_ERR(dsi->pllref_clk); 380f569aa9bSYannick Fertré DRM_ERROR("Unable to get pll reference clock: %d\n", ret); 381f569aa9bSYannick Fertré goto err_clk_get; 382c1c026dbSPhilippe CORNU } 383c1c026dbSPhilippe CORNU 384c1c026dbSPhilippe CORNU ret = clk_prepare_enable(dsi->pllref_clk); 385c1c026dbSPhilippe CORNU if (ret) { 386f569aa9bSYannick Fertré DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 387f569aa9bSYannick Fertré goto err_clk_get; 388c1c026dbSPhilippe CORNU } 389c1c026dbSPhilippe CORNU 390fa6251a7SYannick Fertré pclk = devm_clk_get(dev, "pclk"); 391fa6251a7SYannick Fertré if (IS_ERR(pclk)) { 392fa6251a7SYannick Fertré ret = PTR_ERR(pclk); 393fa6251a7SYannick Fertré DRM_ERROR("Unable to get peripheral clock: %d\n", ret); 394fa6251a7SYannick Fertré goto err_dsi_probe; 395fa6251a7SYannick Fertré } 396fa6251a7SYannick Fertré 397fa6251a7SYannick Fertré ret = clk_prepare_enable(pclk); 398fa6251a7SYannick Fertré if (ret) { 399fa6251a7SYannick Fertré DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__); 400fa6251a7SYannick Fertré goto err_dsi_probe; 401fa6251a7SYannick Fertré } 402fa6251a7SYannick Fertré 403fa6251a7SYannick Fertré dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 404fa6251a7SYannick Fertré clk_disable_unprepare(pclk); 405fa6251a7SYannick Fertré 406fa6251a7SYannick Fertré if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) { 407fa6251a7SYannick Fertré ret = -ENODEV; 408fa6251a7SYannick Fertré DRM_ERROR("bad dsi hardware version\n"); 409fa6251a7SYannick Fertré goto err_dsi_probe; 410fa6251a7SYannick Fertré } 411fa6251a7SYannick Fertré 412c1c026dbSPhilippe CORNU dw_mipi_dsi_stm_plat_data.base = dsi->base; 413c1c026dbSPhilippe CORNU dw_mipi_dsi_stm_plat_data.priv_data = dsi; 414c1c026dbSPhilippe CORNU 4158242ecbdSBrian Norris platform_set_drvdata(pdev, dsi); 4168242ecbdSBrian Norris 4178242ecbdSBrian Norris dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); 4188242ecbdSBrian Norris if (IS_ERR(dsi->dsi)) { 419f569aa9bSYannick Fertré ret = PTR_ERR(dsi->dsi); 420f569aa9bSYannick Fertré DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret); 421f569aa9bSYannick Fertré goto err_dsi_probe; 422c1c026dbSPhilippe CORNU } 423c1c026dbSPhilippe CORNU 4248242ecbdSBrian Norris return 0; 425f569aa9bSYannick Fertré 426f569aa9bSYannick Fertré err_dsi_probe: 427f569aa9bSYannick Fertré clk_disable_unprepare(dsi->pllref_clk); 428f569aa9bSYannick Fertré err_clk_get: 429f569aa9bSYannick Fertré regulator_disable(dsi->vdd_supply); 430f569aa9bSYannick Fertré 431f569aa9bSYannick Fertré return ret; 432c1c026dbSPhilippe CORNU } 433c1c026dbSPhilippe CORNU 434c1c026dbSPhilippe CORNU static int dw_mipi_dsi_stm_remove(struct platform_device *pdev) 435c1c026dbSPhilippe CORNU { 4368242ecbdSBrian Norris struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev); 437c1c026dbSPhilippe CORNU 4388242ecbdSBrian Norris dw_mipi_dsi_remove(dsi->dsi); 439f569aa9bSYannick Fertré clk_disable_unprepare(dsi->pllref_clk); 440f569aa9bSYannick Fertré regulator_disable(dsi->vdd_supply); 441c1c026dbSPhilippe CORNU 442c1c026dbSPhilippe CORNU return 0; 443c1c026dbSPhilippe CORNU } 444c1c026dbSPhilippe CORNU 4451861a1ffSYannick Fertré static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev) 4461861a1ffSYannick Fertré { 4471861a1ffSYannick Fertré struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 4481861a1ffSYannick Fertré 4491861a1ffSYannick Fertré DRM_DEBUG_DRIVER("\n"); 4501861a1ffSYannick Fertré 4511861a1ffSYannick Fertré clk_disable_unprepare(dsi->pllref_clk); 452f569aa9bSYannick Fertré regulator_disable(dsi->vdd_supply); 4531861a1ffSYannick Fertré 4541861a1ffSYannick Fertré return 0; 4551861a1ffSYannick Fertré } 4561861a1ffSYannick Fertré 4571861a1ffSYannick Fertré static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev) 4581861a1ffSYannick Fertré { 4591861a1ffSYannick Fertré struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 460f569aa9bSYannick Fertré int ret; 4611861a1ffSYannick Fertré 4621861a1ffSYannick Fertré DRM_DEBUG_DRIVER("\n"); 4631861a1ffSYannick Fertré 464f569aa9bSYannick Fertré ret = regulator_enable(dsi->vdd_supply); 465f569aa9bSYannick Fertré if (ret) { 466f569aa9bSYannick Fertré DRM_ERROR("Failed to enable regulator: %d\n", ret); 467f569aa9bSYannick Fertré return ret; 468f569aa9bSYannick Fertré } 469f569aa9bSYannick Fertré 470f569aa9bSYannick Fertré ret = clk_prepare_enable(dsi->pllref_clk); 471f569aa9bSYannick Fertré if (ret) { 472f569aa9bSYannick Fertré regulator_disable(dsi->vdd_supply); 473f569aa9bSYannick Fertré DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 474f569aa9bSYannick Fertré return ret; 475f569aa9bSYannick Fertré } 4761861a1ffSYannick Fertré 4771861a1ffSYannick Fertré return 0; 4781861a1ffSYannick Fertré } 4791861a1ffSYannick Fertré 4801861a1ffSYannick Fertré static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = { 4811861a1ffSYannick Fertré SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend, 4821861a1ffSYannick Fertré dw_mipi_dsi_stm_resume) 4831861a1ffSYannick Fertré }; 4841861a1ffSYannick Fertré 485c1c026dbSPhilippe CORNU static struct platform_driver dw_mipi_dsi_stm_driver = { 486c1c026dbSPhilippe CORNU .probe = dw_mipi_dsi_stm_probe, 487c1c026dbSPhilippe CORNU .remove = dw_mipi_dsi_stm_remove, 488c1c026dbSPhilippe CORNU .driver = { 489c1c026dbSPhilippe CORNU .of_match_table = dw_mipi_dsi_stm_dt_ids, 490bb3fb5e5SPhilippe CORNU .name = "stm32-display-dsi", 4911861a1ffSYannick Fertré .pm = &dw_mipi_dsi_stm_pm_ops, 492c1c026dbSPhilippe CORNU }, 493c1c026dbSPhilippe CORNU }; 494c1c026dbSPhilippe CORNU 495c1c026dbSPhilippe CORNU module_platform_driver(dw_mipi_dsi_stm_driver); 496c1c026dbSPhilippe CORNU 497c1c026dbSPhilippe CORNU MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 498c1c026dbSPhilippe CORNU MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 499c1c026dbSPhilippe CORNU MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver"); 500c1c026dbSPhilippe CORNU MODULE_LICENSE("GPL v2"); 501