1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * Vincent Abriou <vincent.abriou@st.com> 7 * for STMicroelectronics. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/io.h> 12 #include <linux/notifier.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 16 #include <drm/drm_modes.h> 17 #include <drm/drm_print.h> 18 19 #include "sti_drv.h" 20 #include "sti_vtg.h" 21 22 #define VTG_MODE_MASTER 0 23 24 /* registers offset */ 25 #define VTG_MODE 0x0000 26 #define VTG_CLKLN 0x0008 27 #define VTG_HLFLN 0x000C 28 #define VTG_DRST_AUTOC 0x0010 29 #define VTG_VID_TFO 0x0040 30 #define VTG_VID_TFS 0x0044 31 #define VTG_VID_BFO 0x0048 32 #define VTG_VID_BFS 0x004C 33 34 #define VTG_HOST_ITS 0x0078 35 #define VTG_HOST_ITS_BCLR 0x007C 36 #define VTG_HOST_ITM_BCLR 0x0088 37 #define VTG_HOST_ITM_BSET 0x008C 38 39 #define VTG_H_HD_1 0x00C0 40 #define VTG_TOP_V_VD_1 0x00C4 41 #define VTG_BOT_V_VD_1 0x00C8 42 #define VTG_TOP_V_HD_1 0x00CC 43 #define VTG_BOT_V_HD_1 0x00D0 44 45 #define VTG_H_HD_2 0x00E0 46 #define VTG_TOP_V_VD_2 0x00E4 47 #define VTG_BOT_V_VD_2 0x00E8 48 #define VTG_TOP_V_HD_2 0x00EC 49 #define VTG_BOT_V_HD_2 0x00F0 50 51 #define VTG_H_HD_3 0x0100 52 #define VTG_TOP_V_VD_3 0x0104 53 #define VTG_BOT_V_VD_3 0x0108 54 #define VTG_TOP_V_HD_3 0x010C 55 #define VTG_BOT_V_HD_3 0x0110 56 57 #define VTG_H_HD_4 0x0120 58 #define VTG_TOP_V_VD_4 0x0124 59 #define VTG_BOT_V_VD_4 0x0128 60 #define VTG_TOP_V_HD_4 0x012c 61 #define VTG_BOT_V_HD_4 0x0130 62 63 #define VTG_IRQ_BOTTOM BIT(0) 64 #define VTG_IRQ_TOP BIT(1) 65 #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) 66 67 /* Delay introduced by the HDMI in nb of pixel */ 68 #define HDMI_DELAY (5) 69 70 /* Delay introduced by the DVO in nb of pixel */ 71 #define DVO_DELAY (7) 72 73 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ 74 #define AWG_DELAY_HD (-9) 75 #define AWG_DELAY_ED (-8) 76 #define AWG_DELAY_SD (-7) 77 78 /* 79 * STI VTG register offset structure 80 * 81 *@h_hd: stores the VTG_H_HD_x register offset 82 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset 83 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset 84 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset 85 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset 86 */ 87 struct sti_vtg_regs_offs { 88 u32 h_hd; 89 u32 top_v_vd; 90 u32 bot_v_vd; 91 u32 top_v_hd; 92 u32 bot_v_hd; 93 }; 94 95 #define VTG_MAX_SYNC_OUTPUT 4 96 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { 97 { VTG_H_HD_1, 98 VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 }, 99 { VTG_H_HD_2, 100 VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 }, 101 { VTG_H_HD_3, 102 VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 }, 103 { VTG_H_HD_4, 104 VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 } 105 }; 106 107 /* 108 * STI VTG synchronisation parameters structure 109 * 110 *@hsync: sample number falling and rising edge 111 *@vsync_line_top: vertical top field line number falling and rising edge 112 *@vsync_line_bot: vertical bottom field line number falling and rising edge 113 *@vsync_off_top: vertical top field sample number rising and falling edge 114 *@vsync_off_bot: vertical bottom field sample number rising and falling edge 115 */ 116 struct sti_vtg_sync_params { 117 u32 hsync; 118 u32 vsync_line_top; 119 u32 vsync_line_bot; 120 u32 vsync_off_top; 121 u32 vsync_off_bot; 122 }; 123 124 /* 125 * STI VTG structure 126 * 127 * @regs: register mapping 128 * @sync_params: synchronisation parameters used to generate timings 129 * @irq: VTG irq 130 * @irq_status: store the IRQ status value 131 * @notifier_list: notifier callback 132 * @crtc: the CRTC for vblank event 133 */ 134 struct sti_vtg { 135 void __iomem *regs; 136 struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT]; 137 int irq; 138 u32 irq_status; 139 struct raw_notifier_head notifier_list; 140 struct drm_crtc *crtc; 141 }; 142 143 struct sti_vtg *of_vtg_find(struct device_node *np) 144 { 145 struct platform_device *pdev; 146 struct sti_vtg *vtg; 147 148 pdev = of_find_device_by_node(np); 149 if (!pdev) 150 return NULL; 151 152 vtg = platform_get_drvdata(pdev); 153 154 put_device(&pdev->dev); 155 156 return vtg; 157 } 158 159 static void vtg_reset(struct sti_vtg *vtg) 160 { 161 writel(1, vtg->regs + VTG_DRST_AUTOC); 162 } 163 164 static void vtg_set_output_window(void __iomem *regs, 165 const struct drm_display_mode *mode) 166 { 167 u32 video_top_field_start; 168 u32 video_top_field_stop; 169 u32 video_bottom_field_start; 170 u32 video_bottom_field_stop; 171 u32 xstart = sti_vtg_get_pixel_number(*mode, 0); 172 u32 ystart = sti_vtg_get_line_number(*mode, 0); 173 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 174 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 175 176 /* Set output window to fit the display mode selected */ 177 video_top_field_start = (ystart << 16) | xstart; 178 video_top_field_stop = (ystop << 16) | xstop; 179 180 /* Only progressive supported for now */ 181 video_bottom_field_start = video_top_field_start; 182 video_bottom_field_stop = video_top_field_stop; 183 184 writel(video_top_field_start, regs + VTG_VID_TFO); 185 writel(video_top_field_stop, regs + VTG_VID_TFS); 186 writel(video_bottom_field_start, regs + VTG_VID_BFO); 187 writel(video_bottom_field_stop, regs + VTG_VID_BFS); 188 } 189 190 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, 191 int delay, 192 const struct drm_display_mode *mode) 193 { 194 long clocksperline, start, stop; 195 u32 risesync_top, fallsync_top; 196 u32 risesync_offs_top, fallsync_offs_top; 197 198 clocksperline = mode->htotal; 199 200 /* Get the hsync position */ 201 start = 0; 202 stop = mode->hsync_end - mode->hsync_start; 203 204 start += delay; 205 stop += delay; 206 207 if (start < 0) 208 start += clocksperline; 209 else if (start >= clocksperline) 210 start -= clocksperline; 211 212 if (stop < 0) 213 stop += clocksperline; 214 else if (stop >= clocksperline) 215 stop -= clocksperline; 216 217 sync->hsync = (stop << 16) | start; 218 219 /* Get the vsync position */ 220 if (delay >= 0) { 221 risesync_top = 1; 222 fallsync_top = risesync_top; 223 fallsync_top += mode->vsync_end - mode->vsync_start; 224 225 fallsync_offs_top = (u32)delay; 226 risesync_offs_top = (u32)delay; 227 } else { 228 risesync_top = mode->vtotal; 229 fallsync_top = mode->vsync_end - mode->vsync_start; 230 231 fallsync_offs_top = clocksperline + delay; 232 risesync_offs_top = clocksperline + delay; 233 } 234 235 sync->vsync_line_top = (fallsync_top << 16) | risesync_top; 236 sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top; 237 238 /* Only progressive supported for now */ 239 sync->vsync_line_bot = sync->vsync_line_top; 240 sync->vsync_off_bot = sync->vsync_off_top; 241 } 242 243 static void vtg_set_mode(struct sti_vtg *vtg, 244 int type, 245 struct sti_vtg_sync_params *sync, 246 const struct drm_display_mode *mode) 247 { 248 unsigned int i; 249 250 /* Set the number of clock cycles per line */ 251 writel(mode->htotal, vtg->regs + VTG_CLKLN); 252 253 /* Set Half Line Per Field (only progressive supported for now) */ 254 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 255 256 /* Program output window */ 257 vtg_set_output_window(vtg->regs, mode); 258 259 /* Set hsync and vsync position for HDMI */ 260 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode); 261 262 /* Set hsync and vsync position for HD DCS */ 263 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode); 264 265 /* Set hsync and vsync position for HDF */ 266 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode); 267 268 /* Set hsync and vsync position for DVO */ 269 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode); 270 271 /* Progam the syncs outputs */ 272 for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) { 273 writel(sync[i].hsync, 274 vtg->regs + vtg_regs_offs[i].h_hd); 275 writel(sync[i].vsync_line_top, 276 vtg->regs + vtg_regs_offs[i].top_v_vd); 277 writel(sync[i].vsync_line_bot, 278 vtg->regs + vtg_regs_offs[i].bot_v_vd); 279 writel(sync[i].vsync_off_top, 280 vtg->regs + vtg_regs_offs[i].top_v_hd); 281 writel(sync[i].vsync_off_bot, 282 vtg->regs + vtg_regs_offs[i].bot_v_hd); 283 } 284 285 /* mode */ 286 writel(type, vtg->regs + VTG_MODE); 287 } 288 289 static void vtg_enable_irq(struct sti_vtg *vtg) 290 { 291 /* clear interrupt status and mask */ 292 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); 293 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); 294 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); 295 } 296 297 void sti_vtg_set_config(struct sti_vtg *vtg, 298 const struct drm_display_mode *mode) 299 { 300 /* write configuration */ 301 vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode); 302 303 vtg_reset(vtg); 304 305 vtg_enable_irq(vtg); 306 } 307 308 /** 309 * sti_vtg_get_line_number 310 * 311 * @mode: display mode to be used 312 * @y: line 313 * 314 * Return the line number according to the display mode taking 315 * into account the Sync and Back Porch information. 316 * Video frame line numbers start at 1, y starts at 0. 317 * In interlaced modes the start line is the field line number of the odd 318 * field, but y is still defined as a progressive frame. 319 */ 320 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) 321 { 322 u32 start_line = mode.vtotal - mode.vsync_start + 1; 323 324 if (mode.flags & DRM_MODE_FLAG_INTERLACE) 325 start_line *= 2; 326 327 return start_line + y; 328 } 329 330 /** 331 * sti_vtg_get_pixel_number 332 * 333 * @mode: display mode to be used 334 * @x: row 335 * 336 * Return the pixel number according to the display mode taking 337 * into account the Sync and Back Porch information. 338 * Pixels are counted from 0. 339 */ 340 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) 341 { 342 return mode.htotal - mode.hsync_start + x; 343 } 344 345 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb, 346 struct drm_crtc *crtc) 347 { 348 vtg->crtc = crtc; 349 return raw_notifier_chain_register(&vtg->notifier_list, nb); 350 } 351 352 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb) 353 { 354 return raw_notifier_chain_unregister(&vtg->notifier_list, nb); 355 } 356 357 static irqreturn_t vtg_irq_thread(int irq, void *arg) 358 { 359 struct sti_vtg *vtg = arg; 360 u32 event; 361 362 event = (vtg->irq_status & VTG_IRQ_TOP) ? 363 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT; 364 365 raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc); 366 367 return IRQ_HANDLED; 368 } 369 370 static irqreturn_t vtg_irq(int irq, void *arg) 371 { 372 struct sti_vtg *vtg = arg; 373 374 vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS); 375 376 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); 377 378 /* force sync bus write */ 379 readl(vtg->regs + VTG_HOST_ITS); 380 381 return IRQ_WAKE_THREAD; 382 } 383 384 static int vtg_probe(struct platform_device *pdev) 385 { 386 struct device *dev = &pdev->dev; 387 struct sti_vtg *vtg; 388 int ret; 389 390 vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); 391 if (!vtg) 392 return -ENOMEM; 393 vtg->regs = devm_platform_ioremap_resource(pdev, 0); 394 if (IS_ERR(vtg->regs)) { 395 DRM_ERROR("failed to remap I/O memory\n"); 396 return PTR_ERR(vtg->regs); 397 } 398 399 vtg->irq = platform_get_irq(pdev, 0); 400 if (vtg->irq < 0) { 401 DRM_ERROR("Failed to get VTG interrupt\n"); 402 return vtg->irq; 403 } 404 405 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); 406 407 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, 408 vtg_irq_thread, IRQF_ONESHOT, 409 dev_name(dev), vtg); 410 if (ret < 0) { 411 DRM_ERROR("Failed to register VTG interrupt\n"); 412 return ret; 413 } 414 415 platform_set_drvdata(pdev, vtg); 416 417 DRM_INFO("%s %s\n", __func__, dev_name(dev)); 418 419 return 0; 420 } 421 422 static const struct of_device_id vtg_of_match[] = { 423 { .compatible = "st,vtg", }, 424 { /* sentinel */ } 425 }; 426 MODULE_DEVICE_TABLE(of, vtg_of_match); 427 428 struct platform_driver sti_vtg_driver = { 429 .driver = { 430 .name = "sti-vtg", 431 .of_match_table = vtg_of_match, 432 }, 433 .probe = vtg_probe, 434 }; 435 436 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 437 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 438 MODULE_LICENSE("GPL"); 439