1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * Vincent Abriou <vincent.abriou@st.com> 6 * for STMicroelectronics. 7 * License terms: GNU General Public License (GPL), version 2 8 */ 9 10 #include <linux/module.h> 11 #include <linux/notifier.h> 12 #include <linux/platform_device.h> 13 14 #include <drm/drmP.h> 15 16 #include "sti_drv.h" 17 #include "sti_vtg.h" 18 19 #define VTG_MODE_MASTER 0 20 21 /* registers offset */ 22 #define VTG_MODE 0x0000 23 #define VTG_CLKLN 0x0008 24 #define VTG_HLFLN 0x000C 25 #define VTG_DRST_AUTOC 0x0010 26 #define VTG_VID_TFO 0x0040 27 #define VTG_VID_TFS 0x0044 28 #define VTG_VID_BFO 0x0048 29 #define VTG_VID_BFS 0x004C 30 31 #define VTG_HOST_ITS 0x0078 32 #define VTG_HOST_ITS_BCLR 0x007C 33 #define VTG_HOST_ITM_BCLR 0x0088 34 #define VTG_HOST_ITM_BSET 0x008C 35 36 #define VTG_H_HD_1 0x00C0 37 #define VTG_TOP_V_VD_1 0x00C4 38 #define VTG_BOT_V_VD_1 0x00C8 39 #define VTG_TOP_V_HD_1 0x00CC 40 #define VTG_BOT_V_HD_1 0x00D0 41 42 #define VTG_H_HD_2 0x00E0 43 #define VTG_TOP_V_VD_2 0x00E4 44 #define VTG_BOT_V_VD_2 0x00E8 45 #define VTG_TOP_V_HD_2 0x00EC 46 #define VTG_BOT_V_HD_2 0x00F0 47 48 #define VTG_H_HD_3 0x0100 49 #define VTG_TOP_V_VD_3 0x0104 50 #define VTG_BOT_V_VD_3 0x0108 51 #define VTG_TOP_V_HD_3 0x010C 52 #define VTG_BOT_V_HD_3 0x0110 53 54 #define VTG_H_HD_4 0x0120 55 #define VTG_TOP_V_VD_4 0x0124 56 #define VTG_BOT_V_VD_4 0x0128 57 #define VTG_TOP_V_HD_4 0x012c 58 #define VTG_BOT_V_HD_4 0x0130 59 60 #define VTG_IRQ_BOTTOM BIT(0) 61 #define VTG_IRQ_TOP BIT(1) 62 #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) 63 64 /* Delay introduced by the HDMI in nb of pixel */ 65 #define HDMI_DELAY (5) 66 67 /* Delay introduced by the DVO in nb of pixel */ 68 #define DVO_DELAY (7) 69 70 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ 71 #define AWG_DELAY_HD (-9) 72 #define AWG_DELAY_ED (-8) 73 #define AWG_DELAY_SD (-7) 74 75 static LIST_HEAD(vtg_lookup); 76 77 /* 78 * STI VTG register offset structure 79 * 80 *@h_hd: stores the VTG_H_HD_x register offset 81 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset 82 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset 83 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset 84 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset 85 */ 86 struct sti_vtg_regs_offs { 87 u32 h_hd; 88 u32 top_v_vd; 89 u32 bot_v_vd; 90 u32 top_v_hd; 91 u32 bot_v_hd; 92 }; 93 94 #define VTG_MAX_SYNC_OUTPUT 4 95 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { 96 { VTG_H_HD_1, 97 VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 }, 98 { VTG_H_HD_2, 99 VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 }, 100 { VTG_H_HD_3, 101 VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 }, 102 { VTG_H_HD_4, 103 VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 } 104 }; 105 106 /* 107 * STI VTG synchronisation parameters structure 108 * 109 *@hsync: sample number falling and rising edge 110 *@vsync_line_top: vertical top field line number falling and rising edge 111 *@vsync_line_bot: vertical bottom field line number falling and rising edge 112 *@vsync_off_top: vertical top field sample number rising and falling edge 113 *@vsync_off_bot: vertical bottom field sample number rising and falling edge 114 */ 115 struct sti_vtg_sync_params { 116 u32 hsync; 117 u32 vsync_line_top; 118 u32 vsync_line_bot; 119 u32 vsync_off_top; 120 u32 vsync_off_bot; 121 }; 122 123 /** 124 * STI VTG structure 125 * 126 * @dev: pointer to device driver 127 * @np: device node 128 * @regs: register mapping 129 * @sync_params: synchronisation parameters used to generate timings 130 * @irq: VTG irq 131 * @irq_status: store the IRQ status value 132 * @notifier_list: notifier callback 133 * @crtc: the CRTC for vblank event 134 * @link: List node to link the structure in lookup list 135 */ 136 struct sti_vtg { 137 struct device *dev; 138 struct device_node *np; 139 void __iomem *regs; 140 struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT]; 141 int irq; 142 u32 irq_status; 143 struct raw_notifier_head notifier_list; 144 struct drm_crtc *crtc; 145 struct list_head link; 146 }; 147 148 static void vtg_register(struct sti_vtg *vtg) 149 { 150 list_add_tail(&vtg->link, &vtg_lookup); 151 } 152 153 struct sti_vtg *of_vtg_find(struct device_node *np) 154 { 155 struct sti_vtg *vtg; 156 157 list_for_each_entry(vtg, &vtg_lookup, link) { 158 if (vtg->np == np) 159 return vtg; 160 } 161 return NULL; 162 } 163 164 static void vtg_reset(struct sti_vtg *vtg) 165 { 166 writel(1, vtg->regs + VTG_DRST_AUTOC); 167 } 168 169 static void vtg_set_output_window(void __iomem *regs, 170 const struct drm_display_mode *mode) 171 { 172 u32 video_top_field_start; 173 u32 video_top_field_stop; 174 u32 video_bottom_field_start; 175 u32 video_bottom_field_stop; 176 u32 xstart = sti_vtg_get_pixel_number(*mode, 0); 177 u32 ystart = sti_vtg_get_line_number(*mode, 0); 178 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 179 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 180 181 /* Set output window to fit the display mode selected */ 182 video_top_field_start = (ystart << 16) | xstart; 183 video_top_field_stop = (ystop << 16) | xstop; 184 185 /* Only progressive supported for now */ 186 video_bottom_field_start = video_top_field_start; 187 video_bottom_field_stop = video_top_field_stop; 188 189 writel(video_top_field_start, regs + VTG_VID_TFO); 190 writel(video_top_field_stop, regs + VTG_VID_TFS); 191 writel(video_bottom_field_start, regs + VTG_VID_BFO); 192 writel(video_bottom_field_stop, regs + VTG_VID_BFS); 193 } 194 195 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, 196 int delay, 197 const struct drm_display_mode *mode) 198 { 199 long clocksperline, start, stop; 200 u32 risesync_top, fallsync_top; 201 u32 risesync_offs_top, fallsync_offs_top; 202 203 clocksperline = mode->htotal; 204 205 /* Get the hsync position */ 206 start = 0; 207 stop = mode->hsync_end - mode->hsync_start; 208 209 start += delay; 210 stop += delay; 211 212 if (start < 0) 213 start += clocksperline; 214 else if (start >= clocksperline) 215 start -= clocksperline; 216 217 if (stop < 0) 218 stop += clocksperline; 219 else if (stop >= clocksperline) 220 stop -= clocksperline; 221 222 sync->hsync = (stop << 16) | start; 223 224 /* Get the vsync position */ 225 if (delay >= 0) { 226 risesync_top = 1; 227 fallsync_top = risesync_top; 228 fallsync_top += mode->vsync_end - mode->vsync_start; 229 230 fallsync_offs_top = (u32)delay; 231 risesync_offs_top = (u32)delay; 232 } else { 233 risesync_top = mode->vtotal; 234 fallsync_top = mode->vsync_end - mode->vsync_start; 235 236 fallsync_offs_top = clocksperline + delay; 237 risesync_offs_top = clocksperline + delay; 238 } 239 240 sync->vsync_line_top = (fallsync_top << 16) | risesync_top; 241 sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top; 242 243 /* Only progressive supported for now */ 244 sync->vsync_line_bot = sync->vsync_line_top; 245 sync->vsync_off_bot = sync->vsync_off_top; 246 } 247 248 static void vtg_set_mode(struct sti_vtg *vtg, 249 int type, 250 struct sti_vtg_sync_params *sync, 251 const struct drm_display_mode *mode) 252 { 253 unsigned int i; 254 255 /* Set the number of clock cycles per line */ 256 writel(mode->htotal, vtg->regs + VTG_CLKLN); 257 258 /* Set Half Line Per Field (only progressive supported for now) */ 259 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 260 261 /* Program output window */ 262 vtg_set_output_window(vtg->regs, mode); 263 264 /* Set hsync and vsync position for HDMI */ 265 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode); 266 267 /* Set hsync and vsync position for HD DCS */ 268 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode); 269 270 /* Set hsync and vsync position for HDF */ 271 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode); 272 273 /* Set hsync and vsync position for DVO */ 274 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode); 275 276 /* Progam the syncs outputs */ 277 for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) { 278 writel(sync[i].hsync, 279 vtg->regs + vtg_regs_offs[i].h_hd); 280 writel(sync[i].vsync_line_top, 281 vtg->regs + vtg_regs_offs[i].top_v_vd); 282 writel(sync[i].vsync_line_bot, 283 vtg->regs + vtg_regs_offs[i].bot_v_vd); 284 writel(sync[i].vsync_off_top, 285 vtg->regs + vtg_regs_offs[i].top_v_hd); 286 writel(sync[i].vsync_off_bot, 287 vtg->regs + vtg_regs_offs[i].bot_v_hd); 288 } 289 290 /* mode */ 291 writel(type, vtg->regs + VTG_MODE); 292 } 293 294 static void vtg_enable_irq(struct sti_vtg *vtg) 295 { 296 /* clear interrupt status and mask */ 297 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); 298 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); 299 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); 300 } 301 302 void sti_vtg_set_config(struct sti_vtg *vtg, 303 const struct drm_display_mode *mode) 304 { 305 /* write configuration */ 306 vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode); 307 308 vtg_reset(vtg); 309 310 vtg_enable_irq(vtg); 311 } 312 313 /** 314 * sti_vtg_get_line_number 315 * 316 * @mode: display mode to be used 317 * @y: line 318 * 319 * Return the line number according to the display mode taking 320 * into account the Sync and Back Porch information. 321 * Video frame line numbers start at 1, y starts at 0. 322 * In interlaced modes the start line is the field line number of the odd 323 * field, but y is still defined as a progressive frame. 324 */ 325 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) 326 { 327 u32 start_line = mode.vtotal - mode.vsync_start + 1; 328 329 if (mode.flags & DRM_MODE_FLAG_INTERLACE) 330 start_line *= 2; 331 332 return start_line + y; 333 } 334 335 /** 336 * sti_vtg_get_pixel_number 337 * 338 * @mode: display mode to be used 339 * @x: row 340 * 341 * Return the pixel number according to the display mode taking 342 * into account the Sync and Back Porch information. 343 * Pixels are counted from 0. 344 */ 345 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) 346 { 347 return mode.htotal - mode.hsync_start + x; 348 } 349 350 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb, 351 struct drm_crtc *crtc) 352 { 353 vtg->crtc = crtc; 354 return raw_notifier_chain_register(&vtg->notifier_list, nb); 355 } 356 357 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb) 358 { 359 return raw_notifier_chain_unregister(&vtg->notifier_list, nb); 360 } 361 362 static irqreturn_t vtg_irq_thread(int irq, void *arg) 363 { 364 struct sti_vtg *vtg = arg; 365 u32 event; 366 367 event = (vtg->irq_status & VTG_IRQ_TOP) ? 368 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT; 369 370 raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc); 371 372 return IRQ_HANDLED; 373 } 374 375 static irqreturn_t vtg_irq(int irq, void *arg) 376 { 377 struct sti_vtg *vtg = arg; 378 379 vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS); 380 381 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); 382 383 /* force sync bus write */ 384 readl(vtg->regs + VTG_HOST_ITS); 385 386 return IRQ_WAKE_THREAD; 387 } 388 389 static int vtg_probe(struct platform_device *pdev) 390 { 391 struct device *dev = &pdev->dev; 392 struct sti_vtg *vtg; 393 struct resource *res; 394 int ret; 395 396 vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); 397 if (!vtg) 398 return -ENOMEM; 399 400 vtg->dev = dev; 401 vtg->np = pdev->dev.of_node; 402 403 /* Get Memory ressources */ 404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 405 if (!res) { 406 DRM_ERROR("Get memory resource failed\n"); 407 return -ENOMEM; 408 } 409 vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 410 if (!vtg->regs) { 411 DRM_ERROR("failed to remap I/O memory\n"); 412 return -ENOMEM; 413 } 414 415 vtg->irq = platform_get_irq(pdev, 0); 416 if (vtg->irq < 0) { 417 DRM_ERROR("Failed to get VTG interrupt\n"); 418 return vtg->irq; 419 } 420 421 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); 422 423 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, 424 vtg_irq_thread, IRQF_ONESHOT, 425 dev_name(dev), vtg); 426 if (ret < 0) { 427 DRM_ERROR("Failed to register VTG interrupt\n"); 428 return ret; 429 } 430 431 vtg_register(vtg); 432 platform_set_drvdata(pdev, vtg); 433 434 DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev)); 435 436 return 0; 437 } 438 439 static int vtg_remove(struct platform_device *pdev) 440 { 441 return 0; 442 } 443 444 static const struct of_device_id vtg_of_match[] = { 445 { .compatible = "st,vtg", }, 446 { /* sentinel */ } 447 }; 448 MODULE_DEVICE_TABLE(of, vtg_of_match); 449 450 struct platform_driver sti_vtg_driver = { 451 .driver = { 452 .name = "sti-vtg", 453 .owner = THIS_MODULE, 454 .of_match_table = vtg_of_match, 455 }, 456 .probe = vtg_probe, 457 .remove = vtg_remove, 458 }; 459 460 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 461 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 462 MODULE_LICENSE("GPL"); 463