1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 #include <linux/seq_file.h> 7 8 #include <drm/drmP.h> 9 10 #include "sti_plane.h" 11 #include "sti_vid.h" 12 #include "sti_vtg.h" 13 14 /* Registers */ 15 #define VID_CTL 0x00 16 #define VID_ALP 0x04 17 #define VID_CLF 0x08 18 #define VID_VPO 0x0C 19 #define VID_VPS 0x10 20 #define VID_KEY1 0x28 21 #define VID_KEY2 0x2C 22 #define VID_MPR0 0x30 23 #define VID_MPR1 0x34 24 #define VID_MPR2 0x38 25 #define VID_MPR3 0x3C 26 #define VID_MST 0x68 27 #define VID_BC 0x70 28 #define VID_TINT 0x74 29 #define VID_CSAT 0x78 30 31 /* Registers values */ 32 #define VID_CTL_IGNORE (BIT(31) | BIT(30)) 33 #define VID_CTL_PSI_ENABLE (BIT(2) | BIT(1) | BIT(0)) 34 #define VID_ALP_OPAQUE 0x00000080 35 #define VID_BC_DFLT 0x00008000 36 #define VID_TINT_DFLT 0x00000000 37 #define VID_CSAT_DFLT 0x00000080 38 /* YCbCr to RGB BT709: 39 * R = Y+1.5391Cr 40 * G = Y-0.4590Cr-0.1826Cb 41 * B = Y+1.8125Cb */ 42 #define VID_MPR0_BT709 0x0A800000 43 #define VID_MPR1_BT709 0x0AC50000 44 #define VID_MPR2_BT709 0x07150545 45 #define VID_MPR3_BT709 0x00000AE8 46 /* YCbCr to RGB BT709: 47 * R = Y+1.3711Cr 48 * G = Y-0.6992Cr-0.3359Cb 49 * B = Y+1.7344Cb 50 */ 51 #define VID_MPR0_BT601 0x0A800000 52 #define VID_MPR1_BT601 0x0AAF0000 53 #define VID_MPR2_BT601 0x094E0754 54 #define VID_MPR3_BT601 0x00000ADD 55 56 #define VID_MIN_HD_HEIGHT 720 57 58 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 59 readl(vid->regs + reg)) 60 61 static void vid_dbg_ctl(struct seq_file *s, int val) 62 { 63 val = val >> 30; 64 seq_puts(s, "\t"); 65 66 if (!(val & 1)) 67 seq_puts(s, "NOT "); 68 seq_puts(s, "ignored on main mixer - "); 69 70 if (!(val & 2)) 71 seq_puts(s, "NOT "); 72 seq_puts(s, "ignored on aux mixer"); 73 } 74 75 static void vid_dbg_vpo(struct seq_file *s, int val) 76 { 77 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); 78 } 79 80 static void vid_dbg_vps(struct seq_file *s, int val) 81 { 82 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); 83 } 84 85 static void vid_dbg_mst(struct seq_file *s, int val) 86 { 87 if (val & 1) 88 seq_puts(s, "\tBUFFER UNDERFLOW!"); 89 } 90 91 static int vid_dbg_show(struct seq_file *s, void *arg) 92 { 93 struct drm_info_node *node = s->private; 94 struct sti_vid *vid = (struct sti_vid *)node->info_ent->data; 95 struct drm_device *dev = node->minor->dev; 96 int ret; 97 98 ret = mutex_lock_interruptible(&dev->struct_mutex); 99 if (ret) 100 return ret; 101 102 seq_printf(s, "VID: (vaddr= 0x%p)", vid->regs); 103 104 DBGFS_DUMP(VID_CTL); 105 vid_dbg_ctl(s, readl(vid->regs + VID_CTL)); 106 DBGFS_DUMP(VID_ALP); 107 DBGFS_DUMP(VID_CLF); 108 DBGFS_DUMP(VID_VPO); 109 vid_dbg_vpo(s, readl(vid->regs + VID_VPO)); 110 DBGFS_DUMP(VID_VPS); 111 vid_dbg_vps(s, readl(vid->regs + VID_VPS)); 112 DBGFS_DUMP(VID_KEY1); 113 DBGFS_DUMP(VID_KEY2); 114 DBGFS_DUMP(VID_MPR0); 115 DBGFS_DUMP(VID_MPR1); 116 DBGFS_DUMP(VID_MPR2); 117 DBGFS_DUMP(VID_MPR3); 118 DBGFS_DUMP(VID_MST); 119 vid_dbg_mst(s, readl(vid->regs + VID_MST)); 120 DBGFS_DUMP(VID_BC); 121 DBGFS_DUMP(VID_TINT); 122 DBGFS_DUMP(VID_CSAT); 123 seq_puts(s, "\n"); 124 125 mutex_unlock(&dev->struct_mutex); 126 return 0; 127 } 128 129 static struct drm_info_list vid_debugfs_files[] = { 130 { "vid", vid_dbg_show, 0, NULL }, 131 }; 132 133 static int vid_debugfs_init(struct sti_vid *vid, struct drm_minor *minor) 134 { 135 unsigned int i; 136 137 for (i = 0; i < ARRAY_SIZE(vid_debugfs_files); i++) 138 vid_debugfs_files[i].data = vid; 139 140 return drm_debugfs_create_files(vid_debugfs_files, 141 ARRAY_SIZE(vid_debugfs_files), 142 minor->debugfs_root, minor); 143 } 144 145 void sti_vid_commit(struct sti_vid *vid, 146 struct drm_plane_state *state) 147 { 148 struct drm_crtc *crtc = state->crtc; 149 struct drm_display_mode *mode = &crtc->mode; 150 int dst_x = state->crtc_x; 151 int dst_y = state->crtc_y; 152 int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 153 int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 154 int src_h = state->src_h >> 16; 155 u32 val, ydo, xdo, yds, xds; 156 157 /* Input / output size 158 * Align to upper even value */ 159 dst_w = ALIGN(dst_w, 2); 160 dst_h = ALIGN(dst_h, 2); 161 162 /* Unmask */ 163 val = readl(vid->regs + VID_CTL); 164 val &= ~VID_CTL_IGNORE; 165 writel(val, vid->regs + VID_CTL); 166 167 ydo = sti_vtg_get_line_number(*mode, dst_y); 168 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 169 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 170 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 171 172 writel((ydo << 16) | xdo, vid->regs + VID_VPO); 173 writel((yds << 16) | xds, vid->regs + VID_VPS); 174 175 /* Color conversion parameters */ 176 if (src_h >= VID_MIN_HD_HEIGHT) { 177 writel(VID_MPR0_BT709, vid->regs + VID_MPR0); 178 writel(VID_MPR1_BT709, vid->regs + VID_MPR1); 179 writel(VID_MPR2_BT709, vid->regs + VID_MPR2); 180 writel(VID_MPR3_BT709, vid->regs + VID_MPR3); 181 } else { 182 writel(VID_MPR0_BT601, vid->regs + VID_MPR0); 183 writel(VID_MPR1_BT601, vid->regs + VID_MPR1); 184 writel(VID_MPR2_BT601, vid->regs + VID_MPR2); 185 writel(VID_MPR3_BT601, vid->regs + VID_MPR3); 186 } 187 } 188 189 void sti_vid_disable(struct sti_vid *vid) 190 { 191 u32 val; 192 193 /* Mask */ 194 val = readl(vid->regs + VID_CTL); 195 val |= VID_CTL_IGNORE; 196 writel(val, vid->regs + VID_CTL); 197 } 198 199 static void sti_vid_init(struct sti_vid *vid) 200 { 201 /* Enable PSI, Mask layer */ 202 writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL); 203 204 /* Opaque */ 205 writel(VID_ALP_OPAQUE, vid->regs + VID_ALP); 206 207 /* Brightness, contrast, tint, saturation */ 208 writel(VID_BC_DFLT, vid->regs + VID_BC); 209 writel(VID_TINT_DFLT, vid->regs + VID_TINT); 210 writel(VID_CSAT_DFLT, vid->regs + VID_CSAT); 211 } 212 213 struct sti_vid *sti_vid_create(struct device *dev, struct drm_device *drm_dev, 214 int id, void __iomem *baseaddr) 215 { 216 struct sti_vid *vid; 217 218 vid = devm_kzalloc(dev, sizeof(*vid), GFP_KERNEL); 219 if (!vid) { 220 DRM_ERROR("Failed to allocate memory for VID\n"); 221 return NULL; 222 } 223 224 vid->dev = dev; 225 vid->regs = baseaddr; 226 vid->id = id; 227 228 sti_vid_init(vid); 229 230 if (vid_debugfs_init(vid, drm_dev->primary)) 231 DRM_ERROR("VID debugfs setup failed\n"); 232 233 return vid; 234 } 235