1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #include <linux/component.h> 8 #include <linux/firmware.h> 9 #include <linux/reset.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_fb_cma_helper.h> 14 #include <drm/drm_gem_cma_helper.h> 15 16 #include "sti_compositor.h" 17 #include "sti_hqvdp_lut.h" 18 #include "sti_plane.h" 19 #include "sti_vtg.h" 20 #include "sti_drv.h" 21 22 /* Firmware name */ 23 #define HQVDP_FMW_NAME "hqvdp-stih407.bin" 24 25 /* Regs address */ 26 #define HQVDP_DMEM 0x00000000 /* 0x00000000 */ 27 #define HQVDP_PMEM 0x00040000 /* 0x00040000 */ 28 #define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */ 29 #define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */ 30 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */ 31 #define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */ 32 #define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */ 33 #define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */ 34 #define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */ 35 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */ 36 #define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */ 37 #define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */ 38 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */ 39 #define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */ 40 #define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */ 41 #define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */ 42 #define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */ 43 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */ 44 #define HQVDP_MBX 0x000E4000 /* 0x000E4000 */ 45 #define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */ 46 #define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */ 47 #define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */ 48 #define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */ 49 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */ 50 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */ 51 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */ 52 #define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */ 53 #define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */ 54 #define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */ 55 #define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */ 56 57 /* Plugs config */ 58 #define PLUG_CONTROL_ENABLE 0x00000001 59 #define PLUG_PAGE_SIZE_256 0x00000002 60 #define PLUG_MIN_OPC_8 0x00000003 61 #define PLUG_MAX_OPC_64 0x00000006 62 #define PLUG_MAX_CHK_2X 0x00000001 63 #define PLUG_MAX_MSG_1X 0x00000000 64 #define PLUG_MIN_SPACE_1 0x00000000 65 66 /* SW reset CTRL */ 67 #define SW_RESET_CTRL_FULL BIT(0) 68 #define SW_RESET_CTRL_CORE BIT(1) 69 70 /* Startup ctrl 1 */ 71 #define STARTUP_CTRL1_RST_DONE BIT(0) 72 #define STARTUP_CTRL1_AUTH_IDLE BIT(2) 73 74 /* Startup ctrl 2 */ 75 #define STARTUP_CTRL2_FETCH_EN BIT(1) 76 77 /* Info xP70 */ 78 #define INFO_XP70_FW_READY BIT(15) 79 #define INFO_XP70_FW_PROCESSING BIT(14) 80 #define INFO_XP70_FW_INITQUEUES BIT(13) 81 82 /* SOFT_VSYNC */ 83 #define SOFT_VSYNC_HW 0x00000000 84 #define SOFT_VSYNC_SW_CMD 0x00000001 85 #define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003 86 87 /* Reset & boot poll config */ 88 #define POLL_MAX_ATTEMPT 50 89 #define POLL_DELAY_MS 20 90 91 #define SCALE_FACTOR 8192 92 #define SCALE_MAX_FOR_LEG_LUT_F 4096 93 #define SCALE_MAX_FOR_LEG_LUT_E 4915 94 #define SCALE_MAX_FOR_LEG_LUT_D 6654 95 #define SCALE_MAX_FOR_LEG_LUT_C 8192 96 97 enum sti_hvsrc_orient { 98 HVSRC_HORI, 99 HVSRC_VERT 100 }; 101 102 /* Command structures */ 103 struct sti_hqvdp_top { 104 u32 config; 105 u32 mem_format; 106 u32 current_luma; 107 u32 current_enh_luma; 108 u32 current_right_luma; 109 u32 current_enh_right_luma; 110 u32 current_chroma; 111 u32 current_enh_chroma; 112 u32 current_right_chroma; 113 u32 current_enh_right_chroma; 114 u32 output_luma; 115 u32 output_chroma; 116 u32 luma_src_pitch; 117 u32 luma_enh_src_pitch; 118 u32 luma_right_src_pitch; 119 u32 luma_enh_right_src_pitch; 120 u32 chroma_src_pitch; 121 u32 chroma_enh_src_pitch; 122 u32 chroma_right_src_pitch; 123 u32 chroma_enh_right_src_pitch; 124 u32 luma_processed_pitch; 125 u32 chroma_processed_pitch; 126 u32 input_frame_size; 127 u32 input_viewport_ori; 128 u32 input_viewport_ori_right; 129 u32 input_viewport_size; 130 u32 left_view_border_width; 131 u32 right_view_border_width; 132 u32 left_view_3d_offset_width; 133 u32 right_view_3d_offset_width; 134 u32 side_stripe_color; 135 u32 crc_reset_ctrl; 136 }; 137 138 /* Configs for interlaced : no IT, no pass thru, 3 fields */ 139 #define TOP_CONFIG_INTER_BTM 0x00000000 140 #define TOP_CONFIG_INTER_TOP 0x00000002 141 142 /* Config for progressive : no IT, no pass thru, 3 fields */ 143 #define TOP_CONFIG_PROGRESSIVE 0x00000001 144 145 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */ 146 #define TOP_MEM_FORMAT_DFLT 0x00018060 147 148 /* Min/Max size */ 149 #define MAX_WIDTH 0x1FFF 150 #define MAX_HEIGHT 0x0FFF 151 #define MIN_WIDTH 0x0030 152 #define MIN_HEIGHT 0x0010 153 154 struct sti_hqvdp_vc1re { 155 u32 ctrl_prv_csdi; 156 u32 ctrl_cur_csdi; 157 u32 ctrl_nxt_csdi; 158 u32 ctrl_cur_fmd; 159 u32 ctrl_nxt_fmd; 160 }; 161 162 struct sti_hqvdp_fmd { 163 u32 config; 164 u32 viewport_ori; 165 u32 viewport_size; 166 u32 next_next_luma; 167 u32 next_next_right_luma; 168 u32 next_next_next_luma; 169 u32 next_next_next_right_luma; 170 u32 threshold_scd; 171 u32 threshold_rfd; 172 u32 threshold_move; 173 u32 threshold_cfd; 174 }; 175 176 struct sti_hqvdp_csdi { 177 u32 config; 178 u32 config2; 179 u32 dcdi_config; 180 u32 prev_luma; 181 u32 prev_enh_luma; 182 u32 prev_right_luma; 183 u32 prev_enh_right_luma; 184 u32 next_luma; 185 u32 next_enh_luma; 186 u32 next_right_luma; 187 u32 next_enh_right_luma; 188 u32 prev_chroma; 189 u32 prev_enh_chroma; 190 u32 prev_right_chroma; 191 u32 prev_enh_right_chroma; 192 u32 next_chroma; 193 u32 next_enh_chroma; 194 u32 next_right_chroma; 195 u32 next_enh_right_chroma; 196 u32 prev_motion; 197 u32 prev_right_motion; 198 u32 cur_motion; 199 u32 cur_right_motion; 200 u32 next_motion; 201 u32 next_right_motion; 202 }; 203 204 /* Config for progressive: by pass */ 205 #define CSDI_CONFIG_PROG 0x00000000 206 /* Config for directional deinterlacing without motion */ 207 #define CSDI_CONFIG_INTER_DIR 0x00000016 208 /* Additional configs for fader, blender, motion,... deinterlace algorithms */ 209 #define CSDI_CONFIG2_DFLT 0x000001B3 210 #define CSDI_DCDI_CONFIG_DFLT 0x00203803 211 212 struct sti_hqvdp_hvsrc { 213 u32 hor_panoramic_ctrl; 214 u32 output_picture_size; 215 u32 init_horizontal; 216 u32 init_vertical; 217 u32 param_ctrl; 218 u32 yh_coef[NB_COEF]; 219 u32 ch_coef[NB_COEF]; 220 u32 yv_coef[NB_COEF]; 221 u32 cv_coef[NB_COEF]; 222 u32 hori_shift; 223 u32 vert_shift; 224 }; 225 226 /* Default ParamCtrl: all controls enabled */ 227 #define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF 228 229 struct sti_hqvdp_iqi { 230 u32 config; 231 u32 demo_wind_size; 232 u32 pk_config; 233 u32 coeff0_coeff1; 234 u32 coeff2_coeff3; 235 u32 coeff4; 236 u32 pk_lut; 237 u32 pk_gain; 238 u32 pk_coring_level; 239 u32 cti_config; 240 u32 le_config; 241 u32 le_lut[64]; 242 u32 con_bri; 243 u32 sat_gain; 244 u32 pxf_conf; 245 u32 default_color; 246 }; 247 248 /* Default Config : IQI bypassed */ 249 #define IQI_CONFIG_DFLT 0x00000001 250 /* Default Contrast & Brightness gain = 256 */ 251 #define IQI_CON_BRI_DFLT 0x00000100 252 /* Default Saturation gain = 256 */ 253 #define IQI_SAT_GAIN_DFLT 0x00000100 254 /* Default PxfConf : P2I bypassed */ 255 #define IQI_PXF_CONF_DFLT 0x00000001 256 257 struct sti_hqvdp_top_status { 258 u32 processing_time; 259 u32 input_y_crc; 260 u32 input_uv_crc; 261 }; 262 263 struct sti_hqvdp_fmd_status { 264 u32 fmd_repeat_move_status; 265 u32 fmd_scene_count_status; 266 u32 cfd_sum; 267 u32 field_sum; 268 u32 next_y_fmd_crc; 269 u32 next_next_y_fmd_crc; 270 u32 next_next_next_y_fmd_crc; 271 }; 272 273 struct sti_hqvdp_csdi_status { 274 u32 prev_y_csdi_crc; 275 u32 cur_y_csdi_crc; 276 u32 next_y_csdi_crc; 277 u32 prev_uv_csdi_crc; 278 u32 cur_uv_csdi_crc; 279 u32 next_uv_csdi_crc; 280 u32 y_csdi_crc; 281 u32 uv_csdi_crc; 282 u32 uv_cup_crc; 283 u32 mot_csdi_crc; 284 u32 mot_cur_csdi_crc; 285 u32 mot_prev_csdi_crc; 286 }; 287 288 struct sti_hqvdp_hvsrc_status { 289 u32 y_hvsrc_crc; 290 u32 u_hvsrc_crc; 291 u32 v_hvsrc_crc; 292 }; 293 294 struct sti_hqvdp_iqi_status { 295 u32 pxf_it_status; 296 u32 y_iqi_crc; 297 u32 u_iqi_crc; 298 u32 v_iqi_crc; 299 }; 300 301 /* Main commands. We use 2 commands one being processed by the firmware, one 302 * ready to be fetched upon next Vsync*/ 303 #define NB_VDP_CMD 2 304 305 struct sti_hqvdp_cmd { 306 struct sti_hqvdp_top top; 307 struct sti_hqvdp_vc1re vc1re; 308 struct sti_hqvdp_fmd fmd; 309 struct sti_hqvdp_csdi csdi; 310 struct sti_hqvdp_hvsrc hvsrc; 311 struct sti_hqvdp_iqi iqi; 312 struct sti_hqvdp_top_status top_status; 313 struct sti_hqvdp_fmd_status fmd_status; 314 struct sti_hqvdp_csdi_status csdi_status; 315 struct sti_hqvdp_hvsrc_status hvsrc_status; 316 struct sti_hqvdp_iqi_status iqi_status; 317 }; 318 319 /* 320 * STI HQVDP structure 321 * 322 * @dev: driver device 323 * @drm_dev: the drm device 324 * @regs: registers 325 * @plane: plane structure for hqvdp it self 326 * @clk: IP clock 327 * @clk_pix_main: pix main clock 328 * @reset: reset control 329 * @vtg_nb: notifier to handle VTG Vsync 330 * @btm_field_pending: is there any bottom field (interlaced frame) to display 331 * @hqvdp_cmd: buffer of commands 332 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd 333 * @vtg: vtg for main data path 334 * @xp70_initialized: true if xp70 is already initialized 335 * @vtg_registered: true if registered to VTG 336 */ 337 struct sti_hqvdp { 338 struct device *dev; 339 struct drm_device *drm_dev; 340 void __iomem *regs; 341 struct sti_plane plane; 342 struct clk *clk; 343 struct clk *clk_pix_main; 344 struct reset_control *reset; 345 struct notifier_block vtg_nb; 346 bool btm_field_pending; 347 void *hqvdp_cmd; 348 u32 hqvdp_cmd_paddr; 349 struct sti_vtg *vtg; 350 bool xp70_initialized; 351 bool vtg_registered; 352 }; 353 354 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane) 355 356 static const uint32_t hqvdp_supported_formats[] = { 357 DRM_FORMAT_NV12, 358 }; 359 360 /** 361 * sti_hqvdp_get_free_cmd 362 * @hqvdp: hqvdp structure 363 * 364 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW. 365 * 366 * RETURNS: 367 * the offset of the command to be used. 368 * -1 in error cases 369 */ 370 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp) 371 { 372 u32 curr_cmd, next_cmd; 373 u32 cmd = hqvdp->hqvdp_cmd_paddr; 374 int i; 375 376 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 377 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 378 379 for (i = 0; i < NB_VDP_CMD; i++) { 380 if ((cmd != curr_cmd) && (cmd != next_cmd)) 381 return i * sizeof(struct sti_hqvdp_cmd); 382 cmd += sizeof(struct sti_hqvdp_cmd); 383 } 384 385 return -1; 386 } 387 388 /** 389 * sti_hqvdp_get_curr_cmd 390 * @hqvdp: hqvdp structure 391 * 392 * Look for the hqvdp_cmd that is being used by the FW. 393 * 394 * RETURNS: 395 * the offset of the command to be used. 396 * -1 in error cases 397 */ 398 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp) 399 { 400 u32 curr_cmd; 401 u32 cmd = hqvdp->hqvdp_cmd_paddr; 402 unsigned int i; 403 404 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 405 406 for (i = 0; i < NB_VDP_CMD; i++) { 407 if (cmd == curr_cmd) 408 return i * sizeof(struct sti_hqvdp_cmd); 409 410 cmd += sizeof(struct sti_hqvdp_cmd); 411 } 412 413 return -1; 414 } 415 416 /** 417 * sti_hqvdp_get_next_cmd 418 * @hqvdp: hqvdp structure 419 * 420 * Look for the next hqvdp_cmd that will be used by the FW. 421 * 422 * RETURNS: 423 * the offset of the next command that will be used. 424 * -1 in error cases 425 */ 426 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp) 427 { 428 int next_cmd; 429 dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr; 430 unsigned int i; 431 432 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 433 434 for (i = 0; i < NB_VDP_CMD; i++) { 435 if (cmd == next_cmd) 436 return i * sizeof(struct sti_hqvdp_cmd); 437 438 cmd += sizeof(struct sti_hqvdp_cmd); 439 } 440 441 return -1; 442 } 443 444 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 445 readl(hqvdp->regs + reg)) 446 447 static const char *hqvdp_dbg_get_lut(u32 *coef) 448 { 449 if (!memcmp(coef, coef_lut_a_legacy, 16)) 450 return "LUT A"; 451 if (!memcmp(coef, coef_lut_b, 16)) 452 return "LUT B"; 453 if (!memcmp(coef, coef_lut_c_y_legacy, 16)) 454 return "LUT C Y"; 455 if (!memcmp(coef, coef_lut_c_c_legacy, 16)) 456 return "LUT C C"; 457 if (!memcmp(coef, coef_lut_d_y_legacy, 16)) 458 return "LUT D Y"; 459 if (!memcmp(coef, coef_lut_d_c_legacy, 16)) 460 return "LUT D C"; 461 if (!memcmp(coef, coef_lut_e_y_legacy, 16)) 462 return "LUT E Y"; 463 if (!memcmp(coef, coef_lut_e_c_legacy, 16)) 464 return "LUT E C"; 465 if (!memcmp(coef, coef_lut_f_y_legacy, 16)) 466 return "LUT F Y"; 467 if (!memcmp(coef, coef_lut_f_c_legacy, 16)) 468 return "LUT F C"; 469 return "<UNKNOWN>"; 470 } 471 472 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c) 473 { 474 int src_w, src_h, dst_w, dst_h; 475 476 seq_puts(s, "\n\tTOP:"); 477 seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config); 478 switch (c->top.config) { 479 case TOP_CONFIG_PROGRESSIVE: 480 seq_puts(s, "\tProgressive"); 481 break; 482 case TOP_CONFIG_INTER_TOP: 483 seq_puts(s, "\tInterlaced, top field"); 484 break; 485 case TOP_CONFIG_INTER_BTM: 486 seq_puts(s, "\tInterlaced, bottom field"); 487 break; 488 default: 489 seq_puts(s, "\t<UNKNOWN>"); 490 break; 491 } 492 493 seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format); 494 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma); 495 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma); 496 seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch); 497 seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch", 498 c->top.chroma_src_pitch); 499 seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize", 500 c->top.input_frame_size); 501 seq_printf(s, "\t%dx%d", 502 c->top.input_frame_size & 0x0000FFFF, 503 c->top.input_frame_size >> 16); 504 seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize", 505 c->top.input_viewport_size); 506 src_w = c->top.input_viewport_size & 0x0000FFFF; 507 src_h = c->top.input_viewport_size >> 16; 508 seq_printf(s, "\t%dx%d", src_w, src_h); 509 510 seq_puts(s, "\n\tHVSRC:"); 511 seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize", 512 c->hvsrc.output_picture_size); 513 dst_w = c->hvsrc.output_picture_size & 0x0000FFFF; 514 dst_h = c->hvsrc.output_picture_size >> 16; 515 seq_printf(s, "\t%dx%d", dst_w, dst_h); 516 seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl); 517 518 seq_printf(s, "\n\t %-20s %s", "yh_coef", 519 hqvdp_dbg_get_lut(c->hvsrc.yh_coef)); 520 seq_printf(s, "\n\t %-20s %s", "ch_coef", 521 hqvdp_dbg_get_lut(c->hvsrc.ch_coef)); 522 seq_printf(s, "\n\t %-20s %s", "yv_coef", 523 hqvdp_dbg_get_lut(c->hvsrc.yv_coef)); 524 seq_printf(s, "\n\t %-20s %s", "cv_coef", 525 hqvdp_dbg_get_lut(c->hvsrc.cv_coef)); 526 527 seq_printf(s, "\n\t %-20s", "ScaleH"); 528 if (dst_w > src_w) 529 seq_printf(s, " %d/1", dst_w / src_w); 530 else 531 seq_printf(s, " 1/%d", src_w / dst_w); 532 533 seq_printf(s, "\n\t %-20s", "tScaleV"); 534 if (dst_h > src_h) 535 seq_printf(s, " %d/1", dst_h / src_h); 536 else 537 seq_printf(s, " 1/%d", src_h / dst_h); 538 539 seq_puts(s, "\n\tCSDI:"); 540 seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config); 541 switch (c->csdi.config) { 542 case CSDI_CONFIG_PROG: 543 seq_puts(s, "Bypass"); 544 break; 545 case CSDI_CONFIG_INTER_DIR: 546 seq_puts(s, "Deinterlace, directional"); 547 break; 548 default: 549 seq_puts(s, "<UNKNOWN>"); 550 break; 551 } 552 553 seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2); 554 seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config); 555 } 556 557 static int hqvdp_dbg_show(struct seq_file *s, void *data) 558 { 559 struct drm_info_node *node = s->private; 560 struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data; 561 int cmd, cmd_offset, infoxp70; 562 void *virt; 563 564 seq_printf(s, "%s: (vaddr = 0x%p)", 565 sti_plane_to_str(&hqvdp->plane), hqvdp->regs); 566 567 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70); 568 DBGFS_DUMP(HQVDP_MBX_INFO_HOST); 569 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST); 570 DBGFS_DUMP(HQVDP_MBX_INFO_XP70); 571 infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70); 572 seq_puts(s, "\tFirmware state: "); 573 if (infoxp70 & INFO_XP70_FW_READY) 574 seq_puts(s, "idle and ready"); 575 else if (infoxp70 & INFO_XP70_FW_PROCESSING) 576 seq_puts(s, "processing a picture"); 577 else if (infoxp70 & INFO_XP70_FW_INITQUEUES) 578 seq_puts(s, "programming queues"); 579 else 580 seq_puts(s, "NOT READY"); 581 582 DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL); 583 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1); 584 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 585 & STARTUP_CTRL1_RST_DONE) 586 seq_puts(s, "\tReset is done"); 587 else 588 seq_puts(s, "\tReset is NOT done"); 589 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2); 590 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2) 591 & STARTUP_CTRL2_FETCH_EN) 592 seq_puts(s, "\tFetch is enabled"); 593 else 594 seq_puts(s, "\tFetch is NOT enabled"); 595 DBGFS_DUMP(HQVDP_MBX_GP_STATUS); 596 DBGFS_DUMP(HQVDP_MBX_NEXT_CMD); 597 DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD); 598 DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC); 599 if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3)) 600 seq_puts(s, "\tHW Vsync"); 601 else 602 seq_puts(s, "\tSW Vsync ?!?!"); 603 604 /* Last command */ 605 cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 606 cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp); 607 if (cmd_offset == -1) { 608 seq_puts(s, "\n\n Last command: unknown"); 609 } else { 610 virt = hqvdp->hqvdp_cmd + cmd_offset; 611 seq_printf(s, "\n\n Last command: address @ 0x%x (0x%p)", 612 cmd, virt); 613 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 614 } 615 616 /* Next command */ 617 cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 618 cmd_offset = sti_hqvdp_get_next_cmd(hqvdp); 619 if (cmd_offset == -1) { 620 seq_puts(s, "\n\n Next command: unknown"); 621 } else { 622 virt = hqvdp->hqvdp_cmd + cmd_offset; 623 seq_printf(s, "\n\n Next command address: @ 0x%x (0x%p)", 624 cmd, virt); 625 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 626 } 627 628 seq_puts(s, "\n"); 629 630 return 0; 631 } 632 633 static struct drm_info_list hqvdp_debugfs_files[] = { 634 { "hqvdp", hqvdp_dbg_show, 0, NULL }, 635 }; 636 637 static int hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor) 638 { 639 unsigned int i; 640 641 for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++) 642 hqvdp_debugfs_files[i].data = hqvdp; 643 644 return drm_debugfs_create_files(hqvdp_debugfs_files, 645 ARRAY_SIZE(hqvdp_debugfs_files), 646 minor->debugfs_root, minor); 647 } 648 649 /** 650 * sti_hqvdp_update_hvsrc 651 * @orient: horizontal or vertical 652 * @scale: scaling/zoom factor 653 * @hvsrc: the structure containing the LUT coef 654 * 655 * Update the Y and C Lut coef, as well as the shift param 656 * 657 * RETURNS: 658 * None. 659 */ 660 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale, 661 struct sti_hqvdp_hvsrc *hvsrc) 662 { 663 const int *coef_c, *coef_y; 664 int shift_c, shift_y; 665 666 /* Get the appropriate coef tables */ 667 if (scale < SCALE_MAX_FOR_LEG_LUT_F) { 668 coef_y = coef_lut_f_y_legacy; 669 coef_c = coef_lut_f_c_legacy; 670 shift_y = SHIFT_LUT_F_Y_LEGACY; 671 shift_c = SHIFT_LUT_F_C_LEGACY; 672 } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) { 673 coef_y = coef_lut_e_y_legacy; 674 coef_c = coef_lut_e_c_legacy; 675 shift_y = SHIFT_LUT_E_Y_LEGACY; 676 shift_c = SHIFT_LUT_E_C_LEGACY; 677 } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) { 678 coef_y = coef_lut_d_y_legacy; 679 coef_c = coef_lut_d_c_legacy; 680 shift_y = SHIFT_LUT_D_Y_LEGACY; 681 shift_c = SHIFT_LUT_D_C_LEGACY; 682 } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) { 683 coef_y = coef_lut_c_y_legacy; 684 coef_c = coef_lut_c_c_legacy; 685 shift_y = SHIFT_LUT_C_Y_LEGACY; 686 shift_c = SHIFT_LUT_C_C_LEGACY; 687 } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) { 688 coef_y = coef_c = coef_lut_b; 689 shift_y = shift_c = SHIFT_LUT_B; 690 } else { 691 coef_y = coef_c = coef_lut_a_legacy; 692 shift_y = shift_c = SHIFT_LUT_A_LEGACY; 693 } 694 695 if (orient == HVSRC_HORI) { 696 hvsrc->hori_shift = (shift_c << 16) | shift_y; 697 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef)); 698 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef)); 699 } else { 700 hvsrc->vert_shift = (shift_c << 16) | shift_y; 701 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef)); 702 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef)); 703 } 704 } 705 706 /** 707 * sti_hqvdp_check_hw_scaling 708 * @hqvdp: hqvdp pointer 709 * @mode: display mode with timing constraints 710 * @src_w: source width 711 * @src_h: source height 712 * @dst_w: destination width 713 * @dst_h: destination height 714 * 715 * Check if the HW is able to perform the scaling request 716 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where: 717 * Zy = OutputHeight / InputHeight 718 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp) 719 * Tx : Total video mode horizontal resolution 720 * IPClock : HQVDP IP clock (Mhz) 721 * MaxNbCycles: max(InputWidth, OutputWidth) 722 * Cp: Video mode pixel clock (Mhz) 723 * 724 * RETURNS: 725 * True if the HW can scale. 726 */ 727 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp, 728 struct drm_display_mode *mode, 729 int src_w, int src_h, 730 int dst_w, int dst_h) 731 { 732 unsigned long lfw; 733 unsigned int inv_zy; 734 735 lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000); 736 lfw /= max(src_w, dst_w) * mode->clock / 1000; 737 738 inv_zy = DIV_ROUND_UP(src_h, dst_h); 739 740 return (inv_zy <= lfw) ? true : false; 741 } 742 743 /** 744 * sti_hqvdp_disable 745 * @hqvdp: hqvdp pointer 746 * 747 * Disables the HQVDP plane 748 */ 749 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp) 750 { 751 int i; 752 753 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane)); 754 755 /* Unregister VTG Vsync callback */ 756 if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb)) 757 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 758 759 /* Set next cmd to NULL */ 760 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 761 762 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 763 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 764 & INFO_XP70_FW_READY) 765 break; 766 msleep(POLL_DELAY_MS); 767 } 768 769 /* VTG can stop now */ 770 clk_disable_unprepare(hqvdp->clk_pix_main); 771 772 if (i == POLL_MAX_ATTEMPT) 773 DRM_ERROR("XP70 could not revert to idle\n"); 774 775 hqvdp->plane.status = STI_PLANE_DISABLED; 776 hqvdp->vtg_registered = false; 777 } 778 779 /** 780 * sti_vdp_vtg_cb 781 * @nb: notifier block 782 * @evt: event message 783 * @data: private data 784 * 785 * Handle VTG Vsync event, display pending bottom field 786 * 787 * RETURNS: 788 * 0 on success. 789 */ 790 static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data) 791 { 792 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb); 793 int btm_cmd_offset, top_cmd_offest; 794 struct sti_hqvdp_cmd *btm_cmd, *top_cmd; 795 796 if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) { 797 DRM_DEBUG_DRIVER("Unknown event\n"); 798 return 0; 799 } 800 801 if (hqvdp->plane.status == STI_PLANE_FLUSHING) { 802 /* disable need to be synchronize on vsync event */ 803 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 804 sti_plane_to_str(&hqvdp->plane)); 805 806 sti_hqvdp_disable(hqvdp); 807 } 808 809 if (hqvdp->btm_field_pending) { 810 /* Create the btm field command from the current one */ 811 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 812 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp); 813 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) { 814 DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n"); 815 return -EBUSY; 816 } 817 818 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset; 819 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest; 820 821 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd)); 822 823 btm_cmd->top.config = TOP_CONFIG_INTER_BTM; 824 btm_cmd->top.current_luma += 825 btm_cmd->top.luma_src_pitch / 2; 826 btm_cmd->top.current_chroma += 827 btm_cmd->top.chroma_src_pitch / 2; 828 829 /* Post the command to mailbox */ 830 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset, 831 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 832 833 hqvdp->btm_field_pending = false; 834 835 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 836 __func__, hqvdp->hqvdp_cmd_paddr); 837 838 sti_plane_update_fps(&hqvdp->plane, false, true); 839 } 840 841 return 0; 842 } 843 844 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp) 845 { 846 int size; 847 dma_addr_t dma_addr; 848 849 hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb; 850 851 /* Allocate memory for the VDP commands */ 852 size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd); 853 hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size, 854 &dma_addr, 855 GFP_KERNEL | GFP_DMA); 856 if (!hqvdp->hqvdp_cmd) { 857 DRM_ERROR("Failed to allocate memory for VDP cmd\n"); 858 return; 859 } 860 861 hqvdp->hqvdp_cmd_paddr = (u32)dma_addr; 862 memset(hqvdp->hqvdp_cmd, 0, size); 863 } 864 865 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp) 866 { 867 /* Configure Plugs (same for RD & WR) */ 868 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE); 869 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC); 870 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC); 871 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK); 872 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG); 873 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE); 874 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL); 875 876 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE); 877 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC); 878 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC); 879 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK); 880 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG); 881 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE); 882 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL); 883 } 884 885 /** 886 * sti_hqvdp_start_xp70 887 * @hqvdp: hqvdp pointer 888 * 889 * Run the xP70 initialization sequence 890 */ 891 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp) 892 { 893 const struct firmware *firmware; 894 u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem; 895 u8 *data; 896 int i; 897 struct fw_header { 898 int rd_size; 899 int wr_size; 900 int pmem_size; 901 int dmem_size; 902 } *header; 903 904 DRM_DEBUG_DRIVER("\n"); 905 906 if (hqvdp->xp70_initialized) { 907 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n"); 908 return; 909 } 910 911 /* Request firmware */ 912 if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) { 913 DRM_ERROR("Can't get HQVDP firmware\n"); 914 return; 915 } 916 917 /* Check firmware parts */ 918 if (!firmware) { 919 DRM_ERROR("Firmware not available\n"); 920 return; 921 } 922 923 header = (struct fw_header *)firmware->data; 924 if (firmware->size < sizeof(*header)) { 925 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size); 926 goto out; 927 } 928 if ((sizeof(*header) + header->rd_size + header->wr_size + 929 header->pmem_size + header->dmem_size) != firmware->size) { 930 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n", 931 sizeof(*header), header->rd_size, header->wr_size, 932 header->pmem_size, header->dmem_size, 933 firmware->size); 934 goto out; 935 } 936 937 data = (u8 *)firmware->data; 938 data += sizeof(*header); 939 fw_rd_plug = (void *)data; 940 data += header->rd_size; 941 fw_wr_plug = (void *)data; 942 data += header->wr_size; 943 fw_pmem = (void *)data; 944 data += header->pmem_size; 945 fw_dmem = (void *)data; 946 947 /* Enable clock */ 948 if (clk_prepare_enable(hqvdp->clk)) 949 DRM_ERROR("Failed to prepare/enable HQVDP clk\n"); 950 951 /* Reset */ 952 writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL); 953 954 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 955 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 956 & STARTUP_CTRL1_RST_DONE) 957 break; 958 msleep(POLL_DELAY_MS); 959 } 960 if (i == POLL_MAX_ATTEMPT) { 961 DRM_ERROR("Could not reset\n"); 962 goto out; 963 } 964 965 /* Init Read & Write plugs */ 966 for (i = 0; i < header->rd_size / 4; i++) 967 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4); 968 for (i = 0; i < header->wr_size / 4; i++) 969 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4); 970 971 sti_hqvdp_init_plugs(hqvdp); 972 973 /* Authorize Idle Mode */ 974 writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1); 975 976 /* Prevent VTG interruption during the boot */ 977 writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 978 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 979 980 /* Download PMEM & DMEM */ 981 for (i = 0; i < header->pmem_size / 4; i++) 982 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4); 983 for (i = 0; i < header->dmem_size / 4; i++) 984 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4); 985 986 /* Enable fetch */ 987 writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2); 988 989 /* Wait end of boot */ 990 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 991 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 992 & INFO_XP70_FW_READY) 993 break; 994 msleep(POLL_DELAY_MS); 995 } 996 if (i == POLL_MAX_ATTEMPT) { 997 DRM_ERROR("Could not boot\n"); 998 goto out; 999 } 1000 1001 /* Launch Vsync */ 1002 writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 1003 1004 DRM_INFO("HQVDP XP70 initialized\n"); 1005 1006 hqvdp->xp70_initialized = true; 1007 1008 out: 1009 release_firmware(firmware); 1010 } 1011 1012 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane, 1013 struct drm_plane_state *state) 1014 { 1015 struct sti_plane *plane = to_sti_plane(drm_plane); 1016 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1017 struct drm_crtc *crtc = state->crtc; 1018 struct drm_framebuffer *fb = state->fb; 1019 struct drm_crtc_state *crtc_state; 1020 struct drm_display_mode *mode; 1021 int dst_x, dst_y, dst_w, dst_h; 1022 int src_x, src_y, src_w, src_h; 1023 1024 /* no need for further checks if the plane is being disabled */ 1025 if (!crtc || !fb) 1026 return 0; 1027 1028 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 1029 mode = &crtc_state->mode; 1030 dst_x = state->crtc_x; 1031 dst_y = state->crtc_y; 1032 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1033 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1034 /* src_x are in 16.16 format */ 1035 src_x = state->src_x >> 16; 1036 src_y = state->src_y >> 16; 1037 src_w = state->src_w >> 16; 1038 src_h = state->src_h >> 16; 1039 1040 if (mode->clock && !sti_hqvdp_check_hw_scaling(hqvdp, mode, 1041 src_w, src_h, 1042 dst_w, dst_h)) { 1043 DRM_ERROR("Scaling beyond HW capabilities\n"); 1044 return -EINVAL; 1045 } 1046 1047 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 1048 DRM_ERROR("Can't get CMA GEM object for fb\n"); 1049 return -EINVAL; 1050 } 1051 1052 /* 1053 * Input / output size 1054 * Align to upper even value 1055 */ 1056 dst_w = ALIGN(dst_w, 2); 1057 dst_h = ALIGN(dst_h, 2); 1058 1059 if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) || 1060 (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) || 1061 (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) || 1062 (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) { 1063 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n", 1064 src_w, src_h, 1065 dst_w, dst_h); 1066 return -EINVAL; 1067 } 1068 1069 if (!hqvdp->xp70_initialized) 1070 /* Start HQVDP XP70 coprocessor */ 1071 sti_hqvdp_start_xp70(hqvdp); 1072 1073 if (!hqvdp->vtg_registered) { 1074 /* Prevent VTG shutdown */ 1075 if (clk_prepare_enable(hqvdp->clk_pix_main)) { 1076 DRM_ERROR("Failed to prepare/enable pix main clk\n"); 1077 return -EINVAL; 1078 } 1079 1080 /* Register VTG Vsync callback to handle bottom fields */ 1081 if (sti_vtg_register_client(hqvdp->vtg, 1082 &hqvdp->vtg_nb, 1083 crtc)) { 1084 DRM_ERROR("Cannot register VTG notifier\n"); 1085 return -EINVAL; 1086 } 1087 hqvdp->vtg_registered = true; 1088 } 1089 1090 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 1091 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)), 1092 drm_plane->base.id, sti_plane_to_str(plane)); 1093 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 1094 sti_plane_to_str(plane), 1095 dst_w, dst_h, dst_x, dst_y, 1096 src_w, src_h, src_x, src_y); 1097 1098 return 0; 1099 } 1100 1101 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane, 1102 struct drm_plane_state *oldstate) 1103 { 1104 struct drm_plane_state *state = drm_plane->state; 1105 struct sti_plane *plane = to_sti_plane(drm_plane); 1106 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1107 struct drm_crtc *crtc = state->crtc; 1108 struct drm_framebuffer *fb = state->fb; 1109 struct drm_display_mode *mode; 1110 int dst_x, dst_y, dst_w, dst_h; 1111 int src_x, src_y, src_w, src_h; 1112 struct drm_gem_cma_object *cma_obj; 1113 struct sti_hqvdp_cmd *cmd; 1114 int scale_h, scale_v; 1115 int cmd_offset; 1116 1117 if (!crtc || !fb) 1118 return; 1119 1120 if ((oldstate->fb == state->fb) && 1121 (oldstate->crtc_x == state->crtc_x) && 1122 (oldstate->crtc_y == state->crtc_y) && 1123 (oldstate->crtc_w == state->crtc_w) && 1124 (oldstate->crtc_h == state->crtc_h) && 1125 (oldstate->src_x == state->src_x) && 1126 (oldstate->src_y == state->src_y) && 1127 (oldstate->src_w == state->src_w) && 1128 (oldstate->src_h == state->src_h)) { 1129 /* No change since last update, do not post cmd */ 1130 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 1131 plane->status = STI_PLANE_UPDATED; 1132 return; 1133 } 1134 1135 mode = &crtc->mode; 1136 dst_x = state->crtc_x; 1137 dst_y = state->crtc_y; 1138 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1139 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1140 /* src_x are in 16.16 format */ 1141 src_x = state->src_x >> 16; 1142 src_y = state->src_y >> 16; 1143 src_w = state->src_w >> 16; 1144 src_h = state->src_h >> 16; 1145 1146 cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 1147 if (cmd_offset == -1) { 1148 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n"); 1149 return; 1150 } 1151 cmd = hqvdp->hqvdp_cmd + cmd_offset; 1152 1153 /* Static parameters, defaulting to progressive mode */ 1154 cmd->top.config = TOP_CONFIG_PROGRESSIVE; 1155 cmd->top.mem_format = TOP_MEM_FORMAT_DFLT; 1156 cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT; 1157 cmd->csdi.config = CSDI_CONFIG_PROG; 1158 1159 /* VC1RE, FMD bypassed : keep everything set to 0 1160 * IQI/P2I bypassed */ 1161 cmd->iqi.config = IQI_CONFIG_DFLT; 1162 cmd->iqi.con_bri = IQI_CON_BRI_DFLT; 1163 cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT; 1164 cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT; 1165 1166 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 1167 1168 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 1169 (char *)&fb->format->format, 1170 (unsigned long)cma_obj->paddr); 1171 1172 /* Buffer planes address */ 1173 cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0]; 1174 cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1]; 1175 1176 /* Pitches */ 1177 cmd->top.luma_processed_pitch = fb->pitches[0]; 1178 cmd->top.luma_src_pitch = fb->pitches[0]; 1179 cmd->top.chroma_processed_pitch = fb->pitches[1]; 1180 cmd->top.chroma_src_pitch = fb->pitches[1]; 1181 1182 /* Input / output size 1183 * Align to upper even value */ 1184 dst_w = ALIGN(dst_w, 2); 1185 dst_h = ALIGN(dst_h, 2); 1186 1187 cmd->top.input_viewport_size = src_h << 16 | src_w; 1188 cmd->top.input_frame_size = src_h << 16 | src_w; 1189 cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w; 1190 cmd->top.input_viewport_ori = src_y << 16 | src_x; 1191 1192 /* Handle interlaced */ 1193 if (fb->flags & DRM_MODE_FB_INTERLACED) { 1194 /* Top field to display */ 1195 cmd->top.config = TOP_CONFIG_INTER_TOP; 1196 1197 /* Update pitches and vert size */ 1198 cmd->top.input_frame_size = (src_h / 2) << 16 | src_w; 1199 cmd->top.luma_processed_pitch *= 2; 1200 cmd->top.luma_src_pitch *= 2; 1201 cmd->top.chroma_processed_pitch *= 2; 1202 cmd->top.chroma_src_pitch *= 2; 1203 1204 /* Enable directional deinterlacing processing */ 1205 cmd->csdi.config = CSDI_CONFIG_INTER_DIR; 1206 cmd->csdi.config2 = CSDI_CONFIG2_DFLT; 1207 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT; 1208 } 1209 1210 /* Update hvsrc lut coef */ 1211 scale_h = SCALE_FACTOR * dst_w / src_w; 1212 sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc); 1213 1214 scale_v = SCALE_FACTOR * dst_h / src_h; 1215 sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc); 1216 1217 writel(hqvdp->hqvdp_cmd_paddr + cmd_offset, 1218 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 1219 1220 /* Interlaced : get ready to display the bottom field at next Vsync */ 1221 if (fb->flags & DRM_MODE_FB_INTERLACED) 1222 hqvdp->btm_field_pending = true; 1223 1224 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 1225 __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset); 1226 1227 sti_plane_update_fps(plane, true, true); 1228 1229 plane->status = STI_PLANE_UPDATED; 1230 } 1231 1232 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane, 1233 struct drm_plane_state *oldstate) 1234 { 1235 struct sti_plane *plane = to_sti_plane(drm_plane); 1236 1237 if (!oldstate->crtc) { 1238 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 1239 drm_plane->base.id); 1240 return; 1241 } 1242 1243 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 1244 oldstate->crtc->base.id, 1245 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 1246 drm_plane->base.id, sti_plane_to_str(plane)); 1247 1248 plane->status = STI_PLANE_DISABLING; 1249 } 1250 1251 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = { 1252 .atomic_check = sti_hqvdp_atomic_check, 1253 .atomic_update = sti_hqvdp_atomic_update, 1254 .atomic_disable = sti_hqvdp_atomic_disable, 1255 }; 1256 1257 static void sti_hqvdp_destroy(struct drm_plane *drm_plane) 1258 { 1259 DRM_DEBUG_DRIVER("\n"); 1260 1261 drm_plane_helper_disable(drm_plane); 1262 drm_plane_cleanup(drm_plane); 1263 } 1264 1265 static int sti_hqvdp_late_register(struct drm_plane *drm_plane) 1266 { 1267 struct sti_plane *plane = to_sti_plane(drm_plane); 1268 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1269 1270 return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary); 1271 } 1272 1273 static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = { 1274 .update_plane = drm_atomic_helper_update_plane, 1275 .disable_plane = drm_atomic_helper_disable_plane, 1276 .destroy = sti_hqvdp_destroy, 1277 .set_property = drm_atomic_helper_plane_set_property, 1278 .reset = sti_plane_reset, 1279 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1280 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1281 .late_register = sti_hqvdp_late_register, 1282 }; 1283 1284 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev, 1285 struct device *dev, int desc) 1286 { 1287 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1288 int res; 1289 1290 hqvdp->plane.desc = desc; 1291 hqvdp->plane.status = STI_PLANE_DISABLED; 1292 1293 sti_hqvdp_init(hqvdp); 1294 1295 res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1, 1296 &sti_hqvdp_plane_helpers_funcs, 1297 hqvdp_supported_formats, 1298 ARRAY_SIZE(hqvdp_supported_formats), 1299 DRM_PLANE_TYPE_OVERLAY, NULL); 1300 if (res) { 1301 DRM_ERROR("Failed to initialize universal plane\n"); 1302 return NULL; 1303 } 1304 1305 drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs); 1306 1307 sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY); 1308 1309 return &hqvdp->plane.drm_plane; 1310 } 1311 1312 static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data) 1313 { 1314 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1315 struct drm_device *drm_dev = data; 1316 struct drm_plane *plane; 1317 1318 DRM_DEBUG_DRIVER("\n"); 1319 1320 hqvdp->drm_dev = drm_dev; 1321 1322 /* Create HQVDP plane once xp70 is initialized */ 1323 plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0); 1324 if (!plane) 1325 DRM_ERROR("Can't create HQVDP plane\n"); 1326 1327 return 0; 1328 } 1329 1330 static void sti_hqvdp_unbind(struct device *dev, 1331 struct device *master, void *data) 1332 { 1333 /* do nothing */ 1334 } 1335 1336 static const struct component_ops sti_hqvdp_ops = { 1337 .bind = sti_hqvdp_bind, 1338 .unbind = sti_hqvdp_unbind, 1339 }; 1340 1341 static int sti_hqvdp_probe(struct platform_device *pdev) 1342 { 1343 struct device *dev = &pdev->dev; 1344 struct device_node *vtg_np; 1345 struct sti_hqvdp *hqvdp; 1346 struct resource *res; 1347 1348 DRM_DEBUG_DRIVER("\n"); 1349 1350 hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL); 1351 if (!hqvdp) { 1352 DRM_ERROR("Failed to allocate HQVDP context\n"); 1353 return -ENOMEM; 1354 } 1355 1356 hqvdp->dev = dev; 1357 1358 /* Get Memory resources */ 1359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1360 if (res == NULL) { 1361 DRM_ERROR("Get memory resource failed\n"); 1362 return -ENXIO; 1363 } 1364 hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res)); 1365 if (hqvdp->regs == NULL) { 1366 DRM_ERROR("Register mapping failed\n"); 1367 return -ENXIO; 1368 } 1369 1370 /* Get clock resources */ 1371 hqvdp->clk = devm_clk_get(dev, "hqvdp"); 1372 hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main"); 1373 if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) { 1374 DRM_ERROR("Cannot get clocks\n"); 1375 return -ENXIO; 1376 } 1377 1378 /* Get reset resources */ 1379 hqvdp->reset = devm_reset_control_get(dev, "hqvdp"); 1380 if (!IS_ERR(hqvdp->reset)) 1381 reset_control_deassert(hqvdp->reset); 1382 1383 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0); 1384 if (vtg_np) 1385 hqvdp->vtg = of_vtg_find(vtg_np); 1386 of_node_put(vtg_np); 1387 1388 platform_set_drvdata(pdev, hqvdp); 1389 1390 return component_add(&pdev->dev, &sti_hqvdp_ops); 1391 } 1392 1393 static int sti_hqvdp_remove(struct platform_device *pdev) 1394 { 1395 component_del(&pdev->dev, &sti_hqvdp_ops); 1396 return 0; 1397 } 1398 1399 static struct of_device_id hqvdp_of_match[] = { 1400 { .compatible = "st,stih407-hqvdp", }, 1401 { /* end node */ } 1402 }; 1403 MODULE_DEVICE_TABLE(of, hqvdp_of_match); 1404 1405 struct platform_driver sti_hqvdp_driver = { 1406 .driver = { 1407 .name = "sti-hqvdp", 1408 .owner = THIS_MODULE, 1409 .of_match_table = hqvdp_of_match, 1410 }, 1411 .probe = sti_hqvdp_probe, 1412 .remove = sti_hqvdp_remove, 1413 }; 1414 1415 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 1416 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 1417 MODULE_LICENSE("GPL"); 1418