1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #ifndef _STI_HDMI_H_ 8 #define _STI_HDMI_H_ 9 10 #include <linux/platform_device.h> 11 12 #include <drm/drmP.h> 13 14 #define HDMI_STA 0x0010 15 #define HDMI_STA_DLL_LCK BIT(5) 16 17 struct sti_hdmi; 18 19 struct hdmi_phy_ops { 20 bool (*start)(struct sti_hdmi *hdmi); 21 void (*stop)(struct sti_hdmi *hdmi); 22 }; 23 24 /** 25 * STI hdmi structure 26 * 27 * @dev: driver device 28 * @drm_dev: pointer to drm device 29 * @mode: current display mode selected 30 * @regs: hdmi register 31 * @syscfg: syscfg register for pll rejection configuration 32 * @clk_pix: hdmi pixel clock 33 * @clk_tmds: hdmi tmds clock 34 * @clk_phy: hdmi phy clock 35 * @clk_audio: hdmi audio clock 36 * @irq: hdmi interrupt number 37 * @irq_status: interrupt status register 38 * @phy_ops: phy start/stop operations 39 * @enabled: true if hdmi is enabled else false 40 * @hpd_gpio: hdmi hot plug detect gpio number 41 * @hpd: hot plug detect status 42 * @wait_event: wait event 43 * @event_received: wait event status 44 * @reset: reset control of the hdmi phy 45 */ 46 struct sti_hdmi { 47 struct device dev; 48 struct drm_device *drm_dev; 49 struct drm_display_mode mode; 50 void __iomem *regs; 51 void __iomem *syscfg; 52 struct clk *clk_pix; 53 struct clk *clk_tmds; 54 struct clk *clk_phy; 55 struct clk *clk_audio; 56 int irq; 57 u32 irq_status; 58 struct hdmi_phy_ops *phy_ops; 59 bool enabled; 60 int hpd_gpio; 61 bool hpd; 62 wait_queue_head_t wait_event; 63 bool event_received; 64 struct reset_control *reset; 65 }; 66 67 u32 hdmi_read(struct sti_hdmi *hdmi, int offset); 68 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); 69 70 /** 71 * hdmi phy config structure 72 * 73 * A pointer to an array of these structures is passed to a TMDS (HDMI) output 74 * via the control interface to provide board and SoC specific 75 * configurations of the HDMI PHY. Each entry in the array specifies a hardware 76 * specific configuration for a given TMDS clock frequency range. 77 * 78 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to 79 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to 80 * @config: SoC specific register configuration 81 */ 82 struct hdmi_phy_config { 83 u32 min_tmds_freq; 84 u32 max_tmds_freq; 85 u32 config[4]; 86 }; 87 88 #endif 89