1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/seq_file.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_bridge.h> 16 #include <drm/drm_debugfs.h> 17 #include <drm/drm_device.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_print.h> 20 #include <drm/drm_probe_helper.h> 21 22 /* HDformatter registers */ 23 #define HDA_ANA_CFG 0x0000 24 #define HDA_ANA_SCALE_CTRL_Y 0x0004 25 #define HDA_ANA_SCALE_CTRL_CB 0x0008 26 #define HDA_ANA_SCALE_CTRL_CR 0x000C 27 #define HDA_ANA_ANC_CTRL 0x0010 28 #define HDA_ANA_SRC_Y_CFG 0x0014 29 #define HDA_COEFF_Y_PH1_TAP123 0x0018 30 #define HDA_COEFF_Y_PH1_TAP456 0x001C 31 #define HDA_COEFF_Y_PH2_TAP123 0x0020 32 #define HDA_COEFF_Y_PH2_TAP456 0x0024 33 #define HDA_COEFF_Y_PH3_TAP123 0x0028 34 #define HDA_COEFF_Y_PH3_TAP456 0x002C 35 #define HDA_COEFF_Y_PH4_TAP123 0x0030 36 #define HDA_COEFF_Y_PH4_TAP456 0x0034 37 #define HDA_ANA_SRC_C_CFG 0x0040 38 #define HDA_COEFF_C_PH1_TAP123 0x0044 39 #define HDA_COEFF_C_PH1_TAP456 0x0048 40 #define HDA_COEFF_C_PH2_TAP123 0x004C 41 #define HDA_COEFF_C_PH2_TAP456 0x0050 42 #define HDA_COEFF_C_PH3_TAP123 0x0054 43 #define HDA_COEFF_C_PH3_TAP456 0x0058 44 #define HDA_COEFF_C_PH4_TAP123 0x005C 45 #define HDA_COEFF_C_PH4_TAP456 0x0060 46 #define HDA_SYNC_AWGI 0x0300 47 48 /* HDA_ANA_CFG */ 49 #define CFG_AWG_ASYNC_EN BIT(0) 50 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1) 51 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2) 52 #define CFG_AWG_SYNC_DEL BIT(3) 53 #define CFG_AWG_FLTR_MODE_SHIFT 4 54 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT) 55 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT) 56 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT) 57 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT) 58 #define CFG_SYNC_ON_PBPR_MASK BIT(8) 59 #define CFG_PREFILTER_EN_MASK BIT(9) 60 #define CFG_PBPR_SYNC_OFF_SHIFT 16 61 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT) 62 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */ 63 64 /* Default scaling values */ 65 #define SCALE_CTRL_Y_DFLT 0x00C50256 66 #define SCALE_CTRL_CB_DFLT 0x00DB0249 67 #define SCALE_CTRL_CR_DFLT 0x00DB0249 68 69 /* Video DACs control */ 70 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) 71 72 /* Upsampler values for the alternative 2X Filter */ 73 #define SAMPLER_COEF_NB 8 74 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000 75 static u32 coef_y_alt_2x[] = { 76 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000, 77 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000 78 }; 79 80 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004 81 static u32 coef_c_alt_2x[] = { 82 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000, 83 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000 84 }; 85 86 /* Upsampler values for the 4X Filter */ 87 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005 88 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004 89 static u32 coef_yc_4x[] = { 90 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24, 91 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D 92 }; 93 94 /* AWG instructions for some video modes */ 95 #define AWG_MAX_INST 64 96 97 /* 720p@50 */ 98 static u32 AWGi_720p_50[] = { 99 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 100 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 101 0x00000D8E, 0x00000104, 0x00001804, 0x00000971, 102 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5, 103 0x00000104, 0x00001AE8 104 }; 105 106 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50) 107 108 /* 720p@60 */ 109 static u32 AWGi_720p_60[] = { 110 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 111 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 112 0x00000C44, 0x00000104, 0x00001804, 0x00000971, 113 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10, 114 0x00000104, 0x00001AE8 115 }; 116 117 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60) 118 119 /* 1080p@30 */ 120 static u32 AWGi_1080p_30[] = { 121 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 122 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 123 0x00000C2A, 0x00000104, 0x00001804, 0x00000971, 124 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF, 125 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B, 126 0x00001C52 127 }; 128 129 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30) 130 131 /* 1080p@25 */ 132 static u32 AWGi_1080p_25[] = { 133 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 134 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 135 0x00000DE2, 0x00000104, 0x00001804, 0x00000971, 136 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51, 137 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B, 138 0x00001C52 139 }; 140 141 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25) 142 143 /* 1080p@24 */ 144 static u32 AWGi_1080p_24[] = { 145 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 146 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 147 0x00000E50, 0x00000104, 0x00001804, 0x00000971, 148 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76, 149 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B, 150 0x00001C52 151 }; 152 153 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24) 154 155 /* 720x480p@60 */ 156 static u32 AWGi_720x480p_60[] = { 157 0x00000904, 0x00000F18, 0x0000013B, 0x00001805, 158 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06 159 }; 160 161 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60) 162 163 /* Video mode category */ 164 enum sti_hda_vid_cat { 165 VID_SD, 166 VID_ED, 167 VID_HD_74M, 168 VID_HD_148M 169 }; 170 171 struct sti_hda_video_config { 172 struct drm_display_mode mode; 173 u32 *awg_instr; 174 int nb_instr; 175 enum sti_hda_vid_cat vid_cat; 176 }; 177 178 /* HD analog supported modes 179 * Interlaced modes may be added when supported by the whole display chain 180 */ 181 static const struct sti_hda_video_config hda_supported_modes[] = { 182 /* 1080p30 74.250Mhz */ 183 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 184 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 186 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 187 /* 1080p30 74.176Mhz */ 188 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008, 189 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 191 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 192 /* 1080p24 74.250Mhz */ 193 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 194 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 196 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 197 /* 1080p24 74.176Mhz */ 198 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558, 199 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 201 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 202 /* 1080p25 74.250Mhz */ 203 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 204 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 206 AWGi_1080p_25, NN_1080p_25, VID_HD_74M}, 207 /* 720p60 74.250Mhz */ 208 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 209 1430, 1650, 0, 720, 725, 730, 750, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 211 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 212 /* 720p60 74.176Mhz */ 213 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390, 214 1430, 1650, 0, 720, 725, 730, 750, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 216 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 217 /* 720p50 74.250Mhz */ 218 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 219 1760, 1980, 0, 720, 725, 730, 750, 0, 220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 221 AWGi_720p_50, NN_720p_50, VID_HD_74M}, 222 /* 720x480p60 27.027Mhz */ 223 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736, 224 798, 858, 0, 480, 489, 495, 525, 0, 225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 226 AWGi_720x480p_60, NN_720x480p_60, VID_ED}, 227 /* 720x480p60 27.000Mhz */ 228 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 229 798, 858, 0, 480, 489, 495, 525, 0, 230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 231 AWGi_720x480p_60, NN_720x480p_60, VID_ED} 232 }; 233 234 /* 235 * STI hd analog structure 236 * 237 * @dev: driver device 238 * @drm_dev: pointer to drm device 239 * @mode: current display mode selected 240 * @regs: HD analog register 241 * @video_dacs_ctrl: video DACS control register 242 * @enabled: true if HD analog is enabled else false 243 */ 244 struct sti_hda { 245 struct device dev; 246 struct drm_device *drm_dev; 247 struct drm_display_mode mode; 248 struct drm_bridge bridge; 249 void __iomem *regs; 250 void __iomem *video_dacs_ctrl; 251 struct clk *clk_pix; 252 struct clk *clk_hddac; 253 bool enabled; 254 }; 255 256 struct sti_hda_connector { 257 struct drm_connector drm_connector; 258 struct drm_encoder *encoder; 259 struct sti_hda *hda; 260 }; 261 262 #define to_sti_hda_connector(x) \ 263 container_of(x, struct sti_hda_connector, drm_connector) 264 265 static struct sti_hda *drm_bridge_to_sti_hda(struct drm_bridge *bridge) 266 { 267 return container_of(bridge, struct sti_hda, bridge); 268 } 269 270 static u32 hda_read(struct sti_hda *hda, int offset) 271 { 272 return readl(hda->regs + offset); 273 } 274 275 static void hda_write(struct sti_hda *hda, u32 val, int offset) 276 { 277 writel(val, hda->regs + offset); 278 } 279 280 /** 281 * hda_get_mode_idx - Search for a video mode in the supported modes table 282 * 283 * @mode: mode being searched 284 * @idx: index of the found mode 285 * 286 * Return true if mode is found 287 */ 288 static bool hda_get_mode_idx(const struct drm_display_mode *mode, int *idx) 289 { 290 unsigned int i; 291 292 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) 293 if (drm_mode_equal(&hda_supported_modes[i].mode, mode)) { 294 *idx = i; 295 return true; 296 } 297 return false; 298 } 299 300 /** 301 * hda_enable_hd_dacs - Enable the HD DACS 302 * 303 * @hda: pointer to HD analog structure 304 * @enable: true if HD DACS need to be enabled, else false 305 */ 306 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable) 307 { 308 if (hda->video_dacs_ctrl) { 309 u32 val; 310 311 val = readl(hda->video_dacs_ctrl); 312 if (enable) 313 val &= ~DAC_CFG_HD_HZUVW_OFF_MASK; 314 else 315 val |= DAC_CFG_HD_HZUVW_OFF_MASK; 316 317 writel(val, hda->video_dacs_ctrl); 318 } 319 } 320 321 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 322 readl(hda->regs + reg)) 323 324 static void hda_dbg_cfg(struct seq_file *s, int val) 325 { 326 seq_puts(s, "\tAWG "); 327 seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); 328 } 329 330 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) 331 { 332 unsigned int i; 333 334 seq_puts(s, "\n\n HDA AWG microcode:"); 335 for (i = 0; i < AWG_MAX_INST; i++) { 336 if (i % 8 == 0) 337 seq_printf(s, "\n %04X:", i); 338 seq_printf(s, " %04X", readl(reg + i * 4)); 339 } 340 } 341 342 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) 343 { 344 u32 val = readl(reg); 345 346 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); 347 seq_puts(s, "\tHD DACs "); 348 seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled"); 349 } 350 351 static int hda_dbg_show(struct seq_file *s, void *data) 352 { 353 struct drm_info_node *node = s->private; 354 struct sti_hda *hda = (struct sti_hda *)node->info_ent->data; 355 356 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); 357 DBGFS_DUMP(HDA_ANA_CFG); 358 hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG)); 359 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y); 360 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB); 361 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR); 362 DBGFS_DUMP(HDA_ANA_ANC_CTRL); 363 DBGFS_DUMP(HDA_ANA_SRC_Y_CFG); 364 DBGFS_DUMP(HDA_ANA_SRC_C_CFG); 365 hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI); 366 if (hda->video_dacs_ctrl) 367 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl); 368 seq_putc(s, '\n'); 369 return 0; 370 } 371 372 static struct drm_info_list hda_debugfs_files[] = { 373 { "hda", hda_dbg_show, 0, NULL }, 374 }; 375 376 static void hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor) 377 { 378 unsigned int i; 379 380 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) 381 hda_debugfs_files[i].data = hda; 382 383 drm_debugfs_create_files(hda_debugfs_files, 384 ARRAY_SIZE(hda_debugfs_files), 385 minor->debugfs_root, minor); 386 } 387 388 /** 389 * sti_hda_configure_awg - Configure AWG, writing instructions 390 * 391 * @hda: pointer to HD analog structure 392 * @awg_instr: pointer to AWG instructions table 393 * @nb: nb of AWG instructions 394 */ 395 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb) 396 { 397 unsigned int i; 398 399 DRM_DEBUG_DRIVER("\n"); 400 401 for (i = 0; i < nb; i++) 402 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4); 403 for (i = nb; i < AWG_MAX_INST; i++) 404 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); 405 } 406 407 static void sti_hda_disable(struct drm_bridge *bridge) 408 { 409 struct sti_hda *hda = drm_bridge_to_sti_hda(bridge); 410 u32 val; 411 412 if (!hda->enabled) 413 return; 414 415 DRM_DEBUG_DRIVER("\n"); 416 417 /* Disable HD DAC and AWG */ 418 val = hda_read(hda, HDA_ANA_CFG); 419 val &= ~CFG_AWG_ASYNC_EN; 420 hda_write(hda, val, HDA_ANA_CFG); 421 hda_write(hda, 0, HDA_ANA_ANC_CTRL); 422 423 hda_enable_hd_dacs(hda, false); 424 425 /* Disable/unprepare hda clock */ 426 clk_disable_unprepare(hda->clk_hddac); 427 clk_disable_unprepare(hda->clk_pix); 428 429 hda->enabled = false; 430 } 431 432 static void sti_hda_pre_enable(struct drm_bridge *bridge) 433 { 434 struct sti_hda *hda = drm_bridge_to_sti_hda(bridge); 435 u32 val, i, mode_idx; 436 u32 src_filter_y, src_filter_c; 437 u32 *coef_y, *coef_c; 438 u32 filter_mode; 439 440 DRM_DEBUG_DRIVER("\n"); 441 442 if (hda->enabled) 443 return; 444 445 /* Prepare/enable clocks */ 446 if (clk_prepare_enable(hda->clk_pix)) 447 DRM_ERROR("Failed to prepare/enable hda_pix clk\n"); 448 if (clk_prepare_enable(hda->clk_hddac)) 449 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n"); 450 451 if (!hda_get_mode_idx(&hda->mode, &mode_idx)) { 452 DRM_ERROR("Undefined mode\n"); 453 return; 454 } 455 456 switch (hda_supported_modes[mode_idx].vid_cat) { 457 case VID_HD_148M: 458 DRM_ERROR("Beyond HD analog capabilities\n"); 459 return; 460 case VID_HD_74M: 461 /* HD use alternate 2x filter */ 462 filter_mode = CFG_AWG_FLTR_MODE_HD; 463 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X; 464 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X; 465 coef_y = coef_y_alt_2x; 466 coef_c = coef_c_alt_2x; 467 break; 468 case VID_ED: 469 /* ED uses 4x filter */ 470 filter_mode = CFG_AWG_FLTR_MODE_ED; 471 src_filter_y = HDA_ANA_SRC_Y_CFG_4X; 472 src_filter_c = HDA_ANA_SRC_C_CFG_4X; 473 coef_y = coef_yc_4x; 474 coef_c = coef_yc_4x; 475 break; 476 case VID_SD: 477 DRM_ERROR("Not supported\n"); 478 return; 479 default: 480 DRM_ERROR("Undefined resolution\n"); 481 return; 482 } 483 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx); 484 485 /* Enable HD Video DACs */ 486 hda_enable_hd_dacs(hda, true); 487 488 /* Configure scaler */ 489 hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y); 490 hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB); 491 hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR); 492 493 /* Configure sampler */ 494 hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG); 495 hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG); 496 for (i = 0; i < SAMPLER_COEF_NB; i++) { 497 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4); 498 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4); 499 } 500 501 /* Configure main HDFormatter */ 502 val = 0; 503 val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? 504 0 : CFG_AWG_ASYNC_VSYNC_MTD; 505 val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); 506 val |= filter_mode; 507 hda_write(hda, val, HDA_ANA_CFG); 508 509 /* Configure AWG */ 510 sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr, 511 hda_supported_modes[mode_idx].nb_instr); 512 513 /* Enable AWG */ 514 val = hda_read(hda, HDA_ANA_CFG); 515 val |= CFG_AWG_ASYNC_EN; 516 hda_write(hda, val, HDA_ANA_CFG); 517 518 hda->enabled = true; 519 } 520 521 static void sti_hda_set_mode(struct drm_bridge *bridge, 522 const struct drm_display_mode *mode, 523 const struct drm_display_mode *adjusted_mode) 524 { 525 struct sti_hda *hda = drm_bridge_to_sti_hda(bridge); 526 u32 mode_idx; 527 int hddac_rate; 528 int ret; 529 530 DRM_DEBUG_DRIVER("\n"); 531 532 drm_mode_copy(&hda->mode, mode); 533 534 if (!hda_get_mode_idx(&hda->mode, &mode_idx)) { 535 DRM_ERROR("Undefined mode\n"); 536 return; 537 } 538 539 switch (hda_supported_modes[mode_idx].vid_cat) { 540 case VID_HD_74M: 541 /* HD use alternate 2x filter */ 542 hddac_rate = mode->clock * 1000 * 2; 543 break; 544 case VID_ED: 545 /* ED uses 4x filter */ 546 hddac_rate = mode->clock * 1000 * 4; 547 break; 548 default: 549 DRM_ERROR("Undefined mode\n"); 550 return; 551 } 552 553 /* HD DAC = 148.5Mhz or 108 Mhz */ 554 ret = clk_set_rate(hda->clk_hddac, hddac_rate); 555 if (ret < 0) 556 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n", 557 hddac_rate); 558 559 /* HDformatter clock = compositor clock */ 560 ret = clk_set_rate(hda->clk_pix, mode->clock * 1000); 561 if (ret < 0) 562 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n", 563 mode->clock * 1000); 564 } 565 566 static void sti_hda_bridge_nope(struct drm_bridge *bridge) 567 { 568 /* do nothing */ 569 } 570 571 static const struct drm_bridge_funcs sti_hda_bridge_funcs = { 572 .pre_enable = sti_hda_pre_enable, 573 .enable = sti_hda_bridge_nope, 574 .disable = sti_hda_disable, 575 .post_disable = sti_hda_bridge_nope, 576 .mode_set = sti_hda_set_mode, 577 }; 578 579 static int sti_hda_connector_get_modes(struct drm_connector *connector) 580 { 581 unsigned int i; 582 int count = 0; 583 struct sti_hda_connector *hda_connector 584 = to_sti_hda_connector(connector); 585 struct sti_hda *hda = hda_connector->hda; 586 587 DRM_DEBUG_DRIVER("\n"); 588 589 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { 590 struct drm_display_mode *mode = 591 drm_mode_duplicate(hda->drm_dev, 592 &hda_supported_modes[i].mode); 593 if (!mode) 594 continue; 595 596 /* the first mode is the preferred mode */ 597 if (i == 0) 598 mode->type |= DRM_MODE_TYPE_PREFERRED; 599 600 drm_mode_probed_add(connector, mode); 601 count++; 602 } 603 604 return count; 605 } 606 607 #define CLK_TOLERANCE_HZ 50 608 609 static enum drm_mode_status 610 sti_hda_connector_mode_valid(struct drm_connector *connector, 611 const struct drm_display_mode *mode) 612 { 613 int target = mode->clock * 1000; 614 int target_min = target - CLK_TOLERANCE_HZ; 615 int target_max = target + CLK_TOLERANCE_HZ; 616 int result; 617 int idx; 618 struct sti_hda_connector *hda_connector 619 = to_sti_hda_connector(connector); 620 struct sti_hda *hda = hda_connector->hda; 621 622 if (!hda_get_mode_idx(mode, &idx)) { 623 return MODE_BAD; 624 } else { 625 result = clk_round_rate(hda->clk_pix, target); 626 627 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 628 target, result); 629 630 if ((result < target_min) || (result > target_max)) { 631 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n", 632 target); 633 return MODE_BAD; 634 } 635 } 636 637 return MODE_OK; 638 } 639 640 static const 641 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = { 642 .get_modes = sti_hda_connector_get_modes, 643 .mode_valid = sti_hda_connector_mode_valid, 644 }; 645 646 static int sti_hda_late_register(struct drm_connector *connector) 647 { 648 struct sti_hda_connector *hda_connector 649 = to_sti_hda_connector(connector); 650 struct sti_hda *hda = hda_connector->hda; 651 652 hda_debugfs_init(hda, hda->drm_dev->primary); 653 654 return 0; 655 } 656 657 static const struct drm_connector_funcs sti_hda_connector_funcs = { 658 .fill_modes = drm_helper_probe_single_connector_modes, 659 .destroy = drm_connector_cleanup, 660 .reset = drm_atomic_helper_connector_reset, 661 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 662 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 663 .late_register = sti_hda_late_register, 664 }; 665 666 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev) 667 { 668 struct drm_encoder *encoder; 669 670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 671 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC) 672 return encoder; 673 } 674 675 return NULL; 676 } 677 678 static int sti_hda_bind(struct device *dev, struct device *master, void *data) 679 { 680 struct sti_hda *hda = dev_get_drvdata(dev); 681 struct drm_device *drm_dev = data; 682 struct drm_encoder *encoder; 683 struct sti_hda_connector *connector; 684 struct drm_connector *drm_connector; 685 int err; 686 687 /* Set the drm device handle */ 688 hda->drm_dev = drm_dev; 689 690 encoder = sti_hda_find_encoder(drm_dev); 691 if (!encoder) 692 return -ENOMEM; 693 694 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 695 if (!connector) 696 return -ENOMEM; 697 698 connector->hda = hda; 699 700 drm_bridge_attach(encoder, &hda->bridge, NULL, 0); 701 702 connector->encoder = encoder; 703 704 drm_connector = (struct drm_connector *)connector; 705 706 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 707 708 drm_connector_init(drm_dev, drm_connector, 709 &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component); 710 drm_connector_helper_add(drm_connector, 711 &sti_hda_connector_helper_funcs); 712 713 err = drm_connector_attach_encoder(drm_connector, encoder); 714 if (err) { 715 DRM_ERROR("Failed to attach a connector to a encoder\n"); 716 goto err_sysfs; 717 } 718 719 /* force to disable hd dacs at startup */ 720 hda_enable_hd_dacs(hda, false); 721 722 return 0; 723 724 err_sysfs: 725 return -EINVAL; 726 } 727 728 static void sti_hda_unbind(struct device *dev, 729 struct device *master, void *data) 730 { 731 } 732 733 static const struct component_ops sti_hda_ops = { 734 .bind = sti_hda_bind, 735 .unbind = sti_hda_unbind, 736 }; 737 738 static int sti_hda_probe(struct platform_device *pdev) 739 { 740 struct device *dev = &pdev->dev; 741 struct sti_hda *hda; 742 struct resource *res; 743 int ret; 744 745 DRM_INFO("%s\n", __func__); 746 747 hda = devm_drm_bridge_alloc(dev, struct sti_hda, bridge, &sti_hda_bridge_funcs); 748 if (IS_ERR(hda)) 749 return PTR_ERR(hda); 750 751 hda->dev = pdev->dev; 752 hda->regs = devm_platform_ioremap_resource_byname(pdev, "hda-reg"); 753 if (IS_ERR(hda->regs)) 754 return PTR_ERR(hda->regs); 755 756 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 757 "video-dacs-ctrl"); 758 if (res) { 759 hda->video_dacs_ctrl = devm_ioremap(dev, res->start, 760 resource_size(res)); 761 if (!hda->video_dacs_ctrl) 762 return -ENOMEM; 763 } else { 764 /* If no existing video-dacs-ctrl resource continue the probe */ 765 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); 766 hda->video_dacs_ctrl = NULL; 767 } 768 769 /* Get clock resources */ 770 hda->clk_pix = devm_clk_get(dev, "pix"); 771 if (IS_ERR(hda->clk_pix)) { 772 DRM_ERROR("Cannot get hda_pix clock\n"); 773 return PTR_ERR(hda->clk_pix); 774 } 775 776 hda->clk_hddac = devm_clk_get(dev, "hddac"); 777 if (IS_ERR(hda->clk_hddac)) { 778 DRM_ERROR("Cannot get hda_hddac clock\n"); 779 return PTR_ERR(hda->clk_hddac); 780 } 781 782 ret = devm_drm_bridge_add(dev, &hda->bridge); 783 if (ret) 784 return ret; 785 786 platform_set_drvdata(pdev, hda); 787 788 return component_add(&pdev->dev, &sti_hda_ops); 789 } 790 791 static void sti_hda_remove(struct platform_device *pdev) 792 { 793 component_del(&pdev->dev, &sti_hda_ops); 794 } 795 796 static const struct of_device_id hda_of_match[] = { 797 { .compatible = "st,stih416-hda", }, 798 { .compatible = "st,stih407-hda", }, 799 { /* end node */ } 800 }; 801 MODULE_DEVICE_TABLE(of, hda_of_match); 802 803 struct platform_driver sti_hda_driver = { 804 .driver = { 805 .name = "sti-hda", 806 .of_match_table = hda_of_match, 807 }, 808 .probe = sti_hda_probe, 809 .remove = sti_hda_remove, 810 }; 811 812 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 813 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 814 MODULE_LICENSE("GPL"); 815