1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_crtc_helper.h> 16 17 /* HDformatter registers */ 18 #define HDA_ANA_CFG 0x0000 19 #define HDA_ANA_SCALE_CTRL_Y 0x0004 20 #define HDA_ANA_SCALE_CTRL_CB 0x0008 21 #define HDA_ANA_SCALE_CTRL_CR 0x000C 22 #define HDA_ANA_ANC_CTRL 0x0010 23 #define HDA_ANA_SRC_Y_CFG 0x0014 24 #define HDA_COEFF_Y_PH1_TAP123 0x0018 25 #define HDA_COEFF_Y_PH1_TAP456 0x001C 26 #define HDA_COEFF_Y_PH2_TAP123 0x0020 27 #define HDA_COEFF_Y_PH2_TAP456 0x0024 28 #define HDA_COEFF_Y_PH3_TAP123 0x0028 29 #define HDA_COEFF_Y_PH3_TAP456 0x002C 30 #define HDA_COEFF_Y_PH4_TAP123 0x0030 31 #define HDA_COEFF_Y_PH4_TAP456 0x0034 32 #define HDA_ANA_SRC_C_CFG 0x0040 33 #define HDA_COEFF_C_PH1_TAP123 0x0044 34 #define HDA_COEFF_C_PH1_TAP456 0x0048 35 #define HDA_COEFF_C_PH2_TAP123 0x004C 36 #define HDA_COEFF_C_PH2_TAP456 0x0050 37 #define HDA_COEFF_C_PH3_TAP123 0x0054 38 #define HDA_COEFF_C_PH3_TAP456 0x0058 39 #define HDA_COEFF_C_PH4_TAP123 0x005C 40 #define HDA_COEFF_C_PH4_TAP456 0x0060 41 #define HDA_SYNC_AWGI 0x0300 42 43 /* HDA_ANA_CFG */ 44 #define CFG_AWG_ASYNC_EN BIT(0) 45 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1) 46 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2) 47 #define CFG_AWG_SYNC_DEL BIT(3) 48 #define CFG_AWG_FLTR_MODE_SHIFT 4 49 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT) 50 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT) 51 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT) 52 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT) 53 #define CFG_SYNC_ON_PBPR_MASK BIT(8) 54 #define CFG_PREFILTER_EN_MASK BIT(9) 55 #define CFG_PBPR_SYNC_OFF_SHIFT 16 56 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT) 57 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */ 58 59 /* Default scaling values */ 60 #define SCALE_CTRL_Y_DFLT 0x00C50256 61 #define SCALE_CTRL_CB_DFLT 0x00DB0249 62 #define SCALE_CTRL_CR_DFLT 0x00DB0249 63 64 /* Video DACs control */ 65 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) 66 67 /* Upsampler values for the alternative 2X Filter */ 68 #define SAMPLER_COEF_NB 8 69 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000 70 static u32 coef_y_alt_2x[] = { 71 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000, 72 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000 73 }; 74 75 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004 76 static u32 coef_c_alt_2x[] = { 77 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000, 78 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000 79 }; 80 81 /* Upsampler values for the 4X Filter */ 82 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005 83 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004 84 static u32 coef_yc_4x[] = { 85 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24, 86 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D 87 }; 88 89 /* AWG instructions for some video modes */ 90 #define AWG_MAX_INST 64 91 92 /* 720p@50 */ 93 static u32 AWGi_720p_50[] = { 94 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 95 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 96 0x00000D8E, 0x00000104, 0x00001804, 0x00000971, 97 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5, 98 0x00000104, 0x00001AE8 99 }; 100 101 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50) 102 103 /* 720p@60 */ 104 static u32 AWGi_720p_60[] = { 105 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 106 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 107 0x00000C44, 0x00000104, 0x00001804, 0x00000971, 108 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10, 109 0x00000104, 0x00001AE8 110 }; 111 112 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60) 113 114 /* 1080p@30 */ 115 static u32 AWGi_1080p_30[] = { 116 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 117 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 118 0x00000C2A, 0x00000104, 0x00001804, 0x00000971, 119 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF, 120 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B, 121 0x00001C52 122 }; 123 124 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30) 125 126 /* 1080p@25 */ 127 static u32 AWGi_1080p_25[] = { 128 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 129 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 130 0x00000DE2, 0x00000104, 0x00001804, 0x00000971, 131 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51, 132 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B, 133 0x00001C52 134 }; 135 136 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25) 137 138 /* 1080p@24 */ 139 static u32 AWGi_1080p_24[] = { 140 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 141 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 142 0x00000E50, 0x00000104, 0x00001804, 0x00000971, 143 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76, 144 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B, 145 0x00001C52 146 }; 147 148 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24) 149 150 /* 720x480p@60 */ 151 static u32 AWGi_720x480p_60[] = { 152 0x00000904, 0x00000F18, 0x0000013B, 0x00001805, 153 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06 154 }; 155 156 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60) 157 158 /* Video mode category */ 159 enum sti_hda_vid_cat { 160 VID_SD, 161 VID_ED, 162 VID_HD_74M, 163 VID_HD_148M 164 }; 165 166 struct sti_hda_video_config { 167 struct drm_display_mode mode; 168 u32 *awg_instr; 169 int nb_instr; 170 enum sti_hda_vid_cat vid_cat; 171 }; 172 173 /* HD analog supported modes 174 * Interlaced modes may be added when supported by the whole display chain 175 */ 176 static const struct sti_hda_video_config hda_supported_modes[] = { 177 /* 1080p30 74.250Mhz */ 178 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 179 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 181 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 182 /* 1080p30 74.176Mhz */ 183 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008, 184 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 186 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 187 /* 1080p24 74.250Mhz */ 188 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 189 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 191 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 192 /* 1080p24 74.176Mhz */ 193 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558, 194 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 196 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 197 /* 1080p25 74.250Mhz */ 198 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 199 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 201 AWGi_1080p_25, NN_1080p_25, VID_HD_74M}, 202 /* 720p60 74.250Mhz */ 203 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 204 1430, 1650, 0, 720, 725, 730, 750, 0, 205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 206 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 207 /* 720p60 74.176Mhz */ 208 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390, 209 1430, 1650, 0, 720, 725, 730, 750, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 211 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 212 /* 720p50 74.250Mhz */ 213 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 214 1760, 1980, 0, 720, 725, 730, 750, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 216 AWGi_720p_50, NN_720p_50, VID_HD_74M}, 217 /* 720x480p60 27.027Mhz */ 218 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736, 219 798, 858, 0, 480, 489, 495, 525, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 221 AWGi_720x480p_60, NN_720x480p_60, VID_ED}, 222 /* 720x480p60 27.000Mhz */ 223 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 224 798, 858, 0, 480, 489, 495, 525, 0, 225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 226 AWGi_720x480p_60, NN_720x480p_60, VID_ED} 227 }; 228 229 /** 230 * STI hd analog structure 231 * 232 * @dev: driver device 233 * @drm_dev: pointer to drm device 234 * @mode: current display mode selected 235 * @regs: HD analog register 236 * @video_dacs_ctrl: video DACS control register 237 * @enabled: true if HD analog is enabled else false 238 */ 239 struct sti_hda { 240 struct device dev; 241 struct drm_device *drm_dev; 242 struct drm_display_mode mode; 243 void __iomem *regs; 244 void __iomem *video_dacs_ctrl; 245 struct clk *clk_pix; 246 struct clk *clk_hddac; 247 bool enabled; 248 }; 249 250 struct sti_hda_connector { 251 struct drm_connector drm_connector; 252 struct drm_encoder *encoder; 253 struct sti_hda *hda; 254 }; 255 256 #define to_sti_hda_connector(x) \ 257 container_of(x, struct sti_hda_connector, drm_connector) 258 259 static u32 hda_read(struct sti_hda *hda, int offset) 260 { 261 return readl(hda->regs + offset); 262 } 263 264 static void hda_write(struct sti_hda *hda, u32 val, int offset) 265 { 266 writel(val, hda->regs + offset); 267 } 268 269 /** 270 * Search for a video mode in the supported modes table 271 * 272 * @mode: mode being searched 273 * @idx: index of the found mode 274 * 275 * Return true if mode is found 276 */ 277 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx) 278 { 279 unsigned int i; 280 281 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) 282 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) { 283 *idx = i; 284 return true; 285 } 286 return false; 287 } 288 289 /** 290 * Enable the HD DACS 291 * 292 * @hda: pointer to HD analog structure 293 * @enable: true if HD DACS need to be enabled, else false 294 */ 295 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable) 296 { 297 if (hda->video_dacs_ctrl) { 298 u32 val; 299 300 val = readl(hda->video_dacs_ctrl); 301 if (enable) 302 val &= ~DAC_CFG_HD_HZUVW_OFF_MASK; 303 else 304 val |= DAC_CFG_HD_HZUVW_OFF_MASK; 305 306 writel(val, hda->video_dacs_ctrl); 307 } 308 } 309 310 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 311 readl(hda->regs + reg)) 312 313 static void hda_dbg_cfg(struct seq_file *s, int val) 314 { 315 seq_puts(s, "\tAWG "); 316 seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); 317 } 318 319 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) 320 { 321 unsigned int i; 322 323 seq_puts(s, "\n\n HDA AWG microcode:"); 324 for (i = 0; i < AWG_MAX_INST; i++) { 325 if (i % 8 == 0) 326 seq_printf(s, "\n %04X:", i); 327 seq_printf(s, " %04X", readl(reg + i * 4)); 328 } 329 } 330 331 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) 332 { 333 u32 val = readl(reg); 334 335 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); 336 seq_puts(s, "\tHD DACs "); 337 seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled"); 338 } 339 340 static int hda_dbg_show(struct seq_file *s, void *data) 341 { 342 struct drm_info_node *node = s->private; 343 struct sti_hda *hda = (struct sti_hda *)node->info_ent->data; 344 345 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); 346 DBGFS_DUMP(HDA_ANA_CFG); 347 hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG)); 348 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y); 349 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB); 350 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR); 351 DBGFS_DUMP(HDA_ANA_ANC_CTRL); 352 DBGFS_DUMP(HDA_ANA_SRC_Y_CFG); 353 DBGFS_DUMP(HDA_ANA_SRC_C_CFG); 354 hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI); 355 if (hda->video_dacs_ctrl) 356 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl); 357 seq_putc(s, '\n'); 358 return 0; 359 } 360 361 static struct drm_info_list hda_debugfs_files[] = { 362 { "hda", hda_dbg_show, 0, NULL }, 363 }; 364 365 static int hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor) 366 { 367 unsigned int i; 368 369 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) 370 hda_debugfs_files[i].data = hda; 371 372 return drm_debugfs_create_files(hda_debugfs_files, 373 ARRAY_SIZE(hda_debugfs_files), 374 minor->debugfs_root, minor); 375 } 376 377 /** 378 * Configure AWG, writing instructions 379 * 380 * @hda: pointer to HD analog structure 381 * @awg_instr: pointer to AWG instructions table 382 * @nb: nb of AWG instructions 383 */ 384 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb) 385 { 386 unsigned int i; 387 388 DRM_DEBUG_DRIVER("\n"); 389 390 for (i = 0; i < nb; i++) 391 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4); 392 for (i = nb; i < AWG_MAX_INST; i++) 393 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); 394 } 395 396 static void sti_hda_disable(struct drm_bridge *bridge) 397 { 398 struct sti_hda *hda = bridge->driver_private; 399 u32 val; 400 401 if (!hda->enabled) 402 return; 403 404 DRM_DEBUG_DRIVER("\n"); 405 406 /* Disable HD DAC and AWG */ 407 val = hda_read(hda, HDA_ANA_CFG); 408 val &= ~CFG_AWG_ASYNC_EN; 409 hda_write(hda, val, HDA_ANA_CFG); 410 hda_write(hda, 0, HDA_ANA_ANC_CTRL); 411 412 hda_enable_hd_dacs(hda, false); 413 414 /* Disable/unprepare hda clock */ 415 clk_disable_unprepare(hda->clk_hddac); 416 clk_disable_unprepare(hda->clk_pix); 417 418 hda->enabled = false; 419 } 420 421 static void sti_hda_pre_enable(struct drm_bridge *bridge) 422 { 423 struct sti_hda *hda = bridge->driver_private; 424 u32 val, i, mode_idx; 425 u32 src_filter_y, src_filter_c; 426 u32 *coef_y, *coef_c; 427 u32 filter_mode; 428 429 DRM_DEBUG_DRIVER("\n"); 430 431 if (hda->enabled) 432 return; 433 434 /* Prepare/enable clocks */ 435 if (clk_prepare_enable(hda->clk_pix)) 436 DRM_ERROR("Failed to prepare/enable hda_pix clk\n"); 437 if (clk_prepare_enable(hda->clk_hddac)) 438 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n"); 439 440 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 441 DRM_ERROR("Undefined mode\n"); 442 return; 443 } 444 445 switch (hda_supported_modes[mode_idx].vid_cat) { 446 case VID_HD_148M: 447 DRM_ERROR("Beyond HD analog capabilities\n"); 448 return; 449 case VID_HD_74M: 450 /* HD use alternate 2x filter */ 451 filter_mode = CFG_AWG_FLTR_MODE_HD; 452 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X; 453 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X; 454 coef_y = coef_y_alt_2x; 455 coef_c = coef_c_alt_2x; 456 break; 457 case VID_ED: 458 /* ED uses 4x filter */ 459 filter_mode = CFG_AWG_FLTR_MODE_ED; 460 src_filter_y = HDA_ANA_SRC_Y_CFG_4X; 461 src_filter_c = HDA_ANA_SRC_C_CFG_4X; 462 coef_y = coef_yc_4x; 463 coef_c = coef_yc_4x; 464 break; 465 case VID_SD: 466 DRM_ERROR("Not supported\n"); 467 return; 468 default: 469 DRM_ERROR("Undefined resolution\n"); 470 return; 471 } 472 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx); 473 474 /* Enable HD Video DACs */ 475 hda_enable_hd_dacs(hda, true); 476 477 /* Configure scaler */ 478 hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y); 479 hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB); 480 hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR); 481 482 /* Configure sampler */ 483 hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG); 484 hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG); 485 for (i = 0; i < SAMPLER_COEF_NB; i++) { 486 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4); 487 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4); 488 } 489 490 /* Configure main HDFormatter */ 491 val = 0; 492 val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? 493 0 : CFG_AWG_ASYNC_VSYNC_MTD; 494 val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); 495 val |= filter_mode; 496 hda_write(hda, val, HDA_ANA_CFG); 497 498 /* Configure AWG */ 499 sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr, 500 hda_supported_modes[mode_idx].nb_instr); 501 502 /* Enable AWG */ 503 val = hda_read(hda, HDA_ANA_CFG); 504 val |= CFG_AWG_ASYNC_EN; 505 hda_write(hda, val, HDA_ANA_CFG); 506 507 hda->enabled = true; 508 } 509 510 static void sti_hda_set_mode(struct drm_bridge *bridge, 511 struct drm_display_mode *mode, 512 struct drm_display_mode *adjusted_mode) 513 { 514 struct sti_hda *hda = bridge->driver_private; 515 u32 mode_idx; 516 int hddac_rate; 517 int ret; 518 519 DRM_DEBUG_DRIVER("\n"); 520 521 memcpy(&hda->mode, mode, sizeof(struct drm_display_mode)); 522 523 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 524 DRM_ERROR("Undefined mode\n"); 525 return; 526 } 527 528 switch (hda_supported_modes[mode_idx].vid_cat) { 529 case VID_HD_74M: 530 /* HD use alternate 2x filter */ 531 hddac_rate = mode->clock * 1000 * 2; 532 break; 533 case VID_ED: 534 /* ED uses 4x filter */ 535 hddac_rate = mode->clock * 1000 * 4; 536 break; 537 default: 538 DRM_ERROR("Undefined mode\n"); 539 return; 540 } 541 542 /* HD DAC = 148.5Mhz or 108 Mhz */ 543 ret = clk_set_rate(hda->clk_hddac, hddac_rate); 544 if (ret < 0) 545 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n", 546 hddac_rate); 547 548 /* HDformatter clock = compositor clock */ 549 ret = clk_set_rate(hda->clk_pix, mode->clock * 1000); 550 if (ret < 0) 551 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n", 552 mode->clock * 1000); 553 } 554 555 static void sti_hda_bridge_nope(struct drm_bridge *bridge) 556 { 557 /* do nothing */ 558 } 559 560 static const struct drm_bridge_funcs sti_hda_bridge_funcs = { 561 .pre_enable = sti_hda_pre_enable, 562 .enable = sti_hda_bridge_nope, 563 .disable = sti_hda_disable, 564 .post_disable = sti_hda_bridge_nope, 565 .mode_set = sti_hda_set_mode, 566 }; 567 568 static int sti_hda_connector_get_modes(struct drm_connector *connector) 569 { 570 unsigned int i; 571 int count = 0; 572 struct sti_hda_connector *hda_connector 573 = to_sti_hda_connector(connector); 574 struct sti_hda *hda = hda_connector->hda; 575 576 DRM_DEBUG_DRIVER("\n"); 577 578 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { 579 struct drm_display_mode *mode = 580 drm_mode_duplicate(hda->drm_dev, 581 &hda_supported_modes[i].mode); 582 if (!mode) 583 continue; 584 mode->vrefresh = drm_mode_vrefresh(mode); 585 586 /* the first mode is the preferred mode */ 587 if (i == 0) 588 mode->type |= DRM_MODE_TYPE_PREFERRED; 589 590 drm_mode_probed_add(connector, mode); 591 count++; 592 } 593 594 return count; 595 } 596 597 #define CLK_TOLERANCE_HZ 50 598 599 static int sti_hda_connector_mode_valid(struct drm_connector *connector, 600 struct drm_display_mode *mode) 601 { 602 int target = mode->clock * 1000; 603 int target_min = target - CLK_TOLERANCE_HZ; 604 int target_max = target + CLK_TOLERANCE_HZ; 605 int result; 606 int idx; 607 struct sti_hda_connector *hda_connector 608 = to_sti_hda_connector(connector); 609 struct sti_hda *hda = hda_connector->hda; 610 611 if (!hda_get_mode_idx(*mode, &idx)) { 612 return MODE_BAD; 613 } else { 614 result = clk_round_rate(hda->clk_pix, target); 615 616 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 617 target, result); 618 619 if ((result < target_min) || (result > target_max)) { 620 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n", 621 target); 622 return MODE_BAD; 623 } 624 } 625 626 return MODE_OK; 627 } 628 629 static const 630 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = { 631 .get_modes = sti_hda_connector_get_modes, 632 .mode_valid = sti_hda_connector_mode_valid, 633 }; 634 635 static int sti_hda_late_register(struct drm_connector *connector) 636 { 637 struct sti_hda_connector *hda_connector 638 = to_sti_hda_connector(connector); 639 struct sti_hda *hda = hda_connector->hda; 640 641 if (hda_debugfs_init(hda, hda->drm_dev->primary)) { 642 DRM_ERROR("HDA debugfs setup failed\n"); 643 return -EINVAL; 644 } 645 646 return 0; 647 } 648 649 static const struct drm_connector_funcs sti_hda_connector_funcs = { 650 .dpms = drm_atomic_helper_connector_dpms, 651 .fill_modes = drm_helper_probe_single_connector_modes, 652 .destroy = drm_connector_cleanup, 653 .reset = drm_atomic_helper_connector_reset, 654 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 656 .late_register = sti_hda_late_register, 657 }; 658 659 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev) 660 { 661 struct drm_encoder *encoder; 662 663 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 664 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC) 665 return encoder; 666 } 667 668 return NULL; 669 } 670 671 static int sti_hda_bind(struct device *dev, struct device *master, void *data) 672 { 673 struct sti_hda *hda = dev_get_drvdata(dev); 674 struct drm_device *drm_dev = data; 675 struct drm_encoder *encoder; 676 struct sti_hda_connector *connector; 677 struct drm_connector *drm_connector; 678 struct drm_bridge *bridge; 679 int err; 680 681 /* Set the drm device handle */ 682 hda->drm_dev = drm_dev; 683 684 encoder = sti_hda_find_encoder(drm_dev); 685 if (!encoder) 686 return -ENOMEM; 687 688 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 689 if (!connector) 690 return -ENOMEM; 691 692 connector->hda = hda; 693 694 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 695 if (!bridge) 696 return -ENOMEM; 697 698 bridge->driver_private = hda; 699 bridge->funcs = &sti_hda_bridge_funcs; 700 drm_bridge_attach(encoder, bridge, NULL); 701 702 connector->encoder = encoder; 703 704 drm_connector = (struct drm_connector *)connector; 705 706 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 707 708 drm_connector_init(drm_dev, drm_connector, 709 &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component); 710 drm_connector_helper_add(drm_connector, 711 &sti_hda_connector_helper_funcs); 712 713 err = drm_mode_connector_attach_encoder(drm_connector, encoder); 714 if (err) { 715 DRM_ERROR("Failed to attach a connector to a encoder\n"); 716 goto err_sysfs; 717 } 718 719 /* force to disable hd dacs at startup */ 720 hda_enable_hd_dacs(hda, false); 721 722 return 0; 723 724 err_sysfs: 725 drm_bridge_remove(bridge); 726 return -EINVAL; 727 } 728 729 static void sti_hda_unbind(struct device *dev, 730 struct device *master, void *data) 731 { 732 } 733 734 static const struct component_ops sti_hda_ops = { 735 .bind = sti_hda_bind, 736 .unbind = sti_hda_unbind, 737 }; 738 739 static int sti_hda_probe(struct platform_device *pdev) 740 { 741 struct device *dev = &pdev->dev; 742 struct sti_hda *hda; 743 struct resource *res; 744 745 DRM_INFO("%s\n", __func__); 746 747 hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL); 748 if (!hda) 749 return -ENOMEM; 750 751 hda->dev = pdev->dev; 752 753 /* Get resources */ 754 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg"); 755 if (!res) { 756 DRM_ERROR("Invalid hda resource\n"); 757 return -ENOMEM; 758 } 759 hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 760 if (!hda->regs) 761 return -ENOMEM; 762 763 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 764 "video-dacs-ctrl"); 765 if (res) { 766 hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start, 767 resource_size(res)); 768 if (!hda->video_dacs_ctrl) 769 return -ENOMEM; 770 } else { 771 /* If no existing video-dacs-ctrl resource continue the probe */ 772 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); 773 hda->video_dacs_ctrl = NULL; 774 } 775 776 /* Get clock resources */ 777 hda->clk_pix = devm_clk_get(dev, "pix"); 778 if (IS_ERR(hda->clk_pix)) { 779 DRM_ERROR("Cannot get hda_pix clock\n"); 780 return PTR_ERR(hda->clk_pix); 781 } 782 783 hda->clk_hddac = devm_clk_get(dev, "hddac"); 784 if (IS_ERR(hda->clk_hddac)) { 785 DRM_ERROR("Cannot get hda_hddac clock\n"); 786 return PTR_ERR(hda->clk_hddac); 787 } 788 789 platform_set_drvdata(pdev, hda); 790 791 return component_add(&pdev->dev, &sti_hda_ops); 792 } 793 794 static int sti_hda_remove(struct platform_device *pdev) 795 { 796 component_del(&pdev->dev, &sti_hda_ops); 797 return 0; 798 } 799 800 static const struct of_device_id hda_of_match[] = { 801 { .compatible = "st,stih416-hda", }, 802 { .compatible = "st,stih407-hda", }, 803 { /* end node */ } 804 }; 805 MODULE_DEVICE_TABLE(of, hda_of_match); 806 807 struct platform_driver sti_hda_driver = { 808 .driver = { 809 .name = "sti-hda", 810 .owner = THIS_MODULE, 811 .of_match_table = hda_of_match, 812 }, 813 .probe = sti_hda_probe, 814 .remove = sti_hda_remove, 815 }; 816 817 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 818 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 819 MODULE_LICENSE("GPL"); 820