1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * for STMicroelectronics. 7 */ 8 9 #include <linux/dma-mapping.h> 10 #include <linux/of.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_fb_dma_helper.h> 16 #include <drm/drm_fourcc.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_dma_helper.h> 19 #include <drm/drm_print.h> 20 21 #include "sti_compositor.h" 22 #include "sti_gdp.h" 23 #include "sti_plane.h" 24 #include "sti_vtg.h" 25 26 #define ALPHASWITCH BIT(6) 27 #define ENA_COLOR_FILL BIT(8) 28 #define BIGNOTLITTLE BIT(23) 29 #define WAIT_NEXT_VSYNC BIT(31) 30 31 /* GDP color formats */ 32 #define GDP_RGB565 0x00 33 #define GDP_RGB888 0x01 34 #define GDP_RGB888_32 0x02 35 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 36 #define GDP_ARGB8565 0x04 37 #define GDP_ARGB8888 0x05 38 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 39 #define GDP_ARGB1555 0x06 40 #define GDP_ARGB4444 0x07 41 42 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 43 44 static struct gdp_format_to_str { 45 int format; 46 char name[20]; 47 } gdp_format_to_str[] = { 48 GDP2STR(RGB565), 49 GDP2STR(RGB888), 50 GDP2STR(RGB888_32), 51 GDP2STR(XBGR8888), 52 GDP2STR(ARGB8565), 53 GDP2STR(ARGB8888), 54 GDP2STR(ABGR8888), 55 GDP2STR(ARGB1555), 56 GDP2STR(ARGB4444) 57 }; 58 59 #define GAM_GDP_CTL_OFFSET 0x00 60 #define GAM_GDP_AGC_OFFSET 0x04 61 #define GAM_GDP_VPO_OFFSET 0x0C 62 #define GAM_GDP_VPS_OFFSET 0x10 63 #define GAM_GDP_PML_OFFSET 0x14 64 #define GAM_GDP_PMP_OFFSET 0x18 65 #define GAM_GDP_SIZE_OFFSET 0x1C 66 #define GAM_GDP_NVN_OFFSET 0x24 67 #define GAM_GDP_KEY1_OFFSET 0x28 68 #define GAM_GDP_KEY2_OFFSET 0x2C 69 #define GAM_GDP_PPT_OFFSET 0x34 70 #define GAM_GDP_CML_OFFSET 0x3C 71 #define GAM_GDP_MST_OFFSET 0x68 72 73 #define GAM_GDP_ALPHARANGE_255 BIT(5) 74 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 75 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 76 77 #define GAM_GDP_SIZE_MAX_WIDTH 3840 78 #define GAM_GDP_SIZE_MAX_HEIGHT 2160 79 80 #define GDP_NODE_NB_BANK 2 81 #define GDP_NODE_PER_FIELD 2 82 83 struct sti_gdp_node { 84 u32 gam_gdp_ctl; 85 u32 gam_gdp_agc; 86 u32 reserved1; 87 u32 gam_gdp_vpo; 88 u32 gam_gdp_vps; 89 u32 gam_gdp_pml; 90 u32 gam_gdp_pmp; 91 u32 gam_gdp_size; 92 u32 reserved2; 93 u32 gam_gdp_nvn; 94 u32 gam_gdp_key1; 95 u32 gam_gdp_key2; 96 u32 reserved3; 97 u32 gam_gdp_ppt; 98 u32 reserved4; 99 u32 gam_gdp_cml; 100 }; 101 102 struct sti_gdp_node_list { 103 struct sti_gdp_node *top_field; 104 dma_addr_t top_field_paddr; 105 struct sti_gdp_node *btm_field; 106 dma_addr_t btm_field_paddr; 107 }; 108 109 /* 110 * STI GDP structure 111 * 112 * @sti_plane: sti_plane structure 113 * @dev: driver device 114 * @regs: gdp registers 115 * @clk_pix: pixel clock for the current gdp 116 * @clk_main_parent: gdp parent clock if main path used 117 * @clk_aux_parent: gdp parent clock if aux path used 118 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 119 * @is_curr_top: true if the current node processed is the top field 120 * @node_list: array of node list 121 * @vtg: registered vtg 122 */ 123 struct sti_gdp { 124 struct sti_plane plane; 125 struct device *dev; 126 void __iomem *regs; 127 struct clk *clk_pix; 128 struct clk *clk_main_parent; 129 struct clk *clk_aux_parent; 130 struct notifier_block vtg_field_nb; 131 bool is_curr_top; 132 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 133 struct sti_vtg *vtg; 134 }; 135 136 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 137 138 static const uint32_t gdp_supported_formats[] = { 139 DRM_FORMAT_XRGB8888, 140 DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_ARGB8888, 142 DRM_FORMAT_ABGR8888, 143 DRM_FORMAT_ARGB4444, 144 DRM_FORMAT_ARGB1555, 145 DRM_FORMAT_RGB565, 146 DRM_FORMAT_RGB888, 147 }; 148 149 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 150 readl(gdp->regs + reg ## _OFFSET)) 151 152 static void gdp_dbg_ctl(struct seq_file *s, int val) 153 { 154 int i; 155 156 seq_puts(s, "\tColor:"); 157 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 158 if (gdp_format_to_str[i].format == (val & 0x1F)) { 159 seq_puts(s, gdp_format_to_str[i].name); 160 break; 161 } 162 } 163 if (i == ARRAY_SIZE(gdp_format_to_str)) 164 seq_puts(s, "<UNKNOWN>"); 165 166 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 167 } 168 169 static void gdp_dbg_vpo(struct seq_file *s, int val) 170 { 171 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 172 } 173 174 static void gdp_dbg_vps(struct seq_file *s, int val) 175 { 176 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 177 } 178 179 static void gdp_dbg_size(struct seq_file *s, int val) 180 { 181 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 182 } 183 184 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 185 { 186 void *base = NULL; 187 unsigned int i; 188 189 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 190 if (gdp->node_list[i].top_field_paddr == val) { 191 base = gdp->node_list[i].top_field; 192 break; 193 } 194 if (gdp->node_list[i].btm_field_paddr == val) { 195 base = gdp->node_list[i].btm_field; 196 break; 197 } 198 } 199 200 if (base) 201 seq_printf(s, "\tVirt @: %p", base); 202 } 203 204 static void gdp_dbg_ppt(struct seq_file *s, int val) 205 { 206 if (val & GAM_GDP_PPT_IGNORE) 207 seq_puts(s, "\tNot displayed on mixer!"); 208 } 209 210 static void gdp_dbg_mst(struct seq_file *s, int val) 211 { 212 if (val & 1) 213 seq_puts(s, "\tBUFFER UNDERFLOW!"); 214 } 215 216 static int gdp_dbg_show(struct seq_file *s, void *data) 217 { 218 struct drm_info_node *node = s->private; 219 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 220 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 221 struct drm_crtc *crtc; 222 223 drm_modeset_lock(&drm_plane->mutex, NULL); 224 crtc = drm_plane->state->crtc; 225 drm_modeset_unlock(&drm_plane->mutex); 226 227 seq_printf(s, "%s: (vaddr = 0x%p)", 228 sti_plane_to_str(&gdp->plane), gdp->regs); 229 230 DBGFS_DUMP(GAM_GDP_CTL); 231 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 232 DBGFS_DUMP(GAM_GDP_AGC); 233 DBGFS_DUMP(GAM_GDP_VPO); 234 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 235 DBGFS_DUMP(GAM_GDP_VPS); 236 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 237 DBGFS_DUMP(GAM_GDP_PML); 238 DBGFS_DUMP(GAM_GDP_PMP); 239 DBGFS_DUMP(GAM_GDP_SIZE); 240 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 241 DBGFS_DUMP(GAM_GDP_NVN); 242 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 243 DBGFS_DUMP(GAM_GDP_KEY1); 244 DBGFS_DUMP(GAM_GDP_KEY2); 245 DBGFS_DUMP(GAM_GDP_PPT); 246 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 247 DBGFS_DUMP(GAM_GDP_CML); 248 DBGFS_DUMP(GAM_GDP_MST); 249 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 250 251 seq_puts(s, "\n\n"); 252 if (!crtc) 253 seq_puts(s, " Not connected to any DRM CRTC\n"); 254 else 255 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 256 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 257 258 return 0; 259 } 260 261 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 262 { 263 seq_printf(s, "\t@:0x%p", node); 264 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 265 gdp_dbg_ctl(s, node->gam_gdp_ctl); 266 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 267 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 268 gdp_dbg_vpo(s, node->gam_gdp_vpo); 269 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 270 gdp_dbg_vps(s, node->gam_gdp_vps); 271 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 272 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 273 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 274 gdp_dbg_size(s, node->gam_gdp_size); 275 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 276 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 277 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 278 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 279 gdp_dbg_ppt(s, node->gam_gdp_ppt); 280 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); 281 } 282 283 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 284 { 285 struct drm_info_node *node = s->private; 286 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 287 unsigned int b; 288 289 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 290 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 291 gdp_node_dump_node(s, gdp->node_list[b].top_field); 292 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 293 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 294 } 295 296 return 0; 297 } 298 299 static struct drm_info_list gdp0_debugfs_files[] = { 300 { "gdp0", gdp_dbg_show, 0, NULL }, 301 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 302 }; 303 304 static struct drm_info_list gdp1_debugfs_files[] = { 305 { "gdp1", gdp_dbg_show, 0, NULL }, 306 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 307 }; 308 309 static struct drm_info_list gdp2_debugfs_files[] = { 310 { "gdp2", gdp_dbg_show, 0, NULL }, 311 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 312 }; 313 314 static struct drm_info_list gdp3_debugfs_files[] = { 315 { "gdp3", gdp_dbg_show, 0, NULL }, 316 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 317 }; 318 319 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 320 { 321 unsigned int i; 322 struct drm_info_list *gdp_debugfs_files; 323 int nb_files; 324 325 switch (gdp->plane.desc) { 326 case STI_GDP_0: 327 gdp_debugfs_files = gdp0_debugfs_files; 328 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 329 break; 330 case STI_GDP_1: 331 gdp_debugfs_files = gdp1_debugfs_files; 332 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 333 break; 334 case STI_GDP_2: 335 gdp_debugfs_files = gdp2_debugfs_files; 336 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 337 break; 338 case STI_GDP_3: 339 gdp_debugfs_files = gdp3_debugfs_files; 340 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 341 break; 342 default: 343 return -EINVAL; 344 } 345 346 for (i = 0; i < nb_files; i++) 347 gdp_debugfs_files[i].data = gdp; 348 349 drm_debugfs_create_files(gdp_debugfs_files, 350 nb_files, 351 minor->debugfs_root, minor); 352 return 0; 353 } 354 355 static int sti_gdp_fourcc2format(int fourcc) 356 { 357 switch (fourcc) { 358 case DRM_FORMAT_XRGB8888: 359 return GDP_RGB888_32; 360 case DRM_FORMAT_XBGR8888: 361 return GDP_XBGR8888; 362 case DRM_FORMAT_ARGB8888: 363 return GDP_ARGB8888; 364 case DRM_FORMAT_ABGR8888: 365 return GDP_ABGR8888; 366 case DRM_FORMAT_ARGB4444: 367 return GDP_ARGB4444; 368 case DRM_FORMAT_ARGB1555: 369 return GDP_ARGB1555; 370 case DRM_FORMAT_RGB565: 371 return GDP_RGB565; 372 case DRM_FORMAT_RGB888: 373 return GDP_RGB888; 374 } 375 return -1; 376 } 377 378 static int sti_gdp_get_alpharange(int format) 379 { 380 switch (format) { 381 case GDP_ARGB8565: 382 case GDP_ARGB8888: 383 case GDP_ABGR8888: 384 return GAM_GDP_ALPHARANGE_255; 385 } 386 return 0; 387 } 388 389 /** 390 * sti_gdp_get_free_nodes 391 * @gdp: gdp pointer 392 * 393 * Look for a GDP node list that is not currently read by the HW. 394 * 395 * RETURNS: 396 * Pointer to the free GDP node list 397 */ 398 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 399 { 400 int hw_nvn; 401 unsigned int i; 402 403 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 404 if (!hw_nvn) 405 goto end; 406 407 for (i = 0; i < GDP_NODE_NB_BANK; i++) 408 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 409 (hw_nvn != gdp->node_list[i].top_field_paddr)) 410 return &gdp->node_list[i]; 411 412 /* in hazardous cases restart with the first node */ 413 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 414 sti_plane_to_str(&gdp->plane), hw_nvn); 415 416 end: 417 return &gdp->node_list[0]; 418 } 419 420 /** 421 * sti_gdp_get_current_nodes 422 * @gdp: gdp pointer 423 * 424 * Look for GDP nodes that are currently read by the HW. 425 * 426 * RETURNS: 427 * Pointer to the current GDP node list 428 */ 429 static 430 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 431 { 432 int hw_nvn; 433 unsigned int i; 434 435 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 436 if (!hw_nvn) 437 goto end; 438 439 for (i = 0; i < GDP_NODE_NB_BANK; i++) 440 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 441 (hw_nvn == gdp->node_list[i].top_field_paddr)) 442 return &gdp->node_list[i]; 443 444 end: 445 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 446 hw_nvn, sti_plane_to_str(&gdp->plane)); 447 448 return NULL; 449 } 450 451 /** 452 * sti_gdp_disable 453 * @gdp: gdp pointer 454 * 455 * Disable a GDP. 456 */ 457 static void sti_gdp_disable(struct sti_gdp *gdp) 458 { 459 unsigned int i; 460 461 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 462 463 /* Set the nodes as 'to be ignored on mixer' */ 464 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 465 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 466 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 467 } 468 469 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 470 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 471 472 if (gdp->clk_pix) 473 clk_disable_unprepare(gdp->clk_pix); 474 475 gdp->plane.status = STI_PLANE_DISABLED; 476 gdp->vtg = NULL; 477 } 478 479 /** 480 * sti_gdp_field_cb 481 * @nb: notifier block 482 * @event: event message 483 * @data: private data 484 * 485 * Handle VTG top field and bottom field event. 486 * 487 * RETURNS: 488 * 0 on success. 489 */ 490 static int sti_gdp_field_cb(struct notifier_block *nb, 491 unsigned long event, void *data) 492 { 493 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 494 495 if (gdp->plane.status == STI_PLANE_FLUSHING) { 496 /* disable need to be synchronize on vsync event */ 497 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 498 sti_plane_to_str(&gdp->plane)); 499 500 sti_gdp_disable(gdp); 501 } 502 503 switch (event) { 504 case VTG_TOP_FIELD_EVENT: 505 gdp->is_curr_top = true; 506 break; 507 case VTG_BOTTOM_FIELD_EVENT: 508 gdp->is_curr_top = false; 509 break; 510 default: 511 DRM_ERROR("unsupported event: %lu\n", event); 512 break; 513 } 514 515 return 0; 516 } 517 518 static void sti_gdp_init(struct sti_gdp *gdp) 519 { 520 struct device_node *np = gdp->dev->of_node; 521 dma_addr_t dma_addr; 522 void *base; 523 unsigned int i, size; 524 525 /* Allocate all the nodes within a single memory page */ 526 size = sizeof(struct sti_gdp_node) * 527 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 528 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); 529 530 if (!base) { 531 DRM_ERROR("Failed to allocate memory for GDP node\n"); 532 return; 533 } 534 memset(base, 0, size); 535 536 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 537 if (dma_addr & 0xF) { 538 DRM_ERROR("Mem alignment failed\n"); 539 return; 540 } 541 gdp->node_list[i].top_field = base; 542 gdp->node_list[i].top_field_paddr = dma_addr; 543 544 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 545 base += sizeof(struct sti_gdp_node); 546 dma_addr += sizeof(struct sti_gdp_node); 547 548 if (dma_addr & 0xF) { 549 DRM_ERROR("Mem alignment failed\n"); 550 return; 551 } 552 gdp->node_list[i].btm_field = base; 553 gdp->node_list[i].btm_field_paddr = dma_addr; 554 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 555 base += sizeof(struct sti_gdp_node); 556 dma_addr += sizeof(struct sti_gdp_node); 557 } 558 559 if (of_device_is_compatible(np, "st,stih407-compositor")) { 560 /* GDP of STiH407 chip have its own pixel clock */ 561 char *clk_name; 562 563 switch (gdp->plane.desc) { 564 case STI_GDP_0: 565 clk_name = "pix_gdp1"; 566 break; 567 case STI_GDP_1: 568 clk_name = "pix_gdp2"; 569 break; 570 case STI_GDP_2: 571 clk_name = "pix_gdp3"; 572 break; 573 case STI_GDP_3: 574 clk_name = "pix_gdp4"; 575 break; 576 default: 577 DRM_ERROR("GDP id not recognized\n"); 578 return; 579 } 580 581 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 582 if (IS_ERR(gdp->clk_pix)) 583 DRM_ERROR("Cannot get %s clock\n", clk_name); 584 585 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 586 if (IS_ERR(gdp->clk_main_parent)) 587 DRM_ERROR("Cannot get main_parent clock\n"); 588 589 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 590 if (IS_ERR(gdp->clk_aux_parent)) 591 DRM_ERROR("Cannot get aux_parent clock\n"); 592 } 593 } 594 595 /** 596 * sti_gdp_get_dst 597 * @dev: device 598 * @dst: requested destination size 599 * @src: source size 600 * 601 * Return the cropped / clamped destination size 602 * 603 * RETURNS: 604 * cropped / clamped destination size 605 */ 606 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 607 { 608 if (dst == src) 609 return dst; 610 611 if (dst < src) { 612 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 613 return dst; 614 } 615 616 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 617 return src; 618 } 619 620 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 621 struct drm_atomic_state *state) 622 { 623 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 624 drm_plane); 625 struct sti_plane *plane = to_sti_plane(drm_plane); 626 struct sti_gdp *gdp = to_sti_gdp(plane); 627 struct drm_crtc *crtc = new_plane_state->crtc; 628 struct drm_framebuffer *fb = new_plane_state->fb; 629 struct drm_crtc_state *crtc_state; 630 struct sti_mixer *mixer; 631 struct drm_display_mode *mode; 632 int dst_x, dst_y, dst_w, dst_h; 633 int src_x, src_y, src_w, src_h; 634 int format; 635 636 /* no need for further checks if the plane is being disabled */ 637 if (!crtc || !fb) 638 return 0; 639 640 mixer = to_sti_mixer(crtc); 641 crtc_state = drm_atomic_get_crtc_state(state, crtc); 642 if (IS_ERR(crtc_state)) 643 return PTR_ERR(crtc_state); 644 645 mode = &crtc_state->mode; 646 dst_x = new_plane_state->crtc_x; 647 dst_y = new_plane_state->crtc_y; 648 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x); 649 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); 650 /* src_x are in 16.16 format */ 651 src_x = new_plane_state->src_x >> 16; 652 src_y = new_plane_state->src_y >> 16; 653 src_w = clamp_val(new_plane_state->src_w >> 16, 0, 654 GAM_GDP_SIZE_MAX_WIDTH); 655 src_h = clamp_val(new_plane_state->src_h >> 16, 0, 656 GAM_GDP_SIZE_MAX_HEIGHT); 657 658 format = sti_gdp_fourcc2format(fb->format->format); 659 if (format == -1) { 660 DRM_ERROR("Format not supported by GDP %.4s\n", 661 (char *)&fb->format->format); 662 return -EINVAL; 663 } 664 665 if (!drm_fb_dma_get_gem_obj(fb, 0)) { 666 DRM_ERROR("Can't get DMA GEM object for fb\n"); 667 return -EINVAL; 668 } 669 670 /* Set gdp clock */ 671 if (mode->clock && gdp->clk_pix) { 672 struct clk *clkp; 673 int rate = mode->clock * 1000; 674 int res; 675 676 /* 677 * According to the mixer used, the gdp pixel clock 678 * should have a different parent clock. 679 */ 680 if (mixer->id == STI_MIXER_MAIN) 681 clkp = gdp->clk_main_parent; 682 else 683 clkp = gdp->clk_aux_parent; 684 685 if (clkp) 686 clk_set_parent(gdp->clk_pix, clkp); 687 688 res = clk_set_rate(gdp->clk_pix, rate); 689 if (res < 0) { 690 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 691 rate); 692 return -EINVAL; 693 } 694 } 695 696 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 697 crtc->base.id, sti_mixer_to_str(mixer), 698 drm_plane->base.id, sti_plane_to_str(plane)); 699 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 700 sti_plane_to_str(plane), 701 dst_w, dst_h, dst_x, dst_y, 702 src_w, src_h, src_x, src_y); 703 704 return 0; 705 } 706 707 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 708 struct drm_atomic_state *state) 709 { 710 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 711 drm_plane); 712 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 713 drm_plane); 714 struct sti_plane *plane = to_sti_plane(drm_plane); 715 struct sti_gdp *gdp = to_sti_gdp(plane); 716 struct drm_crtc *crtc = newstate->crtc; 717 struct drm_framebuffer *fb = newstate->fb; 718 struct drm_display_mode *mode; 719 int dst_x, dst_y, dst_w, dst_h; 720 int src_x, src_y, src_w, src_h; 721 struct drm_gem_dma_object *dma_obj; 722 struct sti_gdp_node_list *list; 723 struct sti_gdp_node_list *curr_list; 724 struct sti_gdp_node *top_field, *btm_field; 725 u32 dma_updated_top; 726 u32 dma_updated_btm; 727 int format; 728 unsigned int bpp; 729 u32 ydo, xdo, yds, xds; 730 731 if (!crtc || !fb) 732 return; 733 734 if ((oldstate->fb == newstate->fb) && 735 (oldstate->crtc_x == newstate->crtc_x) && 736 (oldstate->crtc_y == newstate->crtc_y) && 737 (oldstate->crtc_w == newstate->crtc_w) && 738 (oldstate->crtc_h == newstate->crtc_h) && 739 (oldstate->src_x == newstate->src_x) && 740 (oldstate->src_y == newstate->src_y) && 741 (oldstate->src_w == newstate->src_w) && 742 (oldstate->src_h == newstate->src_h)) { 743 /* No change since last update, do not post cmd */ 744 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 745 plane->status = STI_PLANE_UPDATED; 746 return; 747 } 748 749 if (!gdp->vtg) { 750 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 751 struct sti_mixer *mixer = to_sti_mixer(crtc); 752 753 /* Register gdp callback */ 754 gdp->vtg = compo->vtg[mixer->id]; 755 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 756 clk_prepare_enable(gdp->clk_pix); 757 } 758 759 mode = &crtc->mode; 760 dst_x = newstate->crtc_x; 761 dst_y = newstate->crtc_y; 762 dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x); 763 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y); 764 /* src_x are in 16.16 format */ 765 src_x = newstate->src_x >> 16; 766 src_y = newstate->src_y >> 16; 767 src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 768 src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 769 770 list = sti_gdp_get_free_nodes(gdp); 771 top_field = list->top_field; 772 btm_field = list->btm_field; 773 774 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 775 sti_plane_to_str(plane), top_field, btm_field); 776 777 /* build the top field */ 778 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 779 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 780 format = sti_gdp_fourcc2format(fb->format->format); 781 top_field->gam_gdp_ctl |= format; 782 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 783 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 784 785 dma_obj = drm_fb_dma_get_gem_obj(fb, 0); 786 787 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 788 (char *)&fb->format->format, 789 (unsigned long) dma_obj->dma_addr); 790 791 /* pixel memory location */ 792 bpp = fb->format->cpp[0]; 793 top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0]; 794 top_field->gam_gdp_pml += src_x * bpp; 795 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 796 797 /* output parameters (clamped / cropped) */ 798 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 799 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 800 ydo = sti_vtg_get_line_number(*mode, dst_y); 801 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 802 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 803 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 804 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 805 top_field->gam_gdp_vps = (yds << 16) | xds; 806 807 /* input parameters */ 808 src_w = dst_w; 809 top_field->gam_gdp_pmp = fb->pitches[0]; 810 top_field->gam_gdp_size = src_h << 16 | src_w; 811 812 /* Same content and chained together */ 813 memcpy(btm_field, top_field, sizeof(*btm_field)); 814 top_field->gam_gdp_nvn = list->btm_field_paddr; 815 btm_field->gam_gdp_nvn = list->top_field_paddr; 816 817 /* Interlaced mode */ 818 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 819 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 820 fb->pitches[0]; 821 822 /* Update the NVN field of the 'right' field of the current GDP node 823 * (being used by the HW) with the address of the updated ('free') top 824 * field GDP node. 825 * - In interlaced mode the 'right' field is the bottom field as we 826 * update frames starting from their top field 827 * - In progressive mode, we update both bottom and top fields which 828 * are equal nodes. 829 * At the next VSYNC, the updated node list will be used by the HW. 830 */ 831 curr_list = sti_gdp_get_current_nodes(gdp); 832 dma_updated_top = list->top_field_paddr; 833 dma_updated_btm = list->btm_field_paddr; 834 835 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 836 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 837 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 838 (unsigned long) dma_obj->dma_addr, 839 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 840 841 if (!curr_list) { 842 /* First update or invalid node should directly write in the 843 * hw register */ 844 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 845 sti_plane_to_str(plane)); 846 847 writel(gdp->is_curr_top ? 848 dma_updated_btm : dma_updated_top, 849 gdp->regs + GAM_GDP_NVN_OFFSET); 850 goto end; 851 } 852 853 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 854 if (gdp->is_curr_top) { 855 /* Do not update in the middle of the frame, but 856 * postpone the update after the bottom field has 857 * been displayed */ 858 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 859 } else { 860 /* Direct update to avoid one frame delay */ 861 writel(dma_updated_top, 862 gdp->regs + GAM_GDP_NVN_OFFSET); 863 } 864 } else { 865 /* Direct update for progressive to avoid one frame delay */ 866 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 867 } 868 869 end: 870 sti_plane_update_fps(plane, true, false); 871 872 plane->status = STI_PLANE_UPDATED; 873 } 874 875 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 876 struct drm_atomic_state *state) 877 { 878 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 879 drm_plane); 880 struct sti_plane *plane = to_sti_plane(drm_plane); 881 882 if (!oldstate->crtc) { 883 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 884 drm_plane->base.id); 885 return; 886 } 887 888 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 889 oldstate->crtc->base.id, 890 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 891 drm_plane->base.id, sti_plane_to_str(plane)); 892 893 plane->status = STI_PLANE_DISABLING; 894 } 895 896 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 897 .atomic_check = sti_gdp_atomic_check, 898 .atomic_update = sti_gdp_atomic_update, 899 .atomic_disable = sti_gdp_atomic_disable, 900 }; 901 902 static int sti_gdp_late_register(struct drm_plane *drm_plane) 903 { 904 struct sti_plane *plane = to_sti_plane(drm_plane); 905 struct sti_gdp *gdp = to_sti_gdp(plane); 906 907 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 908 } 909 910 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 911 .update_plane = drm_atomic_helper_update_plane, 912 .disable_plane = drm_atomic_helper_disable_plane, 913 .destroy = drm_plane_cleanup, 914 .reset = drm_atomic_helper_plane_reset, 915 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 916 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 917 .late_register = sti_gdp_late_register, 918 }; 919 920 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 921 struct device *dev, int desc, 922 void __iomem *baseaddr, 923 unsigned int possible_crtcs, 924 enum drm_plane_type type) 925 { 926 struct sti_gdp *gdp; 927 int res; 928 929 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 930 if (!gdp) { 931 DRM_ERROR("Failed to allocate memory for GDP\n"); 932 return NULL; 933 } 934 935 gdp->dev = dev; 936 gdp->regs = baseaddr; 937 gdp->plane.desc = desc; 938 gdp->plane.status = STI_PLANE_DISABLED; 939 940 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 941 942 sti_gdp_init(gdp); 943 944 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 945 possible_crtcs, 946 &sti_gdp_plane_helpers_funcs, 947 gdp_supported_formats, 948 ARRAY_SIZE(gdp_supported_formats), 949 NULL, type, NULL); 950 if (res) { 951 DRM_ERROR("Failed to initialize universal plane\n"); 952 goto err; 953 } 954 955 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 956 957 sti_plane_init_property(&gdp->plane, type); 958 959 return &gdp->plane.drm_plane; 960 961 err: 962 devm_kfree(dev, gdp); 963 return NULL; 964 } 965