1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * for STMicroelectronics. 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 #include <linux/seq_file.h> 9 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_fb_cma_helper.h> 12 #include <drm/drm_gem_cma_helper.h> 13 14 #include "sti_compositor.h" 15 #include "sti_gdp.h" 16 #include "sti_plane.h" 17 #include "sti_vtg.h" 18 19 #define ALPHASWITCH BIT(6) 20 #define ENA_COLOR_FILL BIT(8) 21 #define BIGNOTLITTLE BIT(23) 22 #define WAIT_NEXT_VSYNC BIT(31) 23 24 /* GDP color formats */ 25 #define GDP_RGB565 0x00 26 #define GDP_RGB888 0x01 27 #define GDP_RGB888_32 0x02 28 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 29 #define GDP_ARGB8565 0x04 30 #define GDP_ARGB8888 0x05 31 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 32 #define GDP_ARGB1555 0x06 33 #define GDP_ARGB4444 0x07 34 35 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 36 37 static struct gdp_format_to_str { 38 int format; 39 char name[20]; 40 } gdp_format_to_str[] = { 41 GDP2STR(RGB565), 42 GDP2STR(RGB888), 43 GDP2STR(RGB888_32), 44 GDP2STR(XBGR8888), 45 GDP2STR(ARGB8565), 46 GDP2STR(ARGB8888), 47 GDP2STR(ABGR8888), 48 GDP2STR(ARGB1555), 49 GDP2STR(ARGB4444) 50 }; 51 52 #define GAM_GDP_CTL_OFFSET 0x00 53 #define GAM_GDP_AGC_OFFSET 0x04 54 #define GAM_GDP_VPO_OFFSET 0x0C 55 #define GAM_GDP_VPS_OFFSET 0x10 56 #define GAM_GDP_PML_OFFSET 0x14 57 #define GAM_GDP_PMP_OFFSET 0x18 58 #define GAM_GDP_SIZE_OFFSET 0x1C 59 #define GAM_GDP_NVN_OFFSET 0x24 60 #define GAM_GDP_KEY1_OFFSET 0x28 61 #define GAM_GDP_KEY2_OFFSET 0x2C 62 #define GAM_GDP_PPT_OFFSET 0x34 63 #define GAM_GDP_CML_OFFSET 0x3C 64 #define GAM_GDP_MST_OFFSET 0x68 65 66 #define GAM_GDP_ALPHARANGE_255 BIT(5) 67 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 68 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 69 #define GAM_GDP_SIZE_MAX 0x7FF 70 71 #define GDP_NODE_NB_BANK 2 72 #define GDP_NODE_PER_FIELD 2 73 74 struct sti_gdp_node { 75 u32 gam_gdp_ctl; 76 u32 gam_gdp_agc; 77 u32 reserved1; 78 u32 gam_gdp_vpo; 79 u32 gam_gdp_vps; 80 u32 gam_gdp_pml; 81 u32 gam_gdp_pmp; 82 u32 gam_gdp_size; 83 u32 reserved2; 84 u32 gam_gdp_nvn; 85 u32 gam_gdp_key1; 86 u32 gam_gdp_key2; 87 u32 reserved3; 88 u32 gam_gdp_ppt; 89 u32 reserved4; 90 u32 gam_gdp_cml; 91 }; 92 93 struct sti_gdp_node_list { 94 struct sti_gdp_node *top_field; 95 dma_addr_t top_field_paddr; 96 struct sti_gdp_node *btm_field; 97 dma_addr_t btm_field_paddr; 98 }; 99 100 /** 101 * STI GDP structure 102 * 103 * @sti_plane: sti_plane structure 104 * @dev: driver device 105 * @regs: gdp registers 106 * @clk_pix: pixel clock for the current gdp 107 * @clk_main_parent: gdp parent clock if main path used 108 * @clk_aux_parent: gdp parent clock if aux path used 109 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 110 * @is_curr_top: true if the current node processed is the top field 111 * @node_list: array of node list 112 * @vtg: registered vtg 113 */ 114 struct sti_gdp { 115 struct sti_plane plane; 116 struct device *dev; 117 void __iomem *regs; 118 struct clk *clk_pix; 119 struct clk *clk_main_parent; 120 struct clk *clk_aux_parent; 121 struct notifier_block vtg_field_nb; 122 bool is_curr_top; 123 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 124 struct sti_vtg *vtg; 125 }; 126 127 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 128 129 static const uint32_t gdp_supported_formats[] = { 130 DRM_FORMAT_XRGB8888, 131 DRM_FORMAT_XBGR8888, 132 DRM_FORMAT_ARGB8888, 133 DRM_FORMAT_ABGR8888, 134 DRM_FORMAT_ARGB4444, 135 DRM_FORMAT_ARGB1555, 136 DRM_FORMAT_RGB565, 137 DRM_FORMAT_RGB888, 138 }; 139 140 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 141 readl(gdp->regs + reg ## _OFFSET)) 142 143 static void gdp_dbg_ctl(struct seq_file *s, int val) 144 { 145 int i; 146 147 seq_puts(s, "\tColor:"); 148 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 149 if (gdp_format_to_str[i].format == (val & 0x1F)) { 150 seq_printf(s, gdp_format_to_str[i].name); 151 break; 152 } 153 } 154 if (i == ARRAY_SIZE(gdp_format_to_str)) 155 seq_puts(s, "<UNKNOWN>"); 156 157 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 158 } 159 160 static void gdp_dbg_vpo(struct seq_file *s, int val) 161 { 162 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 163 } 164 165 static void gdp_dbg_vps(struct seq_file *s, int val) 166 { 167 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 168 } 169 170 static void gdp_dbg_size(struct seq_file *s, int val) 171 { 172 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 173 } 174 175 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 176 { 177 void *base = NULL; 178 unsigned int i; 179 180 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 181 if (gdp->node_list[i].top_field_paddr == val) { 182 base = gdp->node_list[i].top_field; 183 break; 184 } 185 if (gdp->node_list[i].btm_field_paddr == val) { 186 base = gdp->node_list[i].btm_field; 187 break; 188 } 189 } 190 191 if (base) 192 seq_printf(s, "\tVirt @: %p", base); 193 } 194 195 static void gdp_dbg_ppt(struct seq_file *s, int val) 196 { 197 if (val & GAM_GDP_PPT_IGNORE) 198 seq_puts(s, "\tNot displayed on mixer!"); 199 } 200 201 static void gdp_dbg_mst(struct seq_file *s, int val) 202 { 203 if (val & 1) 204 seq_puts(s, "\tBUFFER UNDERFLOW!"); 205 } 206 207 static int gdp_dbg_show(struct seq_file *s, void *data) 208 { 209 struct drm_info_node *node = s->private; 210 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 211 struct drm_device *dev = node->minor->dev; 212 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 213 struct drm_crtc *crtc = drm_plane->crtc; 214 int ret; 215 216 ret = mutex_lock_interruptible(&dev->struct_mutex); 217 if (ret) 218 return ret; 219 220 seq_printf(s, "%s: (vaddr = 0x%p)", 221 sti_plane_to_str(&gdp->plane), gdp->regs); 222 223 DBGFS_DUMP(GAM_GDP_CTL); 224 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 225 DBGFS_DUMP(GAM_GDP_AGC); 226 DBGFS_DUMP(GAM_GDP_VPO); 227 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 228 DBGFS_DUMP(GAM_GDP_VPS); 229 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 230 DBGFS_DUMP(GAM_GDP_PML); 231 DBGFS_DUMP(GAM_GDP_PMP); 232 DBGFS_DUMP(GAM_GDP_SIZE); 233 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 234 DBGFS_DUMP(GAM_GDP_NVN); 235 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 236 DBGFS_DUMP(GAM_GDP_KEY1); 237 DBGFS_DUMP(GAM_GDP_KEY2); 238 DBGFS_DUMP(GAM_GDP_PPT); 239 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 240 DBGFS_DUMP(GAM_GDP_CML); 241 DBGFS_DUMP(GAM_GDP_MST); 242 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 243 244 seq_puts(s, "\n\n"); 245 if (!crtc) 246 seq_puts(s, " Not connected to any DRM CRTC\n"); 247 else 248 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 249 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 250 251 mutex_unlock(&dev->struct_mutex); 252 return 0; 253 } 254 255 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 256 { 257 seq_printf(s, "\t@:0x%p", node); 258 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 259 gdp_dbg_ctl(s, node->gam_gdp_ctl); 260 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 261 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 262 gdp_dbg_vpo(s, node->gam_gdp_vpo); 263 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 264 gdp_dbg_vps(s, node->gam_gdp_vps); 265 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 266 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 267 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 268 gdp_dbg_size(s, node->gam_gdp_size); 269 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 270 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 271 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 272 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 273 gdp_dbg_ppt(s, node->gam_gdp_ppt); 274 seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml); 275 seq_puts(s, "\n"); 276 } 277 278 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 279 { 280 struct drm_info_node *node = s->private; 281 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 282 struct drm_device *dev = node->minor->dev; 283 unsigned int b; 284 int ret; 285 286 ret = mutex_lock_interruptible(&dev->struct_mutex); 287 if (ret) 288 return ret; 289 290 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 291 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 292 gdp_node_dump_node(s, gdp->node_list[b].top_field); 293 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 294 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 295 } 296 297 mutex_unlock(&dev->struct_mutex); 298 return 0; 299 } 300 301 static struct drm_info_list gdp0_debugfs_files[] = { 302 { "gdp0", gdp_dbg_show, 0, NULL }, 303 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 304 }; 305 306 static struct drm_info_list gdp1_debugfs_files[] = { 307 { "gdp1", gdp_dbg_show, 0, NULL }, 308 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 309 }; 310 311 static struct drm_info_list gdp2_debugfs_files[] = { 312 { "gdp2", gdp_dbg_show, 0, NULL }, 313 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 314 }; 315 316 static struct drm_info_list gdp3_debugfs_files[] = { 317 { "gdp3", gdp_dbg_show, 0, NULL }, 318 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 319 }; 320 321 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 322 { 323 unsigned int i; 324 struct drm_info_list *gdp_debugfs_files; 325 int nb_files; 326 327 switch (gdp->plane.desc) { 328 case STI_GDP_0: 329 gdp_debugfs_files = gdp0_debugfs_files; 330 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 331 break; 332 case STI_GDP_1: 333 gdp_debugfs_files = gdp1_debugfs_files; 334 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 335 break; 336 case STI_GDP_2: 337 gdp_debugfs_files = gdp2_debugfs_files; 338 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 339 break; 340 case STI_GDP_3: 341 gdp_debugfs_files = gdp3_debugfs_files; 342 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 343 break; 344 default: 345 return -EINVAL; 346 } 347 348 for (i = 0; i < nb_files; i++) 349 gdp_debugfs_files[i].data = gdp; 350 351 return drm_debugfs_create_files(gdp_debugfs_files, 352 nb_files, 353 minor->debugfs_root, minor); 354 } 355 356 static int sti_gdp_fourcc2format(int fourcc) 357 { 358 switch (fourcc) { 359 case DRM_FORMAT_XRGB8888: 360 return GDP_RGB888_32; 361 case DRM_FORMAT_XBGR8888: 362 return GDP_XBGR8888; 363 case DRM_FORMAT_ARGB8888: 364 return GDP_ARGB8888; 365 case DRM_FORMAT_ABGR8888: 366 return GDP_ABGR8888; 367 case DRM_FORMAT_ARGB4444: 368 return GDP_ARGB4444; 369 case DRM_FORMAT_ARGB1555: 370 return GDP_ARGB1555; 371 case DRM_FORMAT_RGB565: 372 return GDP_RGB565; 373 case DRM_FORMAT_RGB888: 374 return GDP_RGB888; 375 } 376 return -1; 377 } 378 379 static int sti_gdp_get_alpharange(int format) 380 { 381 switch (format) { 382 case GDP_ARGB8565: 383 case GDP_ARGB8888: 384 case GDP_ABGR8888: 385 return GAM_GDP_ALPHARANGE_255; 386 } 387 return 0; 388 } 389 390 /** 391 * sti_gdp_get_free_nodes 392 * @gdp: gdp pointer 393 * 394 * Look for a GDP node list that is not currently read by the HW. 395 * 396 * RETURNS: 397 * Pointer to the free GDP node list 398 */ 399 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 400 { 401 int hw_nvn; 402 unsigned int i; 403 404 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 405 if (!hw_nvn) 406 goto end; 407 408 for (i = 0; i < GDP_NODE_NB_BANK; i++) 409 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 410 (hw_nvn != gdp->node_list[i].top_field_paddr)) 411 return &gdp->node_list[i]; 412 413 /* in hazardious cases restart with the first node */ 414 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 415 sti_plane_to_str(&gdp->plane), hw_nvn); 416 417 end: 418 return &gdp->node_list[0]; 419 } 420 421 /** 422 * sti_gdp_get_current_nodes 423 * @gdp: gdp pointer 424 * 425 * Look for GDP nodes that are currently read by the HW. 426 * 427 * RETURNS: 428 * Pointer to the current GDP node list 429 */ 430 static 431 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 432 { 433 int hw_nvn; 434 unsigned int i; 435 436 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 437 if (!hw_nvn) 438 goto end; 439 440 for (i = 0; i < GDP_NODE_NB_BANK; i++) 441 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 442 (hw_nvn == gdp->node_list[i].top_field_paddr)) 443 return &gdp->node_list[i]; 444 445 end: 446 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 447 hw_nvn, sti_plane_to_str(&gdp->plane)); 448 449 return NULL; 450 } 451 452 /** 453 * sti_gdp_disable 454 * @gdp: gdp pointer 455 * 456 * Disable a GDP. 457 */ 458 static void sti_gdp_disable(struct sti_gdp *gdp) 459 { 460 unsigned int i; 461 462 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 463 464 /* Set the nodes as 'to be ignored on mixer' */ 465 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 466 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 467 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 468 } 469 470 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 471 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 472 473 if (gdp->clk_pix) 474 clk_disable_unprepare(gdp->clk_pix); 475 476 gdp->plane.status = STI_PLANE_DISABLED; 477 } 478 479 /** 480 * sti_gdp_field_cb 481 * @nb: notifier block 482 * @event: event message 483 * @data: private data 484 * 485 * Handle VTG top field and bottom field event. 486 * 487 * RETURNS: 488 * 0 on success. 489 */ 490 int sti_gdp_field_cb(struct notifier_block *nb, 491 unsigned long event, void *data) 492 { 493 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 494 495 if (gdp->plane.status == STI_PLANE_FLUSHING) { 496 /* disable need to be synchronize on vsync event */ 497 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 498 sti_plane_to_str(&gdp->plane)); 499 500 sti_gdp_disable(gdp); 501 } 502 503 switch (event) { 504 case VTG_TOP_FIELD_EVENT: 505 gdp->is_curr_top = true; 506 break; 507 case VTG_BOTTOM_FIELD_EVENT: 508 gdp->is_curr_top = false; 509 break; 510 default: 511 DRM_ERROR("unsupported event: %lu\n", event); 512 break; 513 } 514 515 return 0; 516 } 517 518 static void sti_gdp_init(struct sti_gdp *gdp) 519 { 520 struct device_node *np = gdp->dev->of_node; 521 dma_addr_t dma_addr; 522 void *base; 523 unsigned int i, size; 524 525 /* Allocate all the nodes within a single memory page */ 526 size = sizeof(struct sti_gdp_node) * 527 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 528 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA); 529 530 if (!base) { 531 DRM_ERROR("Failed to allocate memory for GDP node\n"); 532 return; 533 } 534 memset(base, 0, size); 535 536 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 537 if (dma_addr & 0xF) { 538 DRM_ERROR("Mem alignment failed\n"); 539 return; 540 } 541 gdp->node_list[i].top_field = base; 542 gdp->node_list[i].top_field_paddr = dma_addr; 543 544 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 545 base += sizeof(struct sti_gdp_node); 546 dma_addr += sizeof(struct sti_gdp_node); 547 548 if (dma_addr & 0xF) { 549 DRM_ERROR("Mem alignment failed\n"); 550 return; 551 } 552 gdp->node_list[i].btm_field = base; 553 gdp->node_list[i].btm_field_paddr = dma_addr; 554 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 555 base += sizeof(struct sti_gdp_node); 556 dma_addr += sizeof(struct sti_gdp_node); 557 } 558 559 if (of_device_is_compatible(np, "st,stih407-compositor")) { 560 /* GDP of STiH407 chip have its own pixel clock */ 561 char *clk_name; 562 563 switch (gdp->plane.desc) { 564 case STI_GDP_0: 565 clk_name = "pix_gdp1"; 566 break; 567 case STI_GDP_1: 568 clk_name = "pix_gdp2"; 569 break; 570 case STI_GDP_2: 571 clk_name = "pix_gdp3"; 572 break; 573 case STI_GDP_3: 574 clk_name = "pix_gdp4"; 575 break; 576 default: 577 DRM_ERROR("GDP id not recognized\n"); 578 return; 579 } 580 581 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 582 if (IS_ERR(gdp->clk_pix)) 583 DRM_ERROR("Cannot get %s clock\n", clk_name); 584 585 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 586 if (IS_ERR(gdp->clk_main_parent)) 587 DRM_ERROR("Cannot get main_parent clock\n"); 588 589 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 590 if (IS_ERR(gdp->clk_aux_parent)) 591 DRM_ERROR("Cannot get aux_parent clock\n"); 592 } 593 } 594 595 /** 596 * sti_gdp_get_dst 597 * @dev: device 598 * @dst: requested destination size 599 * @src: source size 600 * 601 * Return the cropped / clamped destination size 602 * 603 * RETURNS: 604 * cropped / clamped destination size 605 */ 606 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 607 { 608 if (dst == src) 609 return dst; 610 611 if (dst < src) { 612 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 613 return dst; 614 } 615 616 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 617 return src; 618 } 619 620 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 621 struct drm_plane_state *state) 622 { 623 struct sti_plane *plane = to_sti_plane(drm_plane); 624 struct sti_gdp *gdp = to_sti_gdp(plane); 625 struct drm_crtc *crtc = state->crtc; 626 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 627 struct drm_framebuffer *fb = state->fb; 628 bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false; 629 struct drm_crtc_state *crtc_state; 630 struct sti_mixer *mixer; 631 struct drm_display_mode *mode; 632 int dst_x, dst_y, dst_w, dst_h; 633 int src_x, src_y, src_w, src_h; 634 int format; 635 636 /* no need for further checks if the plane is being disabled */ 637 if (!crtc || !fb) 638 return 0; 639 640 mixer = to_sti_mixer(crtc); 641 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 642 mode = &crtc_state->mode; 643 dst_x = state->crtc_x; 644 dst_y = state->crtc_y; 645 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 646 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 647 /* src_x are in 16.16 format */ 648 src_x = state->src_x >> 16; 649 src_y = state->src_y >> 16; 650 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); 651 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); 652 653 format = sti_gdp_fourcc2format(fb->pixel_format); 654 if (format == -1) { 655 DRM_ERROR("Format not supported by GDP %.4s\n", 656 (char *)&fb->pixel_format); 657 return -EINVAL; 658 } 659 660 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 661 DRM_ERROR("Can't get CMA GEM object for fb\n"); 662 return -EINVAL; 663 } 664 665 if (first_prepare) { 666 /* Register gdp callback */ 667 gdp->vtg = mixer->id == STI_MIXER_MAIN ? 668 compo->vtg_main : compo->vtg_aux; 669 if (sti_vtg_register_client(gdp->vtg, 670 &gdp->vtg_field_nb, crtc)) { 671 DRM_ERROR("Cannot register VTG notifier\n"); 672 return -EINVAL; 673 } 674 675 /* Set and enable gdp clock */ 676 if (gdp->clk_pix) { 677 struct clk *clkp; 678 int rate = mode->clock * 1000; 679 int res; 680 681 /* 682 * According to the mixer used, the gdp pixel clock 683 * should have a different parent clock. 684 */ 685 if (mixer->id == STI_MIXER_MAIN) 686 clkp = gdp->clk_main_parent; 687 else 688 clkp = gdp->clk_aux_parent; 689 690 if (clkp) 691 clk_set_parent(gdp->clk_pix, clkp); 692 693 res = clk_set_rate(gdp->clk_pix, rate); 694 if (res < 0) { 695 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 696 rate); 697 return -EINVAL; 698 } 699 700 if (clk_prepare_enable(gdp->clk_pix)) { 701 DRM_ERROR("Failed to prepare/enable gdp\n"); 702 return -EINVAL; 703 } 704 } 705 } 706 707 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 708 crtc->base.id, sti_mixer_to_str(mixer), 709 drm_plane->base.id, sti_plane_to_str(plane)); 710 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 711 sti_plane_to_str(plane), 712 dst_w, dst_h, dst_x, dst_y, 713 src_w, src_h, src_x, src_y); 714 715 return 0; 716 } 717 718 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 719 struct drm_plane_state *oldstate) 720 { 721 struct drm_plane_state *state = drm_plane->state; 722 struct sti_plane *plane = to_sti_plane(drm_plane); 723 struct sti_gdp *gdp = to_sti_gdp(plane); 724 struct drm_crtc *crtc = state->crtc; 725 struct drm_framebuffer *fb = state->fb; 726 struct drm_display_mode *mode; 727 int dst_x, dst_y, dst_w, dst_h; 728 int src_x, src_y, src_w, src_h; 729 struct drm_gem_cma_object *cma_obj; 730 struct sti_gdp_node_list *list; 731 struct sti_gdp_node_list *curr_list; 732 struct sti_gdp_node *top_field, *btm_field; 733 u32 dma_updated_top; 734 u32 dma_updated_btm; 735 int format; 736 unsigned int depth, bpp; 737 u32 ydo, xdo, yds, xds; 738 739 if (!crtc || !fb) 740 return; 741 742 mode = &crtc->mode; 743 dst_x = state->crtc_x; 744 dst_y = state->crtc_y; 745 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 746 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 747 /* src_x are in 16.16 format */ 748 src_x = state->src_x >> 16; 749 src_y = state->src_y >> 16; 750 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); 751 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); 752 753 list = sti_gdp_get_free_nodes(gdp); 754 top_field = list->top_field; 755 btm_field = list->btm_field; 756 757 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 758 sti_plane_to_str(plane), top_field, btm_field); 759 760 /* build the top field */ 761 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 762 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 763 format = sti_gdp_fourcc2format(fb->pixel_format); 764 top_field->gam_gdp_ctl |= format; 765 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 766 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 767 768 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 769 770 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 771 (char *)&fb->pixel_format, 772 (unsigned long)cma_obj->paddr); 773 774 /* pixel memory location */ 775 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 776 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 777 top_field->gam_gdp_pml += src_x * (bpp >> 3); 778 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 779 780 /* output parameters (clamped / cropped) */ 781 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 782 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 783 ydo = sti_vtg_get_line_number(*mode, dst_y); 784 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 785 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 786 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 787 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 788 top_field->gam_gdp_vps = (yds << 16) | xds; 789 790 /* input parameters */ 791 src_w = dst_w; 792 top_field->gam_gdp_pmp = fb->pitches[0]; 793 top_field->gam_gdp_size = src_h << 16 | src_w; 794 795 /* Same content and chained together */ 796 memcpy(btm_field, top_field, sizeof(*btm_field)); 797 top_field->gam_gdp_nvn = list->btm_field_paddr; 798 btm_field->gam_gdp_nvn = list->top_field_paddr; 799 800 /* Interlaced mode */ 801 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 802 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 803 fb->pitches[0]; 804 805 /* Update the NVN field of the 'right' field of the current GDP node 806 * (being used by the HW) with the address of the updated ('free') top 807 * field GDP node. 808 * - In interlaced mode the 'right' field is the bottom field as we 809 * update frames starting from their top field 810 * - In progressive mode, we update both bottom and top fields which 811 * are equal nodes. 812 * At the next VSYNC, the updated node list will be used by the HW. 813 */ 814 curr_list = sti_gdp_get_current_nodes(gdp); 815 dma_updated_top = list->top_field_paddr; 816 dma_updated_btm = list->btm_field_paddr; 817 818 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 819 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 820 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 821 (unsigned long)cma_obj->paddr, 822 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 823 824 if (!curr_list) { 825 /* First update or invalid node should directly write in the 826 * hw register */ 827 DRM_DEBUG_DRIVER("%s first update (or invalid node)", 828 sti_plane_to_str(plane)); 829 830 writel(gdp->is_curr_top ? 831 dma_updated_btm : dma_updated_top, 832 gdp->regs + GAM_GDP_NVN_OFFSET); 833 goto end; 834 } 835 836 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 837 if (gdp->is_curr_top) { 838 /* Do not update in the middle of the frame, but 839 * postpone the update after the bottom field has 840 * been displayed */ 841 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 842 } else { 843 /* Direct update to avoid one frame delay */ 844 writel(dma_updated_top, 845 gdp->regs + GAM_GDP_NVN_OFFSET); 846 } 847 } else { 848 /* Direct update for progressive to avoid one frame delay */ 849 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 850 } 851 852 end: 853 sti_plane_update_fps(plane, true, false); 854 855 plane->status = STI_PLANE_UPDATED; 856 } 857 858 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 859 struct drm_plane_state *oldstate) 860 { 861 struct sti_plane *plane = to_sti_plane(drm_plane); 862 863 if (!drm_plane->crtc) { 864 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 865 drm_plane->base.id); 866 return; 867 } 868 869 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 870 drm_plane->crtc->base.id, 871 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), 872 drm_plane->base.id, sti_plane_to_str(plane)); 873 874 plane->status = STI_PLANE_DISABLING; 875 } 876 877 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 878 .atomic_check = sti_gdp_atomic_check, 879 .atomic_update = sti_gdp_atomic_update, 880 .atomic_disable = sti_gdp_atomic_disable, 881 }; 882 883 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 884 struct device *dev, int desc, 885 void __iomem *baseaddr, 886 unsigned int possible_crtcs, 887 enum drm_plane_type type) 888 { 889 struct sti_gdp *gdp; 890 int res; 891 892 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 893 if (!gdp) { 894 DRM_ERROR("Failed to allocate memory for GDP\n"); 895 return NULL; 896 } 897 898 gdp->dev = dev; 899 gdp->regs = baseaddr; 900 gdp->plane.desc = desc; 901 gdp->plane.status = STI_PLANE_DISABLED; 902 903 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 904 905 sti_gdp_init(gdp); 906 907 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 908 possible_crtcs, 909 &sti_plane_helpers_funcs, 910 gdp_supported_formats, 911 ARRAY_SIZE(gdp_supported_formats), 912 type, NULL); 913 if (res) { 914 DRM_ERROR("Failed to initialize universal plane\n"); 915 goto err; 916 } 917 918 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 919 920 sti_plane_init_property(&gdp->plane, type); 921 922 if (gdp_debugfs_init(gdp, drm_dev->primary)) 923 DRM_ERROR("GDP debugfs setup failed\n"); 924 925 return &gdp->plane.drm_plane; 926 927 err: 928 devm_kfree(dev, gdp); 929 return NULL; 930 } 931