1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DRM driver for Solomon SSD13xx OLED displays 4 * 5 * Copyright 2022 Red Hat Inc. 6 * Author: Javier Martinez Canillas <javierm@redhat.com> 7 * 8 * Based on drivers/video/fbdev/ssd1307fb.c 9 * Copyright 2012 Free Electrons 10 */ 11 12 #include <linux/backlight.h> 13 #include <linux/bitfield.h> 14 #include <linux/bits.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/property.h> 18 #include <linux/pwm.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <drm/clients/drm_client_setup.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_damage_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fbdev_shmem.h> 28 #include <drm/drm_format_helper.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_gem_atomic_helper.h> 31 #include <drm/drm_gem_framebuffer_helper.h> 32 #include <drm/drm_gem_shmem_helper.h> 33 #include <drm/drm_managed.h> 34 #include <drm/drm_modes.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "ssd130x.h" 40 41 #define DRIVER_NAME "ssd130x" 42 #define DRIVER_DESC "DRM driver for Solomon SSD13xx OLED displays" 43 #define DRIVER_MAJOR 1 44 #define DRIVER_MINOR 0 45 46 #define SSD130X_PAGE_HEIGHT 8 47 48 #define SSD132X_SEGMENT_WIDTH 2 49 50 /* ssd13xx commands */ 51 #define SSD13XX_CONTRAST 0x81 52 #define SSD13XX_SET_SEG_REMAP 0xa0 53 #define SSD13XX_SET_MULTIPLEX_RATIO 0xa8 54 #define SSD13XX_DISPLAY_OFF 0xae 55 #define SSD13XX_DISPLAY_ON 0xaf 56 57 #define SSD13XX_SET_SEG_REMAP_MASK GENMASK(0, 0) 58 #define SSD13XX_SET_SEG_REMAP_SET(val) FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val)) 59 60 /* ssd130x commands */ 61 #define SSD130X_PAGE_COL_START_LOW 0x00 62 #define SSD130X_PAGE_COL_START_HIGH 0x10 63 #define SSD130X_SET_ADDRESS_MODE 0x20 64 #define SSD130X_SET_COL_RANGE 0x21 65 #define SSD130X_SET_PAGE_RANGE 0x22 66 #define SSD130X_SET_LOOKUP_TABLE 0x91 67 #define SSD130X_CHARGE_PUMP 0x8d 68 #define SSD130X_START_PAGE_ADDRESS 0xb0 69 #define SSD130X_SET_COM_SCAN_DIR 0xc0 70 #define SSD130X_SET_DISPLAY_OFFSET 0xd3 71 #define SSD130X_SET_CLOCK_FREQ 0xd5 72 #define SSD130X_SET_AREA_COLOR_MODE 0xd8 73 #define SSD130X_SET_PRECHARGE_PERIOD 0xd9 74 #define SSD130X_SET_COM_PINS_CONFIG 0xda 75 #define SSD130X_SET_VCOMH 0xdb 76 77 /* ssd130x commands accessors */ 78 #define SSD130X_PAGE_COL_START_MASK GENMASK(3, 0) 79 #define SSD130X_PAGE_COL_START_HIGH_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4) 80 #define SSD130X_PAGE_COL_START_LOW_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val)) 81 #define SSD130X_START_PAGE_ADDRESS_MASK GENMASK(2, 0) 82 #define SSD130X_START_PAGE_ADDRESS_SET(val) FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val)) 83 #define SSD130X_SET_COM_SCAN_DIR_MASK GENMASK(3, 3) 84 #define SSD130X_SET_COM_SCAN_DIR_SET(val) FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val)) 85 #define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0) 86 #define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val)) 87 #define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4) 88 #define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val)) 89 #define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0) 90 #define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val)) 91 #define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4) 92 #define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val)) 93 #define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4) 94 #define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val)) 95 #define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5) 96 #define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val)) 97 98 #define SSD130X_SET_ADDRESS_MODE_HORIZONTAL 0x00 99 #define SSD130X_SET_ADDRESS_MODE_VERTICAL 0x01 100 #define SSD130X_SET_ADDRESS_MODE_PAGE 0x02 101 102 #define SSD130X_SET_AREA_COLOR_MODE_ENABLE 0x1e 103 #define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER 0x05 104 105 /* ssd132x commands */ 106 #define SSD132X_SET_COL_RANGE 0x15 107 #define SSD132X_SET_DEACTIVATE_SCROLL 0x2e 108 #define SSD132X_SET_ROW_RANGE 0x75 109 #define SSD132X_SET_DISPLAY_START 0xa1 110 #define SSD132X_SET_DISPLAY_OFFSET 0xa2 111 #define SSD132X_SET_DISPLAY_NORMAL 0xa4 112 #define SSD132X_SET_FUNCTION_SELECT_A 0xab 113 #define SSD132X_SET_PHASE_LENGTH 0xb1 114 #define SSD132X_SET_CLOCK_FREQ 0xb3 115 #define SSD132X_SET_GPIO 0xb5 116 #define SSD132X_SET_PRECHARGE_PERIOD 0xb6 117 #define SSD132X_SET_GRAY_SCALE_TABLE 0xb8 118 #define SSD132X_SELECT_DEFAULT_TABLE 0xb9 119 #define SSD132X_SET_PRECHARGE_VOLTAGE 0xbc 120 #define SSD130X_SET_VCOMH_VOLTAGE 0xbe 121 #define SSD132X_SET_FUNCTION_SELECT_B 0xd5 122 123 /* ssd133x commands */ 124 #define SSD133X_SET_COL_RANGE 0x15 125 #define SSD133X_SET_ROW_RANGE 0x75 126 #define SSD133X_CONTRAST_A 0x81 127 #define SSD133X_CONTRAST_B 0x82 128 #define SSD133X_CONTRAST_C 0x83 129 #define SSD133X_SET_MASTER_CURRENT 0x87 130 #define SSD132X_SET_PRECHARGE_A 0x8a 131 #define SSD132X_SET_PRECHARGE_B 0x8b 132 #define SSD132X_SET_PRECHARGE_C 0x8c 133 #define SSD133X_SET_DISPLAY_START 0xa1 134 #define SSD133X_SET_DISPLAY_OFFSET 0xa2 135 #define SSD133X_SET_DISPLAY_NORMAL 0xa4 136 #define SSD133X_SET_MASTER_CONFIG 0xad 137 #define SSD133X_POWER_SAVE_MODE 0xb0 138 #define SSD133X_PHASES_PERIOD 0xb1 139 #define SSD133X_SET_CLOCK_FREQ 0xb3 140 #define SSD133X_SET_PRECHARGE_VOLTAGE 0xbb 141 #define SSD133X_SET_VCOMH_VOLTAGE 0xbe 142 143 #define MAX_CONTRAST 255 144 145 const struct ssd130x_deviceinfo ssd130x_variants[] = { 146 [SH1106_ID] = { 147 .default_vcomh = 0x40, 148 .default_dclk_div = 1, 149 .default_dclk_frq = 5, 150 .default_width = 132, 151 .default_height = 64, 152 .page_mode_only = 1, 153 .family_id = SSD130X_FAMILY, 154 }, 155 [SSD1305_ID] = { 156 .default_vcomh = 0x34, 157 .default_dclk_div = 1, 158 .default_dclk_frq = 7, 159 .default_width = 132, 160 .default_height = 64, 161 .family_id = SSD130X_FAMILY, 162 }, 163 [SSD1306_ID] = { 164 .default_vcomh = 0x20, 165 .default_dclk_div = 1, 166 .default_dclk_frq = 8, 167 .need_chargepump = 1, 168 .default_width = 128, 169 .default_height = 64, 170 .family_id = SSD130X_FAMILY, 171 }, 172 [SSD1307_ID] = { 173 .default_vcomh = 0x20, 174 .default_dclk_div = 2, 175 .default_dclk_frq = 12, 176 .need_pwm = 1, 177 .default_width = 128, 178 .default_height = 39, 179 .family_id = SSD130X_FAMILY, 180 }, 181 [SSD1309_ID] = { 182 .default_vcomh = 0x34, 183 .default_dclk_div = 1, 184 .default_dclk_frq = 10, 185 .default_width = 128, 186 .default_height = 64, 187 .family_id = SSD130X_FAMILY, 188 }, 189 /* ssd132x family */ 190 [SSD1322_ID] = { 191 .default_width = 480, 192 .default_height = 128, 193 .family_id = SSD132X_FAMILY, 194 }, 195 [SSD1325_ID] = { 196 .default_width = 128, 197 .default_height = 80, 198 .family_id = SSD132X_FAMILY, 199 }, 200 [SSD1327_ID] = { 201 .default_width = 128, 202 .default_height = 128, 203 .family_id = SSD132X_FAMILY, 204 }, 205 /* ssd133x family */ 206 [SSD1331_ID] = { 207 .default_width = 96, 208 .default_height = 64, 209 .family_id = SSD133X_FAMILY, 210 } 211 }; 212 EXPORT_SYMBOL_NS_GPL(ssd130x_variants, "DRM_SSD130X"); 213 214 struct ssd130x_crtc_state { 215 struct drm_crtc_state base; 216 /* Buffer to store pixels in HW format and written to the panel */ 217 u8 *data_array; 218 }; 219 220 struct ssd130x_plane_state { 221 struct drm_shadow_plane_state base; 222 /* Intermediate buffer to convert pixels from XRGB8888 to HW format */ 223 u8 *buffer; 224 }; 225 226 static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state) 227 { 228 return container_of(state, struct ssd130x_crtc_state, base); 229 } 230 231 static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state) 232 { 233 return container_of(state, struct ssd130x_plane_state, base.base); 234 } 235 236 static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm) 237 { 238 return container_of(drm, struct ssd130x_device, drm); 239 } 240 241 /* 242 * Helper to write data (SSD13XX_DATA) to the device. 243 */ 244 static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count) 245 { 246 return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count); 247 } 248 249 /* 250 * Helper to write command (SSD13XX_COMMAND). The fist variadic argument 251 * is the command to write and the following are the command options. 252 * 253 * Note that the ssd13xx protocol requires each command and option to be 254 * written as a SSD13XX_COMMAND device register value. That is why a call 255 * to regmap_write(..., SSD13XX_COMMAND, ...) is done for each argument. 256 */ 257 static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count, 258 /* u8 cmd, u8 option, ... */...) 259 { 260 va_list ap; 261 u8 value; 262 int ret; 263 264 va_start(ap, count); 265 266 do { 267 value = va_arg(ap, int); 268 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, value); 269 if (ret) 270 goto out_end; 271 } while (--count); 272 273 out_end: 274 va_end(ap); 275 276 return ret; 277 } 278 279 /* 280 * Write a command byte sequence from a buffer. 281 * 282 * Like ssd130x_write_cmd() but takes a pre-built byte array instead of 283 * variadic arguments, handy when the command is already in an array or 284 * when the caller wants to use sizeof() for the length. 285 */ 286 static int ssd130x_write_cmds(struct ssd130x_device *ssd130x, const u8 *cmd, 287 size_t len) 288 { 289 unsigned int i; 290 int ret; 291 292 for (i = 0; i < len; i++) { 293 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, cmd[i]); 294 if (ret) 295 return ret; 296 } 297 298 return 0; 299 } 300 301 /* 302 * Run a packed command sequence. The format is a flat byte array where each 303 * entry starts with a length byte followed by that many command bytes. A 304 * zero length byte terminates the sequence. 305 * 306 * Example: { 2, 0x81, 0x80, 1, 0xAF, 0 } 307 * sends command {0x81, 0x80}, then command {0xAF}, then stops. 308 */ 309 static int ssd130x_run_cmd_seq(struct ssd130x_device *ssd130x, const u8 *seq) 310 { 311 while (*seq) { 312 u8 len = *seq++; 313 int ret = ssd130x_write_cmds(ssd130x, seq, len); 314 315 if (ret) 316 return ret; 317 seq += len; 318 } 319 320 return 0; 321 } 322 /* Set address range for horizontal/vertical addressing modes */ 323 static int ssd130x_set_col_range(struct ssd130x_device *ssd130x, 324 u8 col_start, u8 cols) 325 { 326 u8 col_end = col_start + cols - 1; 327 int ret; 328 329 if (col_start == ssd130x->col_start && col_end == ssd130x->col_end) 330 return 0; 331 332 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_COL_RANGE, col_start, col_end); 333 if (ret < 0) 334 return ret; 335 336 ssd130x->col_start = col_start; 337 ssd130x->col_end = col_end; 338 return 0; 339 } 340 341 static int ssd130x_set_page_range(struct ssd130x_device *ssd130x, 342 u8 page_start, u8 pages) 343 { 344 u8 page_end = page_start + pages - 1; 345 int ret; 346 347 if (page_start == ssd130x->page_start && page_end == ssd130x->page_end) 348 return 0; 349 350 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_PAGE_RANGE, page_start, page_end); 351 if (ret < 0) 352 return ret; 353 354 ssd130x->page_start = page_start; 355 ssd130x->page_end = page_end; 356 return 0; 357 } 358 359 /* Set page and column start address for page addressing mode */ 360 static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x, 361 u8 page_start, u8 col_start) 362 { 363 int ret; 364 u32 page, col_low, col_high; 365 366 page = SSD130X_START_PAGE_ADDRESS | 367 SSD130X_START_PAGE_ADDRESS_SET(page_start); 368 col_low = SSD130X_PAGE_COL_START_LOW | 369 SSD130X_PAGE_COL_START_LOW_SET(col_start); 370 col_high = SSD130X_PAGE_COL_START_HIGH | 371 SSD130X_PAGE_COL_START_HIGH_SET(col_start); 372 ret = ssd130x_write_cmd(ssd130x, 3, page, col_low, col_high); 373 if (ret < 0) 374 return ret; 375 376 return 0; 377 } 378 379 static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x) 380 { 381 struct device *dev = ssd130x->dev; 382 struct pwm_state pwmstate; 383 384 ssd130x->pwm = pwm_get(dev, NULL); 385 if (IS_ERR(ssd130x->pwm)) { 386 dev_err(dev, "Could not get PWM from firmware description!\n"); 387 return PTR_ERR(ssd130x->pwm); 388 } 389 390 pwm_init_state(ssd130x->pwm, &pwmstate); 391 pwm_set_relative_duty_cycle(&pwmstate, 50, 100); 392 pwm_apply_might_sleep(ssd130x->pwm, &pwmstate); 393 394 /* Enable the PWM */ 395 pwm_enable(ssd130x->pwm); 396 397 dev_dbg(dev, "Using PWM %s with a %lluns period.\n", 398 ssd130x->pwm->label, pwm_get_period(ssd130x->pwm)); 399 400 return 0; 401 } 402 403 static void ssd130x_reset(struct ssd130x_device *ssd130x) 404 { 405 if (!ssd130x->reset) 406 return; 407 408 /* Reset the screen */ 409 gpiod_set_value_cansleep(ssd130x->reset, 1); 410 udelay(4); 411 gpiod_set_value_cansleep(ssd130x->reset, 0); 412 udelay(4); 413 } 414 415 static int ssd130x_power_on(struct ssd130x_device *ssd130x) 416 { 417 struct device *dev = ssd130x->dev; 418 int ret; 419 420 ssd130x_reset(ssd130x); 421 422 ret = regulator_enable(ssd130x->vcc_reg); 423 if (ret) { 424 dev_err(dev, "Failed to enable VCC: %d\n", ret); 425 return ret; 426 } 427 428 if (ssd130x->device_info->need_pwm) { 429 ret = ssd130x_pwm_enable(ssd130x); 430 if (ret) { 431 dev_err(dev, "Failed to enable PWM: %d\n", ret); 432 regulator_disable(ssd130x->vcc_reg); 433 return ret; 434 } 435 } 436 437 return 0; 438 } 439 440 static void ssd130x_power_off(struct ssd130x_device *ssd130x) 441 { 442 pwm_disable(ssd130x->pwm); 443 pwm_put(ssd130x->pwm); 444 445 regulator_disable(ssd130x->vcc_reg); 446 } 447 448 static int ssd130x_init(struct ssd130x_device *ssd130x) 449 { 450 u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap; 451 bool scan_mode; 452 int ret; 453 454 /* Set segment re-map */ 455 seg_remap = (SSD13XX_SET_SEG_REMAP | 456 SSD13XX_SET_SEG_REMAP_SET(ssd130x->seg_remap)); 457 /* Set COM direction */ 458 com_invdir = (SSD130X_SET_COM_SCAN_DIR | 459 SSD130X_SET_COM_SCAN_DIR_SET(ssd130x->com_invdir)); 460 /* Set clock frequency */ 461 dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) | 462 SSD130X_SET_CLOCK_FREQ_SET(ssd130x->dclk_frq)); 463 464 const u8 *cmds = (const u8[]) { 465 2, SSD13XX_CONTRAST, ssd130x->contrast, 466 1, seg_remap, 467 1, com_invdir, 0, 468 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 469 2, SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset, 470 2, SSD130X_SET_CLOCK_FREQ, dclk, 471 0, 472 }; 473 ret = ssd130x_run_cmd_seq(ssd130x, cmds); 474 if (ret < 0) 475 return ret; 476 477 /* Set Area Color Mode ON/OFF & Low Power Display Mode */ 478 if (ssd130x->area_color_enable || ssd130x->low_power) { 479 u32 mode = 0; 480 481 if (ssd130x->area_color_enable) 482 mode |= SSD130X_SET_AREA_COLOR_MODE_ENABLE; 483 484 if (ssd130x->low_power) 485 mode |= SSD130X_SET_AREA_COLOR_MODE_LOW_POWER; 486 487 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_AREA_COLOR_MODE, mode); 488 if (ret < 0) 489 return ret; 490 } 491 492 /* Set precharge period in number of ticks from the internal clock */ 493 precharge = (SSD130X_SET_PRECHARGE_PERIOD1_SET(ssd130x->prechargep1) | 494 SSD130X_SET_PRECHARGE_PERIOD2_SET(ssd130x->prechargep2)); 495 496 /* Set COM pins configuration */ 497 compins = BIT(1); 498 /* 499 * The COM scan mode field values are the inverse of the boolean DT 500 * property "solomon,com-seq". The value 0b means scan from COM0 to 501 * COM[N - 1] while 1b means scan from COM[N - 1] to COM0. 502 */ 503 scan_mode = !ssd130x->com_seq; 504 compins |= (SSD130X_SET_COM_PINS_CONFIG1_SET(scan_mode) | 505 SSD130X_SET_COM_PINS_CONFIG2_SET(ssd130x->com_lrremap)); 506 507 /* Turn on the DC-DC Charge Pump */ 508 chargepump = BIT(4); 509 if (ssd130x->device_info->need_chargepump) 510 chargepump |= BIT(2); 511 512 cmds = (const u8[]) { 513 2, SSD130X_SET_PRECHARGE_PERIOD, precharge, 514 2, SSD130X_SET_COM_PINS_CONFIG, compins, 515 2, SSD130X_SET_VCOMH, ssd130x->vcomh, 516 2, SSD130X_CHARGE_PUMP, chargepump, 517 0 518 }; 519 ret = ssd130x_run_cmd_seq(ssd130x, cmds); 520 if (ret < 0) 521 return ret; 522 523 /* Set lookup table */ 524 if (ssd130x->lookup_table_set) { 525 int i; 526 527 ret = ssd130x_write_cmd(ssd130x, 1, SSD130X_SET_LOOKUP_TABLE); 528 if (ret < 0) 529 return ret; 530 531 for (i = 0; i < ARRAY_SIZE(ssd130x->lookup_table); i++) { 532 u8 val = ssd130x->lookup_table[i]; 533 534 if (val < 31 || val > 63) 535 dev_warn(ssd130x->dev, 536 "lookup table index %d value out of range 31 <= %d <= 63\n", 537 i, val); 538 ret = ssd130x_write_cmd(ssd130x, 1, val); 539 if (ret < 0) 540 return ret; 541 } 542 } 543 544 /* Switch to page addressing mode */ 545 if (ssd130x->page_address_mode) 546 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 547 SSD130X_SET_ADDRESS_MODE_PAGE); 548 549 /* Switch to horizontal addressing mode */ 550 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 551 SSD130X_SET_ADDRESS_MODE_HORIZONTAL); 552 } 553 554 static int ssd132x_init(struct ssd130x_device *ssd130x) 555 { 556 const u8 cmds[] = { 557 2, SSD13XX_CONTRAST, 0x80, 558 3, SSD132X_SET_COL_RANGE, 0x00, ssd130x->width / SSD132X_SEGMENT_WIDTH - 1, 559 3, SSD132X_SET_ROW_RANGE, 0x00, ssd130x->height - 1, 560 /* 561 * Horizontal Address Increment 562 * Re-map for Column Address, Nibble and COM 563 * COM Split Odd Even 564 */ 565 2, SSD13XX_SET_SEG_REMAP, 0x53, 566 2, SSD132X_SET_DISPLAY_START, 0x00, 567 2, SSD132X_SET_DISPLAY_OFFSET, 0x00, 568 1, SSD132X_SET_DISPLAY_NORMAL, 569 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 570 2, SSD132X_SET_PHASE_LENGTH, 0x55, 571 1, SSD132X_SELECT_DEFAULT_TABLE, 572 2, SSD132X_SET_CLOCK_FREQ, 0x01, 573 2, SSD132X_SET_FUNCTION_SELECT_A, 0x1, 574 2, SSD132X_SET_PRECHARGE_PERIOD, 0x01, 575 2, SSD132X_SET_PRECHARGE_VOLTAGE, 0x08, 576 2, SSD130X_SET_VCOMH_VOLTAGE, 0x07, 577 /* Enable second pre-charge and internal VSL */ 578 2, SSD132X_SET_FUNCTION_SELECT_B, 0x62, 579 0, 580 }; 581 582 return ssd130x_run_cmd_seq(ssd130x, cmds); 583 } 584 585 static int ssd133x_init(struct ssd130x_device *ssd130x) 586 { 587 const u8 cmds[] = { 588 2, SSD133X_CONTRAST_A, 0x91, 589 2, SSD133X_CONTRAST_B, 0x50, 590 2, SSD133X_CONTRAST_C, 0x7d, 591 2, SSD133X_SET_MASTER_CURRENT, 0x06, 592 3, SSD133X_SET_COL_RANGE, 0x00, ssd130x->width - 1, 593 3, SSD133X_SET_ROW_RANGE, 0x00, ssd130x->height - 1, 594 /* 595 * Horizontal Address Increment 596 * Normal order SA,SB,SC (e.g. RGB) 597 * COM Split Odd Even 598 * 256 color format 599 */ 600 2, SSD13XX_SET_SEG_REMAP, 0x20, 601 2, SSD133X_SET_DISPLAY_START, 0x00, 602 2, SSD133X_SET_DISPLAY_OFFSET, 0x00, 603 1, SSD133X_SET_DISPLAY_NORMAL, 604 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 605 2, SSD133X_SET_MASTER_CONFIG, 0x8e, 606 2, SSD133X_POWER_SAVE_MODE, 0x0b, 607 2, SSD133X_PHASES_PERIOD, 0x31, 608 2, SSD133X_SET_CLOCK_FREQ, 0xf0, 609 2, SSD132X_SET_PRECHARGE_A, 0x64, 610 2, SSD132X_SET_PRECHARGE_B, 0x78, 611 2, SSD132X_SET_PRECHARGE_C, 0x64, 612 2, SSD133X_SET_PRECHARGE_VOLTAGE, 0x3a, 613 2, SSD133X_SET_VCOMH_VOLTAGE, 0x3e, 614 0, 615 }; 616 617 return ssd130x_run_cmd_seq(ssd130x, cmds); 618 } 619 620 static int ssd130x_update_rect(struct ssd130x_device *ssd130x, 621 struct drm_rect *rect, u8 *buf, 622 u8 *data_array) 623 { 624 unsigned int x = rect->x1; 625 unsigned int y = rect->y1; 626 unsigned int width = drm_rect_width(rect); 627 unsigned int height = drm_rect_height(rect); 628 unsigned int line_length = DIV_ROUND_UP(width, 8); 629 unsigned int page_height = SSD130X_PAGE_HEIGHT; 630 u8 page_start = ssd130x->page_offset + y / page_height; 631 unsigned int pages = DIV_ROUND_UP(height, page_height); 632 struct drm_device *drm = &ssd130x->drm; 633 u32 array_idx = 0; 634 int ret, i, j, k; 635 636 drm_WARN_ONCE(drm, y % page_height != 0, "y must be aligned to screen page\n"); 637 638 /* 639 * The screen is divided in pages, each having a height of 8 640 * pixels, and the width of the screen. When sending a byte of 641 * data to the controller, it gives the 8 bits for the current 642 * column. I.e, the first byte are the 8 bits of the first 643 * column, then the 8 bits for the second column, etc. 644 * 645 * 646 * Representation of the screen, assuming it is 5 bits 647 * wide. Each letter-number combination is a bit that controls 648 * one pixel. 649 * 650 * A0 A1 A2 A3 A4 651 * B0 B1 B2 B3 B4 652 * C0 C1 C2 C3 C4 653 * D0 D1 D2 D3 D4 654 * E0 E1 E2 E3 E4 655 * F0 F1 F2 F3 F4 656 * G0 G1 G2 G3 G4 657 * H0 H1 H2 H3 H4 658 * 659 * If you want to update this screen, you need to send 5 bytes: 660 * (1) A0 B0 C0 D0 E0 F0 G0 H0 661 * (2) A1 B1 C1 D1 E1 F1 G1 H1 662 * (3) A2 B2 C2 D2 E2 F2 G2 H2 663 * (4) A3 B3 C3 D3 E3 F3 G3 H3 664 * (5) A4 B4 C4 D4 E4 F4 G4 H4 665 */ 666 667 if (!ssd130x->page_address_mode) { 668 /* Set address range for horizontal addressing mode */ 669 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width); 670 if (ret < 0) 671 return ret; 672 673 ret = ssd130x_set_page_range(ssd130x, page_start, pages); 674 if (ret < 0) 675 return ret; 676 } 677 678 for (i = 0; i < pages; i++) { 679 int m = page_height; 680 681 /* Last page may be partial */ 682 if (page_height * (y / page_height + i + 1) > ssd130x->height) 683 m = ssd130x->height % page_height; 684 685 for (j = 0; j < width; j++) { 686 u8 data = 0; 687 688 for (k = 0; k < m; k++) { 689 u32 idx = (page_height * i + k) * line_length + j / 8; 690 u8 byte = buf[idx]; 691 u8 bit = (byte >> (j % 8)) & 1; 692 693 data |= bit << k; 694 } 695 data_array[array_idx++] = data; 696 } 697 698 /* 699 * In page addressing mode, the start address needs to be reset, 700 * and each page then needs to be written out separately. 701 */ 702 if (ssd130x->page_address_mode) { 703 ret = ssd130x_set_page_pos(ssd130x, 704 page_start + i, 705 ssd130x->col_offset + x); 706 if (ret < 0) 707 return ret; 708 709 ret = ssd130x_write_data(ssd130x, data_array, width); 710 if (ret < 0) 711 return ret; 712 713 array_idx = 0; 714 } 715 } 716 717 /* Write out update in one go if we aren't using page addressing mode */ 718 if (!ssd130x->page_address_mode) 719 ret = ssd130x_write_data(ssd130x, data_array, width * pages); 720 721 return ret; 722 } 723 724 static int ssd132x_update_rect(struct ssd130x_device *ssd130x, 725 struct drm_rect *rect, u8 *buf, 726 u8 *data_array) 727 { 728 unsigned int segment_width = SSD132X_SEGMENT_WIDTH; 729 unsigned int col = rect->x1 / segment_width; 730 unsigned int row = rect->y1; 731 unsigned int width = drm_rect_width(rect); 732 unsigned int height = drm_rect_height(rect); 733 unsigned int columns = DIV_ROUND_UP(width, segment_width); 734 unsigned int rows = height; 735 struct drm_device *drm = &ssd130x->drm; 736 u32 array_idx = 0; 737 unsigned int i, j; 738 int ret; 739 740 drm_WARN_ONCE(drm, rect->x1 % segment_width != 0, "x must be aligned to screen segment\n"); 741 742 /* 743 * The screen is divided in Segment and Common outputs, where 744 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 745 * the columns. 746 * 747 * Each Segment has a 4-bit pixel and each Common output has a 748 * row of pixels. When using the (default) horizontal address 749 * increment mode, each byte of data sent to the controller has 750 * two Segments (e.g: SEG0 and SEG1) that are stored in the lower 751 * and higher nibbles of a single byte representing one column. 752 * That is, the first byte are SEG0 (D0[3:0]) and SEG1 (D0[7:4]), 753 * the second byte are SEG2 (D1[3:0]) and SEG3 (D1[7:4]) and so on. 754 */ 755 756 /* Set column start and end */ 757 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, col, col + columns - 1); 758 if (ret < 0) 759 return ret; 760 761 /* Set row start and end */ 762 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, row, row + rows - 1); 763 if (ret < 0) 764 return ret; 765 766 for (i = 0; i < height; i++) { 767 /* Process pair of pixels and combine them into a single byte */ 768 for (j = 0; j < width; j += segment_width) { 769 u8 n1 = buf[i * width + j]; 770 u8 n2 = buf[i * width + j + 1]; 771 772 data_array[array_idx++] = (n2 & 0xf0) | (n1 >> 4); 773 } 774 } 775 776 /* Write out update in one go since horizontal addressing mode is used */ 777 ret = ssd130x_write_data(ssd130x, data_array, columns * rows); 778 779 return ret; 780 } 781 782 static int ssd133x_update_rect(struct ssd130x_device *ssd130x, 783 struct drm_rect *rect, u8 *data_array, 784 unsigned int pitch) 785 { 786 unsigned int x = rect->x1; 787 unsigned int y = rect->y1; 788 unsigned int columns = drm_rect_width(rect); 789 unsigned int rows = drm_rect_height(rect); 790 int ret; 791 792 /* 793 * The screen is divided in Segment and Common outputs, where 794 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 795 * the columns. 796 * 797 * Each Segment has a 8-bit pixel and each Common output has a 798 * row of pixels. When using the (default) horizontal address 799 * increment mode, each byte of data sent to the controller has 800 * a Segment (e.g: SEG0). 801 * 802 * When using the 256 color depth format, each pixel contains 3 803 * sub-pixels for color A, B and C. These have 3 bit, 3 bit and 804 * 2 bits respectively. 805 */ 806 807 /* Set column start and end */ 808 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, x, x + columns - 1); 809 if (ret < 0) 810 return ret; 811 812 /* Set row start and end */ 813 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, y, y + rows - 1); 814 if (ret < 0) 815 return ret; 816 817 /* Write out update in one go since horizontal addressing mode is used */ 818 ret = ssd130x_write_data(ssd130x, data_array, pitch * rows); 819 820 return ret; 821 } 822 823 static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 824 { 825 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 826 unsigned int width = ssd130x->width; 827 int ret, i; 828 829 if (!ssd130x->page_address_mode) { 830 memset(data_array, 0, width * pages); 831 832 /* Set address range for horizontal addressing mode */ 833 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset, width); 834 if (ret < 0) 835 return; 836 837 ret = ssd130x_set_page_range(ssd130x, ssd130x->page_offset, pages); 838 if (ret < 0) 839 return; 840 841 /* Write out update in one go if we aren't using page addressing mode */ 842 ssd130x_write_data(ssd130x, data_array, width * pages); 843 } else { 844 /* 845 * In page addressing mode, the start address needs to be reset, 846 * and each page then needs to be written out separately. 847 */ 848 memset(data_array, 0, width); 849 850 for (i = 0; i < pages; i++) { 851 ret = ssd130x_set_page_pos(ssd130x, 852 ssd130x->page_offset + i, 853 ssd130x->col_offset); 854 if (ret < 0) 855 return; 856 857 ret = ssd130x_write_data(ssd130x, data_array, width); 858 if (ret < 0) 859 return; 860 } 861 } 862 } 863 864 static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 865 { 866 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 867 unsigned int height = ssd130x->height; 868 869 memset(data_array, 0, columns * height); 870 871 /* Write out update in one go since horizontal addressing mode is used */ 872 ssd130x_write_data(ssd130x, data_array, columns * height); 873 } 874 875 static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 876 { 877 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 878 unsigned int pitch; 879 880 if (!fi) 881 return; 882 883 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 884 885 memset(data_array, 0, pitch * ssd130x->height); 886 887 /* Write out update in one go since horizontal addressing mode is used */ 888 ssd130x_write_data(ssd130x, data_array, pitch * ssd130x->height); 889 } 890 891 static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb, 892 const struct iosys_map *vmap, 893 struct drm_rect *rect, 894 u8 *buf, u8 *data_array, 895 struct drm_format_conv_state *fmtcnv_state) 896 { 897 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 898 struct iosys_map dst; 899 unsigned int dst_pitch; 900 901 /* Align y to display page boundaries */ 902 rect->y1 = round_down(rect->y1, SSD130X_PAGE_HEIGHT); 903 rect->y2 = min_t(unsigned int, round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height); 904 905 dst_pitch = DIV_ROUND_UP(drm_rect_width(rect), 8); 906 907 iosys_map_set_vaddr(&dst, buf); 908 drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 909 910 ssd130x_update_rect(ssd130x, rect, buf, data_array); 911 912 return 0; 913 } 914 915 static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb, 916 const struct iosys_map *vmap, 917 struct drm_rect *rect, u8 *buf, 918 u8 *data_array, 919 struct drm_format_conv_state *fmtcnv_state) 920 { 921 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 922 unsigned int dst_pitch; 923 struct iosys_map dst; 924 925 /* Align x to display segment boundaries */ 926 rect->x1 = round_down(rect->x1, SSD132X_SEGMENT_WIDTH); 927 rect->x2 = min_t(unsigned int, round_up(rect->x2, SSD132X_SEGMENT_WIDTH), 928 ssd130x->width); 929 930 dst_pitch = drm_rect_width(rect); 931 932 iosys_map_set_vaddr(&dst, buf); 933 drm_fb_xrgb8888_to_gray8(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 934 935 ssd132x_update_rect(ssd130x, rect, buf, data_array); 936 937 return 0; 938 } 939 940 static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb, 941 const struct iosys_map *vmap, 942 struct drm_rect *rect, u8 *data_array, 943 struct drm_format_conv_state *fmtcnv_state) 944 { 945 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 946 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 947 unsigned int dst_pitch; 948 struct iosys_map dst; 949 950 if (!fi) 951 return -EINVAL; 952 953 dst_pitch = drm_format_info_min_pitch(fi, 0, drm_rect_width(rect)); 954 955 iosys_map_set_vaddr(&dst, data_array); 956 drm_fb_xrgb8888_to_rgb332(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 957 958 ssd133x_update_rect(ssd130x, rect, data_array, dst_pitch); 959 960 return 0; 961 } 962 963 static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane, 964 struct drm_atomic_commit *state) 965 { 966 struct drm_device *drm = plane->dev; 967 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 968 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 969 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 970 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 971 struct drm_crtc *crtc = plane_state->crtc; 972 struct drm_crtc_state *crtc_state = NULL; 973 const struct drm_format_info *fi; 974 unsigned int pitch; 975 int ret; 976 977 if (crtc) 978 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 979 980 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 981 DRM_PLANE_NO_SCALING, 982 DRM_PLANE_NO_SCALING, 983 false, false); 984 if (ret) 985 return ret; 986 else if (!plane_state->visible) 987 return 0; 988 989 fi = drm_format_info(DRM_FORMAT_R1); 990 if (!fi) 991 return -EINVAL; 992 993 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 994 995 if (plane_state->fb->format != fi) { 996 void *buf; 997 998 /* format conversion necessary; reserve buffer */ 999 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1000 pitch, GFP_KERNEL); 1001 if (!buf) 1002 return -ENOMEM; 1003 } 1004 1005 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1006 if (!ssd130x_state->buffer) 1007 return -ENOMEM; 1008 1009 return 0; 1010 } 1011 1012 static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane, 1013 struct drm_atomic_commit *state) 1014 { 1015 struct drm_device *drm = plane->dev; 1016 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1017 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1018 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 1019 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 1020 struct drm_crtc *crtc = plane_state->crtc; 1021 struct drm_crtc_state *crtc_state = NULL; 1022 const struct drm_format_info *fi; 1023 unsigned int pitch; 1024 int ret; 1025 1026 if (crtc) 1027 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1028 1029 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1030 DRM_PLANE_NO_SCALING, 1031 DRM_PLANE_NO_SCALING, 1032 false, false); 1033 if (ret) 1034 return ret; 1035 else if (!plane_state->visible) 1036 return 0; 1037 1038 fi = drm_format_info(DRM_FORMAT_R8); 1039 if (!fi) 1040 return -EINVAL; 1041 1042 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1043 1044 if (plane_state->fb->format != fi) { 1045 void *buf; 1046 1047 /* format conversion necessary; reserve buffer */ 1048 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1049 pitch, GFP_KERNEL); 1050 if (!buf) 1051 return -ENOMEM; 1052 } 1053 1054 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1055 if (!ssd130x_state->buffer) 1056 return -ENOMEM; 1057 1058 return 0; 1059 } 1060 1061 static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane, 1062 struct drm_atomic_commit *state) 1063 { 1064 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1065 struct drm_crtc *crtc = plane_state->crtc; 1066 struct drm_crtc_state *crtc_state = NULL; 1067 int ret; 1068 1069 if (crtc) 1070 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1071 1072 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1073 DRM_PLANE_NO_SCALING, 1074 DRM_PLANE_NO_SCALING, 1075 false, false); 1076 if (ret) 1077 return ret; 1078 else if (!plane_state->visible) 1079 return 0; 1080 1081 return 0; 1082 } 1083 1084 static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane, 1085 struct drm_atomic_commit *state) 1086 { 1087 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1088 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1089 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1090 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1091 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1092 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1093 struct drm_framebuffer *fb = plane_state->fb; 1094 struct drm_atomic_helper_damage_iter iter; 1095 struct drm_device *drm = plane->dev; 1096 struct drm_rect dst_clip; 1097 struct drm_rect damage; 1098 int idx; 1099 1100 if (!drm_dev_enter(drm, &idx)) 1101 return; 1102 1103 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1104 goto out_drm_dev_exit; 1105 1106 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1107 drm_atomic_for_each_plane_damage(&iter, &damage) { 1108 dst_clip = plane_state->dst; 1109 1110 if (!drm_rect_intersect(&dst_clip, &damage)) 1111 continue; 1112 1113 ssd130x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1114 ssd130x_plane_state->buffer, 1115 ssd130x_crtc_state->data_array, 1116 &shadow_plane_state->fmtcnv_state); 1117 } 1118 1119 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1120 1121 out_drm_dev_exit: 1122 drm_dev_exit(idx); 1123 } 1124 1125 static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane, 1126 struct drm_atomic_commit *state) 1127 { 1128 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1129 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1130 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1131 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1132 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1133 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1134 struct drm_framebuffer *fb = plane_state->fb; 1135 struct drm_atomic_helper_damage_iter iter; 1136 struct drm_device *drm = plane->dev; 1137 struct drm_rect dst_clip; 1138 struct drm_rect damage; 1139 int idx; 1140 1141 if (!drm_dev_enter(drm, &idx)) 1142 return; 1143 1144 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1145 goto out_drm_dev_exit; 1146 1147 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1148 drm_atomic_for_each_plane_damage(&iter, &damage) { 1149 dst_clip = plane_state->dst; 1150 1151 if (!drm_rect_intersect(&dst_clip, &damage)) 1152 continue; 1153 1154 ssd132x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1155 ssd130x_plane_state->buffer, 1156 ssd130x_crtc_state->data_array, 1157 &shadow_plane_state->fmtcnv_state); 1158 } 1159 1160 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1161 1162 out_drm_dev_exit: 1163 drm_dev_exit(idx); 1164 } 1165 1166 static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane, 1167 struct drm_atomic_commit *state) 1168 { 1169 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1170 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1171 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1172 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1173 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1174 struct drm_framebuffer *fb = plane_state->fb; 1175 struct drm_atomic_helper_damage_iter iter; 1176 struct drm_device *drm = plane->dev; 1177 struct drm_rect dst_clip; 1178 struct drm_rect damage; 1179 int idx; 1180 1181 if (!drm_dev_enter(drm, &idx)) 1182 return; 1183 1184 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1185 goto out_drm_dev_exit; 1186 1187 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1188 drm_atomic_for_each_plane_damage(&iter, &damage) { 1189 dst_clip = plane_state->dst; 1190 1191 if (!drm_rect_intersect(&dst_clip, &damage)) 1192 continue; 1193 1194 ssd133x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1195 ssd130x_crtc_state->data_array, 1196 &shadow_plane_state->fmtcnv_state); 1197 } 1198 1199 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1200 1201 out_drm_dev_exit: 1202 drm_dev_exit(idx); 1203 } 1204 1205 static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane, 1206 struct drm_atomic_commit *state) 1207 { 1208 struct drm_device *drm = plane->dev; 1209 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1210 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1211 struct drm_crtc_state *crtc_state; 1212 struct ssd130x_crtc_state *ssd130x_crtc_state; 1213 int idx; 1214 1215 if (!plane_state->crtc) 1216 return; 1217 1218 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1219 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1220 1221 if (!drm_dev_enter(drm, &idx)) 1222 return; 1223 1224 ssd130x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1225 1226 drm_dev_exit(idx); 1227 } 1228 1229 static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane, 1230 struct drm_atomic_commit *state) 1231 { 1232 struct drm_device *drm = plane->dev; 1233 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1234 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1235 struct drm_crtc_state *crtc_state; 1236 struct ssd130x_crtc_state *ssd130x_crtc_state; 1237 int idx; 1238 1239 if (!plane_state->crtc) 1240 return; 1241 1242 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1243 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1244 1245 if (!drm_dev_enter(drm, &idx)) 1246 return; 1247 1248 ssd132x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1249 1250 drm_dev_exit(idx); 1251 } 1252 1253 static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane, 1254 struct drm_atomic_commit *state) 1255 { 1256 struct drm_device *drm = plane->dev; 1257 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1258 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1259 struct drm_crtc_state *crtc_state; 1260 struct ssd130x_crtc_state *ssd130x_crtc_state; 1261 int idx; 1262 1263 if (!plane_state->crtc) 1264 return; 1265 1266 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1267 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1268 1269 if (!drm_dev_enter(drm, &idx)) 1270 return; 1271 1272 ssd133x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1273 1274 drm_dev_exit(idx); 1275 } 1276 1277 /* Called during init to allocate the plane's atomic state. */ 1278 static void ssd130x_primary_plane_reset(struct drm_plane *plane) 1279 { 1280 struct ssd130x_plane_state *ssd130x_state; 1281 1282 drm_WARN_ON_ONCE(plane->dev, plane->state); 1283 1284 ssd130x_state = kzalloc_obj(*ssd130x_state); 1285 if (!ssd130x_state) 1286 return; 1287 1288 __drm_gem_reset_shadow_plane(plane, &ssd130x_state->base); 1289 } 1290 1291 static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane) 1292 { 1293 struct drm_shadow_plane_state *new_shadow_plane_state; 1294 struct ssd130x_plane_state *old_ssd130x_state; 1295 struct ssd130x_plane_state *ssd130x_state; 1296 1297 if (drm_WARN_ON_ONCE(plane->dev, !plane->state)) 1298 return NULL; 1299 1300 old_ssd130x_state = to_ssd130x_plane_state(plane->state); 1301 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1302 if (!ssd130x_state) 1303 return NULL; 1304 1305 /* The buffer is not duplicated and is allocated in .atomic_check */ 1306 ssd130x_state->buffer = NULL; 1307 1308 new_shadow_plane_state = &ssd130x_state->base; 1309 1310 __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state); 1311 1312 return &new_shadow_plane_state->base; 1313 } 1314 1315 static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane, 1316 struct drm_plane_state *state) 1317 { 1318 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state); 1319 1320 kfree(ssd130x_state->buffer); 1321 1322 __drm_gem_destroy_shadow_plane_state(&ssd130x_state->base); 1323 1324 kfree(ssd130x_state); 1325 } 1326 1327 static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = { 1328 [SSD130X_FAMILY] = { 1329 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1330 .atomic_check = ssd130x_primary_plane_atomic_check, 1331 .atomic_update = ssd130x_primary_plane_atomic_update, 1332 .atomic_disable = ssd130x_primary_plane_atomic_disable, 1333 }, 1334 [SSD132X_FAMILY] = { 1335 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1336 .atomic_check = ssd132x_primary_plane_atomic_check, 1337 .atomic_update = ssd132x_primary_plane_atomic_update, 1338 .atomic_disable = ssd132x_primary_plane_atomic_disable, 1339 }, 1340 [SSD133X_FAMILY] = { 1341 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1342 .atomic_check = ssd133x_primary_plane_atomic_check, 1343 .atomic_update = ssd133x_primary_plane_atomic_update, 1344 .atomic_disable = ssd133x_primary_plane_atomic_disable, 1345 } 1346 }; 1347 1348 static const struct drm_plane_funcs ssd130x_primary_plane_funcs = { 1349 .update_plane = drm_atomic_helper_update_plane, 1350 .disable_plane = drm_atomic_helper_disable_plane, 1351 .reset = ssd130x_primary_plane_reset, 1352 .atomic_duplicate_state = ssd130x_primary_plane_duplicate_state, 1353 .atomic_destroy_state = ssd130x_primary_plane_destroy_state, 1354 .destroy = drm_plane_cleanup, 1355 }; 1356 1357 static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc, 1358 const struct drm_display_mode *mode) 1359 { 1360 struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev); 1361 1362 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &ssd130x->mode); 1363 } 1364 1365 static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc, 1366 struct drm_atomic_commit *state) 1367 { 1368 struct drm_device *drm = crtc->dev; 1369 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1370 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1371 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1372 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 1373 int ret; 1374 1375 ret = drm_crtc_helper_atomic_check(crtc, state); 1376 if (ret) 1377 return ret; 1378 1379 ssd130x_state->data_array = kmalloc_array(ssd130x->width, pages, GFP_KERNEL); 1380 if (!ssd130x_state->data_array) 1381 return -ENOMEM; 1382 1383 return 0; 1384 } 1385 1386 static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc, 1387 struct drm_atomic_commit *state) 1388 { 1389 struct drm_device *drm = crtc->dev; 1390 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1391 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1392 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1393 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 1394 int ret; 1395 1396 ret = drm_crtc_helper_atomic_check(crtc, state); 1397 if (ret) 1398 return ret; 1399 1400 ssd130x_state->data_array = kmalloc_array(columns, ssd130x->height, GFP_KERNEL); 1401 if (!ssd130x_state->data_array) 1402 return -ENOMEM; 1403 1404 return 0; 1405 } 1406 1407 static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc, 1408 struct drm_atomic_commit *state) 1409 { 1410 struct drm_device *drm = crtc->dev; 1411 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1412 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1413 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1414 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 1415 unsigned int pitch; 1416 int ret; 1417 1418 if (!fi) 1419 return -EINVAL; 1420 1421 ret = drm_crtc_helper_atomic_check(crtc, state); 1422 if (ret) 1423 return ret; 1424 1425 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1426 1427 ssd130x_state->data_array = kmalloc_array(pitch, ssd130x->height, GFP_KERNEL); 1428 if (!ssd130x_state->data_array) 1429 return -ENOMEM; 1430 1431 return 0; 1432 } 1433 1434 /* Called during init to allocate the CRTC's atomic state. */ 1435 static void ssd130x_crtc_reset(struct drm_crtc *crtc) 1436 { 1437 struct ssd130x_crtc_state *ssd130x_state; 1438 1439 drm_WARN_ON_ONCE(crtc->dev, crtc->state); 1440 1441 ssd130x_state = kzalloc_obj(*ssd130x_state); 1442 if (!ssd130x_state) 1443 return; 1444 1445 __drm_atomic_helper_crtc_reset(crtc, &ssd130x_state->base); 1446 } 1447 1448 static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc) 1449 { 1450 struct ssd130x_crtc_state *old_ssd130x_state; 1451 struct ssd130x_crtc_state *ssd130x_state; 1452 1453 if (drm_WARN_ON_ONCE(crtc->dev, !crtc->state)) 1454 return NULL; 1455 1456 old_ssd130x_state = to_ssd130x_crtc_state(crtc->state); 1457 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1458 if (!ssd130x_state) 1459 return NULL; 1460 1461 /* The buffer is not duplicated and is allocated in .atomic_check */ 1462 ssd130x_state->data_array = NULL; 1463 1464 __drm_atomic_helper_crtc_duplicate_state(crtc, &ssd130x_state->base); 1465 1466 return &ssd130x_state->base; 1467 } 1468 1469 static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc, 1470 struct drm_crtc_state *state) 1471 { 1472 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state); 1473 1474 kfree(ssd130x_state->data_array); 1475 1476 __drm_atomic_helper_crtc_destroy_state(state); 1477 1478 kfree(ssd130x_state); 1479 } 1480 1481 /* 1482 * The CRTC is always enabled. Screen updates are performed by 1483 * the primary plane's atomic_update function. Disabling clears 1484 * the screen in the primary plane's atomic_disable function. 1485 */ 1486 static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = { 1487 [SSD130X_FAMILY] = { 1488 .mode_valid = ssd130x_crtc_mode_valid, 1489 .atomic_check = ssd130x_crtc_atomic_check, 1490 }, 1491 [SSD132X_FAMILY] = { 1492 .mode_valid = ssd130x_crtc_mode_valid, 1493 .atomic_check = ssd132x_crtc_atomic_check, 1494 }, 1495 [SSD133X_FAMILY] = { 1496 .mode_valid = ssd130x_crtc_mode_valid, 1497 .atomic_check = ssd133x_crtc_atomic_check, 1498 }, 1499 }; 1500 1501 static const struct drm_crtc_funcs ssd130x_crtc_funcs = { 1502 .reset = ssd130x_crtc_reset, 1503 .destroy = drm_crtc_cleanup, 1504 .set_config = drm_atomic_helper_set_config, 1505 .page_flip = drm_atomic_helper_page_flip, 1506 .atomic_duplicate_state = ssd130x_crtc_duplicate_state, 1507 .atomic_destroy_state = ssd130x_crtc_destroy_state, 1508 }; 1509 1510 static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder, 1511 struct drm_atomic_commit *state) 1512 { 1513 struct drm_device *drm = encoder->dev; 1514 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1515 int ret; 1516 1517 ret = ssd130x_power_on(ssd130x); 1518 if (ret) 1519 return; 1520 1521 ret = ssd130x_init(ssd130x); 1522 if (ret) 1523 goto power_off; 1524 1525 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1526 1527 backlight_enable(ssd130x->bl_dev); 1528 1529 return; 1530 1531 power_off: 1532 ssd130x_power_off(ssd130x); 1533 return; 1534 } 1535 1536 static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder, 1537 struct drm_atomic_commit *state) 1538 { 1539 struct drm_device *drm = encoder->dev; 1540 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1541 int ret; 1542 1543 ret = ssd130x_power_on(ssd130x); 1544 if (ret) 1545 return; 1546 1547 ret = ssd132x_init(ssd130x); 1548 if (ret) 1549 goto power_off; 1550 1551 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1552 1553 backlight_enable(ssd130x->bl_dev); 1554 1555 return; 1556 1557 power_off: 1558 ssd130x_power_off(ssd130x); 1559 } 1560 1561 static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder, 1562 struct drm_atomic_commit *state) 1563 { 1564 struct drm_device *drm = encoder->dev; 1565 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1566 int ret; 1567 1568 ret = ssd130x_power_on(ssd130x); 1569 if (ret) 1570 return; 1571 1572 ret = ssd133x_init(ssd130x); 1573 if (ret) 1574 goto power_off; 1575 1576 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1577 1578 backlight_enable(ssd130x->bl_dev); 1579 1580 return; 1581 1582 power_off: 1583 ssd130x_power_off(ssd130x); 1584 } 1585 1586 static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder, 1587 struct drm_atomic_commit *state) 1588 { 1589 struct drm_device *drm = encoder->dev; 1590 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1591 1592 backlight_disable(ssd130x->bl_dev); 1593 1594 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_OFF); 1595 1596 ssd130x_power_off(ssd130x); 1597 } 1598 1599 static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = { 1600 [SSD130X_FAMILY] = { 1601 .atomic_enable = ssd130x_encoder_atomic_enable, 1602 .atomic_disable = ssd130x_encoder_atomic_disable, 1603 }, 1604 [SSD132X_FAMILY] = { 1605 .atomic_enable = ssd132x_encoder_atomic_enable, 1606 .atomic_disable = ssd130x_encoder_atomic_disable, 1607 }, 1608 [SSD133X_FAMILY] = { 1609 .atomic_enable = ssd133x_encoder_atomic_enable, 1610 .atomic_disable = ssd130x_encoder_atomic_disable, 1611 } 1612 }; 1613 1614 static const struct drm_encoder_funcs ssd130x_encoder_funcs = { 1615 .destroy = drm_encoder_cleanup, 1616 }; 1617 1618 static int ssd130x_connector_get_modes(struct drm_connector *connector) 1619 { 1620 struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev); 1621 1622 return drm_connector_helper_get_modes_fixed(connector, &ssd130x->mode); 1623 } 1624 1625 static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = { 1626 .get_modes = ssd130x_connector_get_modes, 1627 }; 1628 1629 static const struct drm_connector_funcs ssd130x_connector_funcs = { 1630 .reset = drm_atomic_helper_connector_reset, 1631 .fill_modes = drm_helper_probe_single_connector_modes, 1632 .destroy = drm_connector_cleanup, 1633 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1634 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1635 }; 1636 1637 static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = { 1638 .fb_create = drm_gem_fb_create_with_dirty, 1639 .atomic_check = drm_atomic_helper_check, 1640 .atomic_commit = drm_atomic_helper_commit, 1641 }; 1642 1643 static const uint32_t ssd130x_formats[] = { 1644 DRM_FORMAT_XRGB8888, 1645 }; 1646 1647 DEFINE_DRM_GEM_FOPS(ssd130x_fops); 1648 1649 static const struct drm_driver ssd130x_drm_driver = { 1650 DRM_GEM_SHMEM_DRIVER_OPS, 1651 DRM_FBDEV_SHMEM_DRIVER_OPS, 1652 .name = DRIVER_NAME, 1653 .desc = DRIVER_DESC, 1654 .major = DRIVER_MAJOR, 1655 .minor = DRIVER_MINOR, 1656 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1657 .fops = &ssd130x_fops, 1658 }; 1659 1660 static int ssd130x_update_bl(struct backlight_device *bdev) 1661 { 1662 struct ssd130x_device *ssd130x = bl_get_data(bdev); 1663 int brightness = backlight_get_brightness(bdev); 1664 int ret; 1665 1666 ssd130x->contrast = brightness; 1667 1668 ret = ssd130x_write_cmd(ssd130x, 1, SSD13XX_CONTRAST); 1669 if (ret < 0) 1670 return ret; 1671 1672 ret = ssd130x_write_cmd(ssd130x, 1, ssd130x->contrast); 1673 if (ret < 0) 1674 return ret; 1675 1676 return 0; 1677 } 1678 1679 static const struct backlight_ops ssd130xfb_bl_ops = { 1680 .update_status = ssd130x_update_bl, 1681 }; 1682 1683 static void ssd130x_parse_properties(struct ssd130x_device *ssd130x) 1684 { 1685 struct device *dev = ssd130x->dev; 1686 1687 if (device_property_read_u32(dev, "solomon,width", &ssd130x->width)) 1688 ssd130x->width = ssd130x->device_info->default_width; 1689 1690 if (device_property_read_u32(dev, "solomon,height", &ssd130x->height)) 1691 ssd130x->height = ssd130x->device_info->default_height; 1692 1693 if (device_property_read_u32(dev, "solomon,page-offset", &ssd130x->page_offset)) 1694 ssd130x->page_offset = 1; 1695 1696 if (device_property_read_u32(dev, "solomon,col-offset", &ssd130x->col_offset)) 1697 ssd130x->col_offset = 0; 1698 1699 if (device_property_read_u32(dev, "solomon,com-offset", &ssd130x->com_offset)) 1700 ssd130x->com_offset = 0; 1701 1702 if (device_property_read_u32(dev, "solomon,prechargep1", &ssd130x->prechargep1)) 1703 ssd130x->prechargep1 = 2; 1704 1705 if (device_property_read_u32(dev, "solomon,prechargep2", &ssd130x->prechargep2)) 1706 ssd130x->prechargep2 = 2; 1707 1708 if (!device_property_read_u8_array(dev, "solomon,lookup-table", 1709 ssd130x->lookup_table, 1710 ARRAY_SIZE(ssd130x->lookup_table))) 1711 ssd130x->lookup_table_set = 1; 1712 1713 ssd130x->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap"); 1714 ssd130x->com_seq = device_property_read_bool(dev, "solomon,com-seq"); 1715 ssd130x->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap"); 1716 ssd130x->com_invdir = device_property_read_bool(dev, "solomon,com-invdir"); 1717 ssd130x->area_color_enable = 1718 device_property_read_bool(dev, "solomon,area-color-enable"); 1719 ssd130x->low_power = device_property_read_bool(dev, "solomon,low-power"); 1720 1721 ssd130x->contrast = 127; 1722 ssd130x->vcomh = ssd130x->device_info->default_vcomh; 1723 1724 /* Setup display timing */ 1725 if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div)) 1726 ssd130x->dclk_div = ssd130x->device_info->default_dclk_div; 1727 if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq)) 1728 ssd130x->dclk_frq = ssd130x->device_info->default_dclk_frq; 1729 } 1730 1731 static int ssd130x_init_modeset(struct ssd130x_device *ssd130x) 1732 { 1733 enum ssd130x_family_ids family_id = ssd130x->device_info->family_id; 1734 struct drm_display_mode *mode = &ssd130x->mode; 1735 struct device *dev = ssd130x->dev; 1736 struct drm_device *drm = &ssd130x->drm; 1737 unsigned long max_width, max_height; 1738 struct drm_plane *primary_plane; 1739 struct drm_crtc *crtc; 1740 struct drm_encoder *encoder; 1741 struct drm_connector *connector; 1742 int ret; 1743 1744 /* 1745 * Modesetting 1746 */ 1747 1748 ret = drmm_mode_config_init(drm); 1749 if (ret) { 1750 dev_err(dev, "DRM mode config init failed: %d\n", ret); 1751 return ret; 1752 } 1753 1754 mode->type = DRM_MODE_TYPE_DRIVER; 1755 mode->clock = 1; 1756 mode->hdisplay = ssd130x->width; 1757 mode->htotal = ssd130x->width; 1758 mode->hsync_start = ssd130x->width; 1759 mode->hsync_end = ssd130x->width; 1760 mode->vdisplay = ssd130x->height; 1761 mode->vtotal = ssd130x->height; 1762 mode->vsync_start = ssd130x->height; 1763 mode->vsync_end = ssd130x->height; 1764 mode->width_mm = 27; 1765 mode->height_mm = 27; 1766 1767 max_width = max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH); 1768 max_height = max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT); 1769 1770 drm->mode_config.min_width = mode->hdisplay; 1771 drm->mode_config.max_width = max_width; 1772 drm->mode_config.min_height = mode->vdisplay; 1773 drm->mode_config.max_height = max_height; 1774 drm->mode_config.preferred_depth = 24; 1775 drm->mode_config.funcs = &ssd130x_mode_config_funcs; 1776 1777 /* Primary plane */ 1778 1779 primary_plane = &ssd130x->primary_plane; 1780 ret = drm_universal_plane_init(drm, primary_plane, 0, &ssd130x_primary_plane_funcs, 1781 ssd130x_formats, ARRAY_SIZE(ssd130x_formats), 1782 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1783 if (ret) { 1784 dev_err(dev, "DRM primary plane init failed: %d\n", ret); 1785 return ret; 1786 } 1787 1788 drm_plane_helper_add(primary_plane, &ssd130x_primary_plane_helper_funcs[family_id]); 1789 1790 drm_plane_enable_fb_damage_clips(primary_plane); 1791 1792 /* CRTC */ 1793 1794 crtc = &ssd130x->crtc; 1795 ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1796 &ssd130x_crtc_funcs, NULL); 1797 if (ret) { 1798 dev_err(dev, "DRM crtc init failed: %d\n", ret); 1799 return ret; 1800 } 1801 1802 drm_crtc_helper_add(crtc, &ssd130x_crtc_helper_funcs[family_id]); 1803 1804 /* Encoder */ 1805 1806 encoder = &ssd130x->encoder; 1807 ret = drm_encoder_init(drm, encoder, &ssd130x_encoder_funcs, 1808 DRM_MODE_ENCODER_NONE, NULL); 1809 if (ret) { 1810 dev_err(dev, "DRM encoder init failed: %d\n", ret); 1811 return ret; 1812 } 1813 1814 drm_encoder_helper_add(encoder, &ssd130x_encoder_helper_funcs[family_id]); 1815 1816 encoder->possible_crtcs = drm_crtc_mask(crtc); 1817 1818 /* Connector */ 1819 1820 connector = &ssd130x->connector; 1821 ret = drm_connector_init(drm, connector, &ssd130x_connector_funcs, 1822 DRM_MODE_CONNECTOR_Unknown); 1823 if (ret) { 1824 dev_err(dev, "DRM connector init failed: %d\n", ret); 1825 return ret; 1826 } 1827 1828 drm_connector_helper_add(connector, &ssd130x_connector_helper_funcs); 1829 1830 ret = drm_connector_attach_encoder(connector, encoder); 1831 if (ret) { 1832 dev_err(dev, "DRM attach connector to encoder failed: %d\n", ret); 1833 return ret; 1834 } 1835 1836 drm_mode_config_reset(drm); 1837 1838 return 0; 1839 } 1840 1841 static int ssd130x_get_resources(struct ssd130x_device *ssd130x) 1842 { 1843 struct device *dev = ssd130x->dev; 1844 1845 ssd130x->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1846 if (IS_ERR(ssd130x->reset)) 1847 return dev_err_probe(dev, PTR_ERR(ssd130x->reset), 1848 "Failed to get reset gpio\n"); 1849 1850 ssd130x->vcc_reg = devm_regulator_get(dev, "vcc"); 1851 if (IS_ERR(ssd130x->vcc_reg)) 1852 return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg), 1853 "Failed to get VCC regulator\n"); 1854 1855 return 0; 1856 } 1857 1858 struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap) 1859 { 1860 struct ssd130x_device *ssd130x; 1861 struct backlight_device *bl; 1862 struct drm_device *drm; 1863 int ret; 1864 1865 ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver, 1866 struct ssd130x_device, drm); 1867 if (IS_ERR(ssd130x)) 1868 return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x), 1869 "Failed to allocate DRM device\n")); 1870 1871 drm = &ssd130x->drm; 1872 1873 ssd130x->dev = dev; 1874 ssd130x->regmap = regmap; 1875 ssd130x->device_info = device_get_match_data(dev); 1876 1877 if (ssd130x->device_info->page_mode_only) 1878 ssd130x->page_address_mode = 1; 1879 1880 ssd130x_parse_properties(ssd130x); 1881 1882 ret = ssd130x_get_resources(ssd130x); 1883 if (ret) 1884 return ERR_PTR(ret); 1885 1886 bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x, 1887 &ssd130xfb_bl_ops, NULL); 1888 if (IS_ERR(bl)) 1889 return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl), 1890 "Unable to register backlight device\n")); 1891 1892 bl->props.brightness = ssd130x->contrast; 1893 bl->props.max_brightness = MAX_CONTRAST; 1894 ssd130x->bl_dev = bl; 1895 1896 ret = ssd130x_init_modeset(ssd130x); 1897 if (ret) 1898 return ERR_PTR(ret); 1899 1900 ret = drm_dev_register(drm, 0); 1901 if (ret) 1902 return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n")); 1903 1904 drm_client_setup(drm, NULL); 1905 1906 return ssd130x; 1907 } 1908 EXPORT_SYMBOL_GPL(ssd130x_probe); 1909 1910 void ssd130x_remove(struct ssd130x_device *ssd130x) 1911 { 1912 drm_dev_unplug(&ssd130x->drm); 1913 drm_atomic_helper_shutdown(&ssd130x->drm); 1914 } 1915 EXPORT_SYMBOL_GPL(ssd130x_remove); 1916 1917 void ssd130x_shutdown(struct ssd130x_device *ssd130x) 1918 { 1919 drm_atomic_helper_shutdown(&ssd130x->drm); 1920 } 1921 EXPORT_SYMBOL_GPL(ssd130x_shutdown); 1922 1923 MODULE_DESCRIPTION(DRIVER_DESC); 1924 MODULE_AUTHOR("Javier Martinez Canillas <javierm@redhat.com>"); 1925 MODULE_LICENSE("GPL v2"); 1926