1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DRM driver for Solomon SSD13xx OLED displays 4 * 5 * Copyright 2022 Red Hat Inc. 6 * Author: Javier Martinez Canillas <javierm@redhat.com> 7 * 8 * Based on drivers/video/fbdev/ssd1307fb.c 9 * Copyright 2012 Free Electrons 10 */ 11 12 #include <linux/backlight.h> 13 #include <linux/bitfield.h> 14 #include <linux/bits.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/math.h> 18 #include <linux/property.h> 19 #include <linux/pwm.h> 20 #include <linux/regulator/consumer.h> 21 22 #include <drm/clients/drm_client_setup.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_damage_helper.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_fbdev_shmem.h> 29 #include <drm/drm_format_helper.h> 30 #include <drm/drm_framebuffer.h> 31 #include <drm/drm_gem_atomic_helper.h> 32 #include <drm/drm_gem_framebuffer_helper.h> 33 #include <drm/drm_gem_shmem_helper.h> 34 #include <drm/drm_managed.h> 35 #include <drm/drm_modes.h> 36 #include <drm/drm_rect.h> 37 #include <drm/drm_print.h> 38 #include <drm/drm_probe_helper.h> 39 40 #include "ssd130x.h" 41 42 #define DRIVER_NAME "ssd130x" 43 #define DRIVER_DESC "DRM driver for Solomon SSD13xx OLED displays" 44 #define DRIVER_MAJOR 1 45 #define DRIVER_MINOR 0 46 47 #define SSD130X_PAGE_HEIGHT 8 48 49 #define SSD132X_SEGMENT_WIDTH 2 50 51 /* ssd13xx commands */ 52 #define SSD13XX_CONTRAST 0x81 53 #define SSD13XX_SET_SEG_REMAP 0xa0 54 #define SSD13XX_SET_MULTIPLEX_RATIO 0xa8 55 #define SSD13XX_DISPLAY_OFF 0xae 56 #define SSD13XX_DISPLAY_ON 0xaf 57 58 #define SSD13XX_SET_SEG_REMAP_MASK GENMASK(0, 0) 59 #define SSD13XX_SET_SEG_REMAP_SET(val) FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val)) 60 61 /* ssd130x commands */ 62 #define SSD130X_PAGE_COL_START_LOW 0x00 63 #define SSD130X_PAGE_COL_START_HIGH 0x10 64 #define SSD130X_SET_ADDRESS_MODE 0x20 65 #define SSD130X_SET_COL_RANGE 0x21 66 #define SSD130X_SET_PAGE_RANGE 0x22 67 #define SSD130X_SET_LOOKUP_TABLE 0x91 68 #define SSD130X_CHARGE_PUMP 0x8d 69 #define SSD130X_START_PAGE_ADDRESS 0xb0 70 #define SSD130X_SET_COM_SCAN_DIR 0xc0 71 #define SSD130X_SET_DISPLAY_OFFSET 0xd3 72 #define SSD130X_SET_CLOCK_FREQ 0xd5 73 #define SSD130X_SET_AREA_COLOR_MODE 0xd8 74 #define SSD130X_SET_PRECHARGE_PERIOD 0xd9 75 #define SSD130X_SET_COM_PINS_CONFIG 0xda 76 #define SSD130X_SET_VCOMH 0xdb 77 78 /* ssd130x commands accessors */ 79 #define SSD130X_PAGE_COL_START_MASK GENMASK(3, 0) 80 #define SSD130X_PAGE_COL_START_HIGH_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4) 81 #define SSD130X_PAGE_COL_START_LOW_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val)) 82 #define SSD130X_START_PAGE_ADDRESS_MASK GENMASK(2, 0) 83 #define SSD130X_START_PAGE_ADDRESS_SET(val) FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val)) 84 #define SSD130X_SET_COM_SCAN_DIR_MASK GENMASK(3, 3) 85 #define SSD130X_SET_COM_SCAN_DIR_SET(val) FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val)) 86 #define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0) 87 #define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val)) 88 #define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4) 89 #define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val)) 90 #define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0) 91 #define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val)) 92 #define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4) 93 #define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val)) 94 #define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4) 95 #define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val)) 96 #define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5) 97 #define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val)) 98 99 #define SSD130X_SET_ADDRESS_MODE_HORIZONTAL 0x00 100 #define SSD130X_SET_ADDRESS_MODE_VERTICAL 0x01 101 #define SSD130X_SET_ADDRESS_MODE_PAGE 0x02 102 103 #define SSD130X_SET_AREA_COLOR_MODE_ENABLE 0x1e 104 #define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER 0x05 105 106 /* ssd132x commands */ 107 #define SSD132X_SET_COL_RANGE 0x15 108 #define SSD132X_SET_DEACTIVATE_SCROLL 0x2e 109 #define SSD132X_SET_ROW_RANGE 0x75 110 #define SSD132X_SET_DISPLAY_START 0xa1 111 #define SSD132X_SET_DISPLAY_OFFSET 0xa2 112 #define SSD132X_SET_DISPLAY_NORMAL 0xa4 113 #define SSD132X_SET_FUNCTION_SELECT_A 0xab 114 #define SSD132X_SET_PHASE_LENGTH 0xb1 115 #define SSD132X_SET_CLOCK_FREQ 0xb3 116 #define SSD132X_SET_GPIO 0xb5 117 #define SSD132X_SET_PRECHARGE_PERIOD 0xb6 118 #define SSD132X_SET_GRAY_SCALE_TABLE 0xb8 119 #define SSD132X_SELECT_DEFAULT_TABLE 0xb9 120 #define SSD132X_SET_PRECHARGE_VOLTAGE 0xbc 121 #define SSD130X_SET_VCOMH_VOLTAGE 0xbe 122 #define SSD132X_SET_FUNCTION_SELECT_B 0xd5 123 124 /* ssd133x commands */ 125 #define SSD133X_SET_COL_RANGE 0x15 126 #define SSD133X_SET_ROW_RANGE 0x75 127 #define SSD133X_CONTRAST_A 0x81 128 #define SSD133X_CONTRAST_B 0x82 129 #define SSD133X_CONTRAST_C 0x83 130 #define SSD133X_SET_MASTER_CURRENT 0x87 131 #define SSD132X_SET_PRECHARGE_A 0x8a 132 #define SSD132X_SET_PRECHARGE_B 0x8b 133 #define SSD132X_SET_PRECHARGE_C 0x8c 134 #define SSD133X_SET_DISPLAY_START 0xa1 135 #define SSD133X_SET_DISPLAY_OFFSET 0xa2 136 #define SSD133X_SET_DISPLAY_NORMAL 0xa4 137 #define SSD133X_SET_MASTER_CONFIG 0xad 138 #define SSD133X_POWER_SAVE_MODE 0xb0 139 #define SSD133X_PHASES_PERIOD 0xb1 140 #define SSD133X_SET_CLOCK_FREQ 0xb3 141 #define SSD133X_SET_PRECHARGE_VOLTAGE 0xbb 142 #define SSD133X_SET_VCOMH_VOLTAGE 0xbe 143 144 /* ssd133x A/B/C channel contrast at full brightness (white balance) */ 145 #define SSD133X_DEFAULT_CONTRAST_A 0x91 146 #define SSD133X_DEFAULT_CONTRAST_B 0x50 147 #define SSD133X_DEFAULT_CONTRAST_C 0x7d 148 149 #define MAX_CONTRAST 255 150 151 const struct ssd130x_deviceinfo ssd130x_variants[] = { 152 [SH1106_ID] = { 153 .default_vcomh = 0x40, 154 .default_dclk_div = 1, 155 .default_dclk_frq = 5, 156 .default_width = 132, 157 .default_height = 64, 158 .page_mode_only = 1, 159 .family_id = SSD130X_FAMILY, 160 }, 161 [SSD1305_ID] = { 162 .default_vcomh = 0x34, 163 .default_dclk_div = 1, 164 .default_dclk_frq = 7, 165 .default_width = 132, 166 .default_height = 64, 167 .family_id = SSD130X_FAMILY, 168 }, 169 [SSD1306_ID] = { 170 .default_vcomh = 0x20, 171 .default_dclk_div = 1, 172 .default_dclk_frq = 8, 173 .need_chargepump = 1, 174 .default_width = 128, 175 .default_height = 64, 176 .family_id = SSD130X_FAMILY, 177 }, 178 [SSD1307_ID] = { 179 .default_vcomh = 0x20, 180 .default_dclk_div = 2, 181 .default_dclk_frq = 12, 182 .need_pwm = 1, 183 .default_width = 128, 184 .default_height = 39, 185 .family_id = SSD130X_FAMILY, 186 }, 187 [SSD1309_ID] = { 188 .default_vcomh = 0x34, 189 .default_dclk_div = 1, 190 .default_dclk_frq = 10, 191 .default_width = 128, 192 .default_height = 64, 193 .family_id = SSD130X_FAMILY, 194 }, 195 /* ssd132x family */ 196 [SSD1322_ID] = { 197 .default_width = 480, 198 .default_height = 128, 199 .family_id = SSD132X_FAMILY, 200 }, 201 [SSD1325_ID] = { 202 .default_width = 128, 203 .default_height = 80, 204 .family_id = SSD132X_FAMILY, 205 }, 206 [SSD1327_ID] = { 207 .default_width = 128, 208 .default_height = 128, 209 .family_id = SSD132X_FAMILY, 210 }, 211 /* ssd133x family */ 212 [SSD1331_ID] = { 213 .default_width = 96, 214 .default_height = 64, 215 .family_id = SSD133X_FAMILY, 216 } 217 }; 218 EXPORT_SYMBOL_NS_GPL(ssd130x_variants, "DRM_SSD130X"); 219 220 struct ssd130x_crtc_state { 221 struct drm_crtc_state base; 222 /* Buffer to store pixels in HW format and written to the panel */ 223 u8 *data_array; 224 }; 225 226 struct ssd130x_plane_state { 227 struct drm_shadow_plane_state base; 228 /* Intermediate buffer to convert pixels from XRGB8888 to HW format */ 229 u8 *buffer; 230 }; 231 232 static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state) 233 { 234 return container_of(state, struct ssd130x_crtc_state, base); 235 } 236 237 static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state) 238 { 239 return container_of(state, struct ssd130x_plane_state, base.base); 240 } 241 242 static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm) 243 { 244 return container_of(drm, struct ssd130x_device, drm); 245 } 246 247 /* 248 * Helper to write data (SSD13XX_DATA) to the device. 249 */ 250 static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count) 251 { 252 return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count); 253 } 254 255 /* 256 * Helper to write command (SSD13XX_COMMAND). The fist variadic argument 257 * is the command to write and the following are the command options. 258 * 259 * Note that the ssd13xx protocol requires each command and option to be 260 * written as a SSD13XX_COMMAND device register value. That is why a call 261 * to regmap_write(..., SSD13XX_COMMAND, ...) is done for each argument. 262 */ 263 static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count, 264 /* u8 cmd, u8 option, ... */...) 265 { 266 va_list ap; 267 u8 value; 268 int ret; 269 270 va_start(ap, count); 271 272 do { 273 value = va_arg(ap, int); 274 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, value); 275 if (ret) 276 goto out_end; 277 } while (--count); 278 279 out_end: 280 va_end(ap); 281 282 return ret; 283 } 284 285 /* 286 * Write a command byte sequence from a buffer. 287 * 288 * Like ssd130x_write_cmd() but takes a pre-built byte array instead of 289 * variadic arguments, handy when the command is already in an array or 290 * when the caller wants to use sizeof() for the length. 291 */ 292 static int ssd130x_write_cmds(struct ssd130x_device *ssd130x, const u8 *cmd, 293 size_t len) 294 { 295 unsigned int i; 296 int ret; 297 298 for (i = 0; i < len; i++) { 299 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, cmd[i]); 300 if (ret) 301 return ret; 302 } 303 304 return 0; 305 } 306 307 /* 308 * Run a packed command sequence. The format is a flat byte array where each 309 * entry starts with a length byte followed by that many command bytes. A 310 * zero length byte terminates the sequence. 311 * 312 * Example: { 2, 0x81, 0x80, 1, 0xAF, 0 } 313 * sends command {0x81, 0x80}, then command {0xAF}, then stops. 314 */ 315 static int ssd130x_run_cmd_seq(struct ssd130x_device *ssd130x, const u8 *seq) 316 { 317 while (*seq) { 318 u8 len = *seq++; 319 int ret = ssd130x_write_cmds(ssd130x, seq, len); 320 321 if (ret) 322 return ret; 323 seq += len; 324 } 325 326 return 0; 327 } 328 /* Set address range for horizontal/vertical addressing modes */ 329 static int ssd130x_set_col_range(struct ssd130x_device *ssd130x, 330 u8 col_start, u8 cols) 331 { 332 u8 col_end = col_start + cols - 1; 333 int ret; 334 335 if (col_start == ssd130x->col_start && col_end == ssd130x->col_end) 336 return 0; 337 338 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_COL_RANGE, col_start, col_end); 339 if (ret < 0) 340 return ret; 341 342 ssd130x->col_start = col_start; 343 ssd130x->col_end = col_end; 344 return 0; 345 } 346 347 static int ssd130x_set_page_range(struct ssd130x_device *ssd130x, 348 u8 page_start, u8 pages) 349 { 350 u8 page_end = page_start + pages - 1; 351 int ret; 352 353 if (page_start == ssd130x->page_start && page_end == ssd130x->page_end) 354 return 0; 355 356 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_PAGE_RANGE, page_start, page_end); 357 if (ret < 0) 358 return ret; 359 360 ssd130x->page_start = page_start; 361 ssd130x->page_end = page_end; 362 return 0; 363 } 364 365 /* Set page and column start address for page addressing mode */ 366 static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x, 367 u8 page_start, u8 col_start) 368 { 369 int ret; 370 u32 page, col_low, col_high; 371 372 page = SSD130X_START_PAGE_ADDRESS | 373 SSD130X_START_PAGE_ADDRESS_SET(page_start); 374 col_low = SSD130X_PAGE_COL_START_LOW | 375 SSD130X_PAGE_COL_START_LOW_SET(col_start); 376 col_high = SSD130X_PAGE_COL_START_HIGH | 377 SSD130X_PAGE_COL_START_HIGH_SET(col_start); 378 ret = ssd130x_write_cmd(ssd130x, 3, page, col_low, col_high); 379 if (ret < 0) 380 return ret; 381 382 return 0; 383 } 384 385 static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x) 386 { 387 struct device *dev = ssd130x->dev; 388 struct pwm_state pwmstate; 389 390 ssd130x->pwm = pwm_get(dev, NULL); 391 if (IS_ERR(ssd130x->pwm)) { 392 dev_err(dev, "Could not get PWM from firmware description!\n"); 393 return PTR_ERR(ssd130x->pwm); 394 } 395 396 pwm_init_state(ssd130x->pwm, &pwmstate); 397 pwm_set_relative_duty_cycle(&pwmstate, 50, 100); 398 pwm_apply_might_sleep(ssd130x->pwm, &pwmstate); 399 400 /* Enable the PWM */ 401 pwm_enable(ssd130x->pwm); 402 403 dev_dbg(dev, "Using PWM %s with a %lluns period.\n", 404 ssd130x->pwm->label, pwm_get_period(ssd130x->pwm)); 405 406 return 0; 407 } 408 409 static void ssd130x_reset(struct ssd130x_device *ssd130x) 410 { 411 if (!ssd130x->reset) 412 return; 413 414 /* Reset the screen */ 415 gpiod_set_value_cansleep(ssd130x->reset, 1); 416 udelay(4); 417 gpiod_set_value_cansleep(ssd130x->reset, 0); 418 udelay(4); 419 } 420 421 static int ssd130x_power_on(struct ssd130x_device *ssd130x) 422 { 423 struct device *dev = ssd130x->dev; 424 int ret; 425 426 ssd130x_reset(ssd130x); 427 428 ret = regulator_enable(ssd130x->vcc_reg); 429 if (ret) { 430 dev_err(dev, "Failed to enable VCC: %d\n", ret); 431 return ret; 432 } 433 434 if (ssd130x->device_info->need_pwm) { 435 ret = ssd130x_pwm_enable(ssd130x); 436 if (ret) { 437 dev_err(dev, "Failed to enable PWM: %d\n", ret); 438 regulator_disable(ssd130x->vcc_reg); 439 return ret; 440 } 441 } 442 443 return 0; 444 } 445 446 static void ssd130x_power_off(struct ssd130x_device *ssd130x) 447 { 448 pwm_disable(ssd130x->pwm); 449 pwm_put(ssd130x->pwm); 450 451 regulator_disable(ssd130x->vcc_reg); 452 } 453 454 static int ssd130x_init(struct ssd130x_device *ssd130x) 455 { 456 u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap; 457 bool scan_mode; 458 int ret; 459 460 /* Set segment re-map */ 461 seg_remap = (SSD13XX_SET_SEG_REMAP | 462 SSD13XX_SET_SEG_REMAP_SET(ssd130x->seg_remap)); 463 /* Set COM direction */ 464 com_invdir = (SSD130X_SET_COM_SCAN_DIR | 465 SSD130X_SET_COM_SCAN_DIR_SET(ssd130x->com_invdir)); 466 /* Set clock frequency */ 467 dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) | 468 SSD130X_SET_CLOCK_FREQ_SET(ssd130x->dclk_frq)); 469 470 const u8 *cmds = (const u8[]) { 471 2, SSD13XX_CONTRAST, ssd130x->contrast, 472 1, seg_remap, 473 1, com_invdir, 0, 474 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 475 2, SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset, 476 2, SSD130X_SET_CLOCK_FREQ, dclk, 477 0, 478 }; 479 ret = ssd130x_run_cmd_seq(ssd130x, cmds); 480 if (ret < 0) 481 return ret; 482 483 /* Set Area Color Mode ON/OFF & Low Power Display Mode */ 484 if (ssd130x->area_color_enable || ssd130x->low_power) { 485 u32 mode = 0; 486 487 if (ssd130x->area_color_enable) 488 mode |= SSD130X_SET_AREA_COLOR_MODE_ENABLE; 489 490 if (ssd130x->low_power) 491 mode |= SSD130X_SET_AREA_COLOR_MODE_LOW_POWER; 492 493 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_AREA_COLOR_MODE, mode); 494 if (ret < 0) 495 return ret; 496 } 497 498 /* Set precharge period in number of ticks from the internal clock */ 499 precharge = (SSD130X_SET_PRECHARGE_PERIOD1_SET(ssd130x->prechargep1) | 500 SSD130X_SET_PRECHARGE_PERIOD2_SET(ssd130x->prechargep2)); 501 502 /* Set COM pins configuration */ 503 compins = BIT(1); 504 /* 505 * The COM scan mode field values are the inverse of the boolean DT 506 * property "solomon,com-seq". The value 0b means scan from COM0 to 507 * COM[N - 1] while 1b means scan from COM[N - 1] to COM0. 508 */ 509 scan_mode = !ssd130x->com_seq; 510 compins |= (SSD130X_SET_COM_PINS_CONFIG1_SET(scan_mode) | 511 SSD130X_SET_COM_PINS_CONFIG2_SET(ssd130x->com_lrremap)); 512 513 /* Turn on the DC-DC Charge Pump */ 514 chargepump = BIT(4); 515 if (ssd130x->device_info->need_chargepump) 516 chargepump |= BIT(2); 517 518 cmds = (const u8[]) { 519 2, SSD130X_SET_PRECHARGE_PERIOD, precharge, 520 2, SSD130X_SET_COM_PINS_CONFIG, compins, 521 2, SSD130X_SET_VCOMH, ssd130x->vcomh, 522 2, SSD130X_CHARGE_PUMP, chargepump, 523 0 524 }; 525 ret = ssd130x_run_cmd_seq(ssd130x, cmds); 526 if (ret < 0) 527 return ret; 528 529 /* Set lookup table */ 530 if (ssd130x->lookup_table_set) { 531 int i; 532 533 ret = ssd130x_write_cmd(ssd130x, 1, SSD130X_SET_LOOKUP_TABLE); 534 if (ret < 0) 535 return ret; 536 537 for (i = 0; i < ARRAY_SIZE(ssd130x->lookup_table); i++) { 538 u8 val = ssd130x->lookup_table[i]; 539 540 if (val < 31 || val > 63) 541 dev_warn(ssd130x->dev, 542 "lookup table index %d value out of range 31 <= %d <= 63\n", 543 i, val); 544 ret = ssd130x_write_cmd(ssd130x, 1, val); 545 if (ret < 0) 546 return ret; 547 } 548 } 549 550 /* Switch to page addressing mode */ 551 if (ssd130x->page_address_mode) 552 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 553 SSD130X_SET_ADDRESS_MODE_PAGE); 554 555 /* Switch to horizontal addressing mode */ 556 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 557 SSD130X_SET_ADDRESS_MODE_HORIZONTAL); 558 } 559 560 static int ssd132x_init(struct ssd130x_device *ssd130x) 561 { 562 const u8 cmds[] = { 563 2, SSD13XX_CONTRAST, 0x80, 564 3, SSD132X_SET_COL_RANGE, 0x00, ssd130x->width / SSD132X_SEGMENT_WIDTH - 1, 565 3, SSD132X_SET_ROW_RANGE, 0x00, ssd130x->height - 1, 566 /* 567 * Horizontal Address Increment 568 * Re-map for Column Address, Nibble and COM 569 * COM Split Odd Even 570 */ 571 2, SSD13XX_SET_SEG_REMAP, 0x53, 572 2, SSD132X_SET_DISPLAY_START, 0x00, 573 2, SSD132X_SET_DISPLAY_OFFSET, 0x00, 574 1, SSD132X_SET_DISPLAY_NORMAL, 575 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 576 2, SSD132X_SET_PHASE_LENGTH, 0x55, 577 1, SSD132X_SELECT_DEFAULT_TABLE, 578 2, SSD132X_SET_CLOCK_FREQ, 0x01, 579 2, SSD132X_SET_FUNCTION_SELECT_A, 0x1, 580 2, SSD132X_SET_PRECHARGE_PERIOD, 0x01, 581 2, SSD132X_SET_PRECHARGE_VOLTAGE, 0x08, 582 2, SSD130X_SET_VCOMH_VOLTAGE, 0x07, 583 /* Enable second pre-charge and internal VSL */ 584 2, SSD132X_SET_FUNCTION_SELECT_B, 0x62, 585 0, 586 }; 587 588 return ssd130x_run_cmd_seq(ssd130x, cmds); 589 } 590 591 /* Scale a channel's white-balance calibration contrast by the requested brightness */ 592 static u8 ssd130x_scale_contrast(u8 calibration, u32 brightness) 593 { 594 return DIV_ROUND_CLOSEST(calibration * brightness, MAX_CONTRAST); 595 } 596 597 /* 598 * The A/B/C contrast channels drive sub-pixels whose OLED materials differ 599 * in luminous efficiency, so the per-channel values are a white-balance 600 * calibration. Scale them by the requested brightness instead of 601 * overwriting them, to keep the white point while dimming. 602 */ 603 static int ssd133x_set_contrast(struct ssd130x_device *ssd130x, u32 brightness) 604 { 605 const u8 cmds[] = { 606 2, SSD133X_CONTRAST_A, 607 ssd130x_scale_contrast(SSD133X_DEFAULT_CONTRAST_A, brightness), 608 2, SSD133X_CONTRAST_B, 609 ssd130x_scale_contrast(SSD133X_DEFAULT_CONTRAST_B, brightness), 610 2, SSD133X_CONTRAST_C, 611 ssd130x_scale_contrast(SSD133X_DEFAULT_CONTRAST_C, brightness), 612 0, 613 }; 614 615 return ssd130x_run_cmd_seq(ssd130x, cmds); 616 } 617 618 static int ssd133x_init(struct ssd130x_device *ssd130x) 619 { 620 int ret; 621 const u8 cmds[] = { 622 2, SSD133X_SET_MASTER_CURRENT, 0x06, 623 3, SSD133X_SET_COL_RANGE, 0x00, ssd130x->width - 1, 624 3, SSD133X_SET_ROW_RANGE, 0x00, ssd130x->height - 1, 625 /* 626 * Horizontal Address Increment 627 * Normal order SA,SB,SC (e.g. RGB) 628 * COM Split Odd Even 629 * 256 color format 630 */ 631 2, SSD13XX_SET_SEG_REMAP, 0x20, 632 2, SSD133X_SET_DISPLAY_START, 0x00, 633 2, SSD133X_SET_DISPLAY_OFFSET, 0x00, 634 1, SSD133X_SET_DISPLAY_NORMAL, 635 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1, 636 2, SSD133X_SET_MASTER_CONFIG, 0x8e, 637 2, SSD133X_POWER_SAVE_MODE, 0x0b, 638 2, SSD133X_PHASES_PERIOD, 0x31, 639 2, SSD133X_SET_CLOCK_FREQ, 0xf0, 640 2, SSD132X_SET_PRECHARGE_A, 0x64, 641 2, SSD132X_SET_PRECHARGE_B, 0x78, 642 2, SSD132X_SET_PRECHARGE_C, 0x64, 643 2, SSD133X_SET_PRECHARGE_VOLTAGE, 0x3a, 644 2, SSD133X_SET_VCOMH_VOLTAGE, 0x3e, 645 0, 646 }; 647 648 ret = ssd133x_set_contrast(ssd130x, ssd130x->contrast); 649 if (ret < 0) 650 return ret; 651 652 return ssd130x_run_cmd_seq(ssd130x, cmds); 653 } 654 655 static int ssd130x_update_rect(struct ssd130x_device *ssd130x, 656 struct drm_rect *rect, u8 *buf, 657 u8 *data_array) 658 { 659 unsigned int x = rect->x1; 660 unsigned int y = rect->y1; 661 unsigned int width = drm_rect_width(rect); 662 unsigned int height = drm_rect_height(rect); 663 unsigned int line_length = DIV_ROUND_UP(width, 8); 664 unsigned int page_height = SSD130X_PAGE_HEIGHT; 665 u8 page_start = ssd130x->page_offset + y / page_height; 666 unsigned int pages = DIV_ROUND_UP(height, page_height); 667 struct drm_device *drm = &ssd130x->drm; 668 u32 array_idx = 0; 669 int ret, i, j, k; 670 671 drm_WARN_ONCE(drm, y % page_height != 0, "y must be aligned to screen page\n"); 672 673 /* 674 * The screen is divided in pages, each having a height of 8 675 * pixels, and the width of the screen. When sending a byte of 676 * data to the controller, it gives the 8 bits for the current 677 * column. I.e, the first byte are the 8 bits of the first 678 * column, then the 8 bits for the second column, etc. 679 * 680 * 681 * Representation of the screen, assuming it is 5 bits 682 * wide. Each letter-number combination is a bit that controls 683 * one pixel. 684 * 685 * A0 A1 A2 A3 A4 686 * B0 B1 B2 B3 B4 687 * C0 C1 C2 C3 C4 688 * D0 D1 D2 D3 D4 689 * E0 E1 E2 E3 E4 690 * F0 F1 F2 F3 F4 691 * G0 G1 G2 G3 G4 692 * H0 H1 H2 H3 H4 693 * 694 * If you want to update this screen, you need to send 5 bytes: 695 * (1) A0 B0 C0 D0 E0 F0 G0 H0 696 * (2) A1 B1 C1 D1 E1 F1 G1 H1 697 * (3) A2 B2 C2 D2 E2 F2 G2 H2 698 * (4) A3 B3 C3 D3 E3 F3 G3 H3 699 * (5) A4 B4 C4 D4 E4 F4 G4 H4 700 */ 701 702 if (!ssd130x->page_address_mode) { 703 /* Set address range for horizontal addressing mode */ 704 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width); 705 if (ret < 0) 706 return ret; 707 708 ret = ssd130x_set_page_range(ssd130x, page_start, pages); 709 if (ret < 0) 710 return ret; 711 } 712 713 for (i = 0; i < pages; i++) { 714 int m = page_height; 715 716 /* Last page may be partial */ 717 if (page_height * (y / page_height + i + 1) > ssd130x->height) 718 m = ssd130x->height % page_height; 719 720 for (j = 0; j < width; j++) { 721 u8 data = 0; 722 723 for (k = 0; k < m; k++) { 724 u32 idx = (page_height * i + k) * line_length + j / 8; 725 u8 byte = buf[idx]; 726 u8 bit = (byte >> (j % 8)) & 1; 727 728 data |= bit << k; 729 } 730 data_array[array_idx++] = data; 731 } 732 733 /* 734 * In page addressing mode, the start address needs to be reset, 735 * and each page then needs to be written out separately. 736 */ 737 if (ssd130x->page_address_mode) { 738 ret = ssd130x_set_page_pos(ssd130x, 739 page_start + i, 740 ssd130x->col_offset + x); 741 if (ret < 0) 742 return ret; 743 744 ret = ssd130x_write_data(ssd130x, data_array, width); 745 if (ret < 0) 746 return ret; 747 748 array_idx = 0; 749 } 750 } 751 752 /* Write out update in one go if we aren't using page addressing mode */ 753 if (!ssd130x->page_address_mode) 754 ret = ssd130x_write_data(ssd130x, data_array, width * pages); 755 756 return ret; 757 } 758 759 static int ssd132x_update_rect(struct ssd130x_device *ssd130x, 760 struct drm_rect *rect, u8 *buf, 761 u8 *data_array) 762 { 763 unsigned int segment_width = SSD132X_SEGMENT_WIDTH; 764 unsigned int col = rect->x1 / segment_width; 765 unsigned int row = rect->y1; 766 unsigned int width = drm_rect_width(rect); 767 unsigned int height = drm_rect_height(rect); 768 unsigned int columns = DIV_ROUND_UP(width, segment_width); 769 unsigned int rows = height; 770 struct drm_device *drm = &ssd130x->drm; 771 u32 array_idx = 0; 772 unsigned int i, j; 773 int ret; 774 775 drm_WARN_ONCE(drm, rect->x1 % segment_width != 0, "x must be aligned to screen segment\n"); 776 777 /* 778 * The screen is divided in Segment and Common outputs, where 779 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 780 * the columns. 781 * 782 * Each Segment has a 4-bit pixel and each Common output has a 783 * row of pixels. When using the (default) horizontal address 784 * increment mode, each byte of data sent to the controller has 785 * two Segments (e.g: SEG0 and SEG1) that are stored in the lower 786 * and higher nibbles of a single byte representing one column. 787 * That is, the first byte are SEG0 (D0[3:0]) and SEG1 (D0[7:4]), 788 * the second byte are SEG2 (D1[3:0]) and SEG3 (D1[7:4]) and so on. 789 */ 790 791 /* Set column start and end */ 792 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, col, col + columns - 1); 793 if (ret < 0) 794 return ret; 795 796 /* Set row start and end */ 797 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, row, row + rows - 1); 798 if (ret < 0) 799 return ret; 800 801 for (i = 0; i < height; i++) { 802 /* Process pair of pixels and combine them into a single byte */ 803 for (j = 0; j < width; j += segment_width) { 804 u8 n1 = buf[i * width + j]; 805 u8 n2 = buf[i * width + j + 1]; 806 807 data_array[array_idx++] = (n2 & 0xf0) | (n1 >> 4); 808 } 809 } 810 811 /* Write out update in one go since horizontal addressing mode is used */ 812 ret = ssd130x_write_data(ssd130x, data_array, columns * rows); 813 814 return ret; 815 } 816 817 static int ssd133x_update_rect(struct ssd130x_device *ssd130x, 818 struct drm_rect *rect, u8 *data_array, 819 unsigned int pitch) 820 { 821 unsigned int x = rect->x1; 822 unsigned int y = rect->y1; 823 unsigned int columns = drm_rect_width(rect); 824 unsigned int rows = drm_rect_height(rect); 825 int ret; 826 827 /* 828 * The screen is divided in Segment and Common outputs, where 829 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 830 * the columns. 831 * 832 * Each Segment has a 8-bit pixel and each Common output has a 833 * row of pixels. When using the (default) horizontal address 834 * increment mode, each byte of data sent to the controller has 835 * a Segment (e.g: SEG0). 836 * 837 * When using the 256 color depth format, each pixel contains 3 838 * sub-pixels for color A, B and C. These have 3 bit, 3 bit and 839 * 2 bits respectively. 840 */ 841 842 /* Set column start and end */ 843 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, x, x + columns - 1); 844 if (ret < 0) 845 return ret; 846 847 /* Set row start and end */ 848 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, y, y + rows - 1); 849 if (ret < 0) 850 return ret; 851 852 /* Write out update in one go since horizontal addressing mode is used */ 853 ret = ssd130x_write_data(ssd130x, data_array, pitch * rows); 854 855 return ret; 856 } 857 858 static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 859 { 860 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 861 unsigned int width = ssd130x->width; 862 int ret, i; 863 864 if (!ssd130x->page_address_mode) { 865 memset(data_array, 0, width * pages); 866 867 /* Set address range for horizontal addressing mode */ 868 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset, width); 869 if (ret < 0) 870 return; 871 872 ret = ssd130x_set_page_range(ssd130x, ssd130x->page_offset, pages); 873 if (ret < 0) 874 return; 875 876 /* Write out update in one go if we aren't using page addressing mode */ 877 ssd130x_write_data(ssd130x, data_array, width * pages); 878 } else { 879 /* 880 * In page addressing mode, the start address needs to be reset, 881 * and each page then needs to be written out separately. 882 */ 883 memset(data_array, 0, width); 884 885 for (i = 0; i < pages; i++) { 886 ret = ssd130x_set_page_pos(ssd130x, 887 ssd130x->page_offset + i, 888 ssd130x->col_offset); 889 if (ret < 0) 890 return; 891 892 ret = ssd130x_write_data(ssd130x, data_array, width); 893 if (ret < 0) 894 return; 895 } 896 } 897 } 898 899 static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 900 { 901 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 902 unsigned int height = ssd130x->height; 903 904 memset(data_array, 0, columns * height); 905 906 /* Write out update in one go since horizontal addressing mode is used */ 907 ssd130x_write_data(ssd130x, data_array, columns * height); 908 } 909 910 static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 911 { 912 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 913 unsigned int pitch; 914 915 if (!fi) 916 return; 917 918 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 919 920 memset(data_array, 0, pitch * ssd130x->height); 921 922 /* Write out update in one go since horizontal addressing mode is used */ 923 ssd130x_write_data(ssd130x, data_array, pitch * ssd130x->height); 924 } 925 926 static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb, 927 const struct iosys_map *vmap, 928 struct drm_rect *rect, 929 u8 *buf, u8 *data_array, 930 struct drm_format_conv_state *fmtcnv_state) 931 { 932 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 933 struct iosys_map dst; 934 unsigned int dst_pitch; 935 936 /* Align y to display page boundaries */ 937 rect->y1 = round_down(rect->y1, SSD130X_PAGE_HEIGHT); 938 rect->y2 = min_t(unsigned int, round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height); 939 940 dst_pitch = DIV_ROUND_UP(drm_rect_width(rect), 8); 941 942 iosys_map_set_vaddr(&dst, buf); 943 drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 944 945 ssd130x_update_rect(ssd130x, rect, buf, data_array); 946 947 return 0; 948 } 949 950 static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb, 951 const struct iosys_map *vmap, 952 struct drm_rect *rect, u8 *buf, 953 u8 *data_array, 954 struct drm_format_conv_state *fmtcnv_state) 955 { 956 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 957 unsigned int dst_pitch; 958 struct iosys_map dst; 959 960 /* Align x to display segment boundaries */ 961 rect->x1 = round_down(rect->x1, SSD132X_SEGMENT_WIDTH); 962 rect->x2 = min_t(unsigned int, round_up(rect->x2, SSD132X_SEGMENT_WIDTH), 963 ssd130x->width); 964 965 dst_pitch = drm_rect_width(rect); 966 967 iosys_map_set_vaddr(&dst, buf); 968 drm_fb_xrgb8888_to_gray8(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 969 970 ssd132x_update_rect(ssd130x, rect, buf, data_array); 971 972 return 0; 973 } 974 975 static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb, 976 const struct iosys_map *vmap, 977 struct drm_rect *rect, u8 *data_array, 978 struct drm_format_conv_state *fmtcnv_state) 979 { 980 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 981 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 982 unsigned int dst_pitch; 983 struct iosys_map dst; 984 985 if (!fi) 986 return -EINVAL; 987 988 dst_pitch = drm_format_info_min_pitch(fi, 0, drm_rect_width(rect)); 989 990 iosys_map_set_vaddr(&dst, data_array); 991 drm_fb_xrgb8888_to_rgb332(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 992 993 ssd133x_update_rect(ssd130x, rect, data_array, dst_pitch); 994 995 return 0; 996 } 997 998 static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane, 999 struct drm_atomic_commit *state) 1000 { 1001 struct drm_device *drm = plane->dev; 1002 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1003 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1004 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 1005 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 1006 struct drm_crtc *crtc = plane_state->crtc; 1007 struct drm_crtc_state *crtc_state = NULL; 1008 const struct drm_format_info *fi; 1009 unsigned int pitch; 1010 int ret; 1011 1012 if (crtc) 1013 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1014 1015 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1016 DRM_PLANE_NO_SCALING, 1017 DRM_PLANE_NO_SCALING, 1018 false, false); 1019 if (ret) 1020 return ret; 1021 else if (!plane_state->visible) 1022 return 0; 1023 1024 fi = drm_format_info(DRM_FORMAT_R1); 1025 if (!fi) 1026 return -EINVAL; 1027 1028 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1029 1030 if (plane_state->fb->format != fi) { 1031 void *buf; 1032 1033 /* format conversion necessary; reserve buffer */ 1034 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1035 pitch, GFP_KERNEL); 1036 if (!buf) 1037 return -ENOMEM; 1038 } 1039 1040 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1041 if (!ssd130x_state->buffer) 1042 return -ENOMEM; 1043 1044 return 0; 1045 } 1046 1047 static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane, 1048 struct drm_atomic_commit *state) 1049 { 1050 struct drm_device *drm = plane->dev; 1051 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1052 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1053 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 1054 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 1055 struct drm_crtc *crtc = plane_state->crtc; 1056 struct drm_crtc_state *crtc_state = NULL; 1057 const struct drm_format_info *fi; 1058 unsigned int pitch; 1059 int ret; 1060 1061 if (crtc) 1062 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1063 1064 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1065 DRM_PLANE_NO_SCALING, 1066 DRM_PLANE_NO_SCALING, 1067 false, false); 1068 if (ret) 1069 return ret; 1070 else if (!plane_state->visible) 1071 return 0; 1072 1073 fi = drm_format_info(DRM_FORMAT_R8); 1074 if (!fi) 1075 return -EINVAL; 1076 1077 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1078 1079 if (plane_state->fb->format != fi) { 1080 void *buf; 1081 1082 /* format conversion necessary; reserve buffer */ 1083 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1084 pitch, GFP_KERNEL); 1085 if (!buf) 1086 return -ENOMEM; 1087 } 1088 1089 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1090 if (!ssd130x_state->buffer) 1091 return -ENOMEM; 1092 1093 return 0; 1094 } 1095 1096 static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane, 1097 struct drm_atomic_commit *state) 1098 { 1099 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1100 struct drm_crtc *crtc = plane_state->crtc; 1101 struct drm_crtc_state *crtc_state = NULL; 1102 int ret; 1103 1104 if (crtc) 1105 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1106 1107 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1108 DRM_PLANE_NO_SCALING, 1109 DRM_PLANE_NO_SCALING, 1110 false, false); 1111 if (ret) 1112 return ret; 1113 else if (!plane_state->visible) 1114 return 0; 1115 1116 return 0; 1117 } 1118 1119 static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane, 1120 struct drm_atomic_commit *state) 1121 { 1122 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1123 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1124 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1125 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1126 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1127 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1128 struct drm_framebuffer *fb = plane_state->fb; 1129 struct drm_atomic_helper_damage_iter iter; 1130 struct drm_device *drm = plane->dev; 1131 struct drm_rect dst_clip; 1132 struct drm_rect damage; 1133 int idx; 1134 1135 if (!drm_dev_enter(drm, &idx)) 1136 return; 1137 1138 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1139 goto out_drm_dev_exit; 1140 1141 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1142 drm_atomic_for_each_plane_damage(&iter, &damage) { 1143 dst_clip = plane_state->dst; 1144 1145 if (!drm_rect_intersect(&dst_clip, &damage)) 1146 continue; 1147 1148 ssd130x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1149 ssd130x_plane_state->buffer, 1150 ssd130x_crtc_state->data_array, 1151 &shadow_plane_state->fmtcnv_state); 1152 } 1153 1154 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1155 1156 out_drm_dev_exit: 1157 drm_dev_exit(idx); 1158 } 1159 1160 static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane, 1161 struct drm_atomic_commit *state) 1162 { 1163 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1164 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1165 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1166 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1167 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1168 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1169 struct drm_framebuffer *fb = plane_state->fb; 1170 struct drm_atomic_helper_damage_iter iter; 1171 struct drm_device *drm = plane->dev; 1172 struct drm_rect dst_clip; 1173 struct drm_rect damage; 1174 int idx; 1175 1176 if (!drm_dev_enter(drm, &idx)) 1177 return; 1178 1179 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1180 goto out_drm_dev_exit; 1181 1182 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1183 drm_atomic_for_each_plane_damage(&iter, &damage) { 1184 dst_clip = plane_state->dst; 1185 1186 if (!drm_rect_intersect(&dst_clip, &damage)) 1187 continue; 1188 1189 ssd132x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1190 ssd130x_plane_state->buffer, 1191 ssd130x_crtc_state->data_array, 1192 &shadow_plane_state->fmtcnv_state); 1193 } 1194 1195 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1196 1197 out_drm_dev_exit: 1198 drm_dev_exit(idx); 1199 } 1200 1201 static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane, 1202 struct drm_atomic_commit *state) 1203 { 1204 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1205 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1206 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1207 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1208 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1209 struct drm_framebuffer *fb = plane_state->fb; 1210 struct drm_atomic_helper_damage_iter iter; 1211 struct drm_device *drm = plane->dev; 1212 struct drm_rect dst_clip; 1213 struct drm_rect damage; 1214 int idx; 1215 1216 if (!drm_dev_enter(drm, &idx)) 1217 return; 1218 1219 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1220 goto out_drm_dev_exit; 1221 1222 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1223 drm_atomic_for_each_plane_damage(&iter, &damage) { 1224 dst_clip = plane_state->dst; 1225 1226 if (!drm_rect_intersect(&dst_clip, &damage)) 1227 continue; 1228 1229 ssd133x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1230 ssd130x_crtc_state->data_array, 1231 &shadow_plane_state->fmtcnv_state); 1232 } 1233 1234 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1235 1236 out_drm_dev_exit: 1237 drm_dev_exit(idx); 1238 } 1239 1240 static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane, 1241 struct drm_atomic_commit *state) 1242 { 1243 struct drm_device *drm = plane->dev; 1244 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1245 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1246 struct drm_crtc_state *crtc_state; 1247 struct ssd130x_crtc_state *ssd130x_crtc_state; 1248 int idx; 1249 1250 if (!plane_state->crtc) 1251 return; 1252 1253 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1254 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1255 1256 if (!drm_dev_enter(drm, &idx)) 1257 return; 1258 1259 ssd130x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1260 1261 drm_dev_exit(idx); 1262 } 1263 1264 static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane, 1265 struct drm_atomic_commit *state) 1266 { 1267 struct drm_device *drm = plane->dev; 1268 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1269 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1270 struct drm_crtc_state *crtc_state; 1271 struct ssd130x_crtc_state *ssd130x_crtc_state; 1272 int idx; 1273 1274 if (!plane_state->crtc) 1275 return; 1276 1277 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1278 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1279 1280 if (!drm_dev_enter(drm, &idx)) 1281 return; 1282 1283 ssd132x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1284 1285 drm_dev_exit(idx); 1286 } 1287 1288 static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane, 1289 struct drm_atomic_commit *state) 1290 { 1291 struct drm_device *drm = plane->dev; 1292 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1293 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1294 struct drm_crtc_state *crtc_state; 1295 struct ssd130x_crtc_state *ssd130x_crtc_state; 1296 int idx; 1297 1298 if (!plane_state->crtc) 1299 return; 1300 1301 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1302 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1303 1304 if (!drm_dev_enter(drm, &idx)) 1305 return; 1306 1307 ssd133x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1308 1309 drm_dev_exit(idx); 1310 } 1311 1312 /* Called during init to allocate the plane's atomic state. */ 1313 static void ssd130x_primary_plane_reset(struct drm_plane *plane) 1314 { 1315 struct ssd130x_plane_state *ssd130x_state; 1316 1317 drm_WARN_ON_ONCE(plane->dev, plane->state); 1318 1319 ssd130x_state = kzalloc_obj(*ssd130x_state); 1320 if (!ssd130x_state) 1321 return; 1322 1323 __drm_gem_reset_shadow_plane(plane, &ssd130x_state->base); 1324 } 1325 1326 static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane) 1327 { 1328 struct drm_shadow_plane_state *new_shadow_plane_state; 1329 struct ssd130x_plane_state *old_ssd130x_state; 1330 struct ssd130x_plane_state *ssd130x_state; 1331 1332 if (drm_WARN_ON_ONCE(plane->dev, !plane->state)) 1333 return NULL; 1334 1335 old_ssd130x_state = to_ssd130x_plane_state(plane->state); 1336 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1337 if (!ssd130x_state) 1338 return NULL; 1339 1340 /* The buffer is not duplicated and is allocated in .atomic_check */ 1341 ssd130x_state->buffer = NULL; 1342 1343 new_shadow_plane_state = &ssd130x_state->base; 1344 1345 __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state); 1346 1347 return &new_shadow_plane_state->base; 1348 } 1349 1350 static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane, 1351 struct drm_plane_state *state) 1352 { 1353 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state); 1354 1355 kfree(ssd130x_state->buffer); 1356 1357 __drm_gem_destroy_shadow_plane_state(&ssd130x_state->base); 1358 1359 kfree(ssd130x_state); 1360 } 1361 1362 static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = { 1363 [SSD130X_FAMILY] = { 1364 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1365 .atomic_check = ssd130x_primary_plane_atomic_check, 1366 .atomic_update = ssd130x_primary_plane_atomic_update, 1367 .atomic_disable = ssd130x_primary_plane_atomic_disable, 1368 }, 1369 [SSD132X_FAMILY] = { 1370 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1371 .atomic_check = ssd132x_primary_plane_atomic_check, 1372 .atomic_update = ssd132x_primary_plane_atomic_update, 1373 .atomic_disable = ssd132x_primary_plane_atomic_disable, 1374 }, 1375 [SSD133X_FAMILY] = { 1376 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1377 .atomic_check = ssd133x_primary_plane_atomic_check, 1378 .atomic_update = ssd133x_primary_plane_atomic_update, 1379 .atomic_disable = ssd133x_primary_plane_atomic_disable, 1380 } 1381 }; 1382 1383 static const struct drm_plane_funcs ssd130x_primary_plane_funcs = { 1384 .update_plane = drm_atomic_helper_update_plane, 1385 .disable_plane = drm_atomic_helper_disable_plane, 1386 .reset = ssd130x_primary_plane_reset, 1387 .atomic_duplicate_state = ssd130x_primary_plane_duplicate_state, 1388 .atomic_destroy_state = ssd130x_primary_plane_destroy_state, 1389 .destroy = drm_plane_cleanup, 1390 }; 1391 1392 static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc, 1393 const struct drm_display_mode *mode) 1394 { 1395 struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev); 1396 1397 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &ssd130x->mode); 1398 } 1399 1400 static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc, 1401 struct drm_atomic_commit *state) 1402 { 1403 struct drm_device *drm = crtc->dev; 1404 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1405 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1406 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1407 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 1408 int ret; 1409 1410 ret = drm_crtc_helper_atomic_check(crtc, state); 1411 if (ret) 1412 return ret; 1413 1414 ssd130x_state->data_array = kmalloc_array(ssd130x->width, pages, GFP_KERNEL); 1415 if (!ssd130x_state->data_array) 1416 return -ENOMEM; 1417 1418 return 0; 1419 } 1420 1421 static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc, 1422 struct drm_atomic_commit *state) 1423 { 1424 struct drm_device *drm = crtc->dev; 1425 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1426 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1427 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1428 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 1429 int ret; 1430 1431 ret = drm_crtc_helper_atomic_check(crtc, state); 1432 if (ret) 1433 return ret; 1434 1435 ssd130x_state->data_array = kmalloc_array(columns, ssd130x->height, GFP_KERNEL); 1436 if (!ssd130x_state->data_array) 1437 return -ENOMEM; 1438 1439 return 0; 1440 } 1441 1442 static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc, 1443 struct drm_atomic_commit *state) 1444 { 1445 struct drm_device *drm = crtc->dev; 1446 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1447 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1448 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1449 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 1450 unsigned int pitch; 1451 int ret; 1452 1453 if (!fi) 1454 return -EINVAL; 1455 1456 ret = drm_crtc_helper_atomic_check(crtc, state); 1457 if (ret) 1458 return ret; 1459 1460 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1461 1462 ssd130x_state->data_array = kmalloc_array(pitch, ssd130x->height, GFP_KERNEL); 1463 if (!ssd130x_state->data_array) 1464 return -ENOMEM; 1465 1466 return 0; 1467 } 1468 1469 /* Called during init to allocate the CRTC's atomic state. */ 1470 static void ssd130x_crtc_reset(struct drm_crtc *crtc) 1471 { 1472 struct ssd130x_crtc_state *ssd130x_state; 1473 1474 drm_WARN_ON_ONCE(crtc->dev, crtc->state); 1475 1476 ssd130x_state = kzalloc_obj(*ssd130x_state); 1477 if (!ssd130x_state) 1478 return; 1479 1480 __drm_atomic_helper_crtc_reset(crtc, &ssd130x_state->base); 1481 } 1482 1483 static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc) 1484 { 1485 struct ssd130x_crtc_state *old_ssd130x_state; 1486 struct ssd130x_crtc_state *ssd130x_state; 1487 1488 if (drm_WARN_ON_ONCE(crtc->dev, !crtc->state)) 1489 return NULL; 1490 1491 old_ssd130x_state = to_ssd130x_crtc_state(crtc->state); 1492 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1493 if (!ssd130x_state) 1494 return NULL; 1495 1496 /* The buffer is not duplicated and is allocated in .atomic_check */ 1497 ssd130x_state->data_array = NULL; 1498 1499 __drm_atomic_helper_crtc_duplicate_state(crtc, &ssd130x_state->base); 1500 1501 return &ssd130x_state->base; 1502 } 1503 1504 static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc, 1505 struct drm_crtc_state *state) 1506 { 1507 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state); 1508 1509 kfree(ssd130x_state->data_array); 1510 1511 __drm_atomic_helper_crtc_destroy_state(state); 1512 1513 kfree(ssd130x_state); 1514 } 1515 1516 /* 1517 * The CRTC is always enabled. Screen updates are performed by 1518 * the primary plane's atomic_update function. Disabling clears 1519 * the screen in the primary plane's atomic_disable function. 1520 */ 1521 static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = { 1522 [SSD130X_FAMILY] = { 1523 .mode_valid = ssd130x_crtc_mode_valid, 1524 .atomic_check = ssd130x_crtc_atomic_check, 1525 }, 1526 [SSD132X_FAMILY] = { 1527 .mode_valid = ssd130x_crtc_mode_valid, 1528 .atomic_check = ssd132x_crtc_atomic_check, 1529 }, 1530 [SSD133X_FAMILY] = { 1531 .mode_valid = ssd130x_crtc_mode_valid, 1532 .atomic_check = ssd133x_crtc_atomic_check, 1533 }, 1534 }; 1535 1536 static const struct drm_crtc_funcs ssd130x_crtc_funcs = { 1537 .reset = ssd130x_crtc_reset, 1538 .destroy = drm_crtc_cleanup, 1539 .set_config = drm_atomic_helper_set_config, 1540 .page_flip = drm_atomic_helper_page_flip, 1541 .atomic_duplicate_state = ssd130x_crtc_duplicate_state, 1542 .atomic_destroy_state = ssd130x_crtc_destroy_state, 1543 }; 1544 1545 static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder, 1546 struct drm_atomic_commit *state) 1547 { 1548 struct drm_device *drm = encoder->dev; 1549 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1550 int ret; 1551 1552 ret = ssd130x_power_on(ssd130x); 1553 if (ret) 1554 return; 1555 1556 ret = ssd130x_init(ssd130x); 1557 if (ret) 1558 goto power_off; 1559 1560 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1561 1562 backlight_enable(ssd130x->bl_dev); 1563 1564 return; 1565 1566 power_off: 1567 ssd130x_power_off(ssd130x); 1568 return; 1569 } 1570 1571 static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder, 1572 struct drm_atomic_commit *state) 1573 { 1574 struct drm_device *drm = encoder->dev; 1575 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1576 int ret; 1577 1578 ret = ssd130x_power_on(ssd130x); 1579 if (ret) 1580 return; 1581 1582 ret = ssd132x_init(ssd130x); 1583 if (ret) 1584 goto power_off; 1585 1586 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1587 1588 backlight_enable(ssd130x->bl_dev); 1589 1590 return; 1591 1592 power_off: 1593 ssd130x_power_off(ssd130x); 1594 } 1595 1596 static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder, 1597 struct drm_atomic_commit *state) 1598 { 1599 struct drm_device *drm = encoder->dev; 1600 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1601 int ret; 1602 1603 ret = ssd130x_power_on(ssd130x); 1604 if (ret) 1605 return; 1606 1607 ret = ssd133x_init(ssd130x); 1608 if (ret) 1609 goto power_off; 1610 1611 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1612 1613 backlight_enable(ssd130x->bl_dev); 1614 1615 return; 1616 1617 power_off: 1618 ssd130x_power_off(ssd130x); 1619 } 1620 1621 static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder, 1622 struct drm_atomic_commit *state) 1623 { 1624 struct drm_device *drm = encoder->dev; 1625 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1626 1627 backlight_disable(ssd130x->bl_dev); 1628 1629 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_OFF); 1630 1631 ssd130x_power_off(ssd130x); 1632 } 1633 1634 static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = { 1635 [SSD130X_FAMILY] = { 1636 .atomic_enable = ssd130x_encoder_atomic_enable, 1637 .atomic_disable = ssd130x_encoder_atomic_disable, 1638 }, 1639 [SSD132X_FAMILY] = { 1640 .atomic_enable = ssd132x_encoder_atomic_enable, 1641 .atomic_disable = ssd130x_encoder_atomic_disable, 1642 }, 1643 [SSD133X_FAMILY] = { 1644 .atomic_enable = ssd133x_encoder_atomic_enable, 1645 .atomic_disable = ssd130x_encoder_atomic_disable, 1646 } 1647 }; 1648 1649 static const struct drm_encoder_funcs ssd130x_encoder_funcs = { 1650 .destroy = drm_encoder_cleanup, 1651 }; 1652 1653 static int ssd130x_connector_get_modes(struct drm_connector *connector) 1654 { 1655 struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev); 1656 1657 return drm_connector_helper_get_modes_fixed(connector, &ssd130x->mode); 1658 } 1659 1660 static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = { 1661 .get_modes = ssd130x_connector_get_modes, 1662 }; 1663 1664 static const struct drm_connector_funcs ssd130x_connector_funcs = { 1665 .reset = drm_atomic_helper_connector_reset, 1666 .fill_modes = drm_helper_probe_single_connector_modes, 1667 .destroy = drm_connector_cleanup, 1668 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1669 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1670 }; 1671 1672 static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = { 1673 .fb_create = drm_gem_fb_create_with_dirty, 1674 .atomic_check = drm_atomic_helper_check, 1675 .atomic_commit = drm_atomic_helper_commit, 1676 }; 1677 1678 static const uint32_t ssd130x_formats[] = { 1679 DRM_FORMAT_XRGB8888, 1680 }; 1681 1682 DEFINE_DRM_GEM_FOPS(ssd130x_fops); 1683 1684 static const struct drm_driver ssd130x_drm_driver = { 1685 DRM_GEM_SHMEM_DRIVER_OPS, 1686 DRM_FBDEV_SHMEM_DRIVER_OPS, 1687 .name = DRIVER_NAME, 1688 .desc = DRIVER_DESC, 1689 .major = DRIVER_MAJOR, 1690 .minor = DRIVER_MINOR, 1691 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1692 .fops = &ssd130x_fops, 1693 }; 1694 1695 static int ssd130x_update_bl(struct backlight_device *bdev) 1696 { 1697 struct ssd130x_device *ssd130x = bl_get_data(bdev); 1698 int brightness = backlight_get_brightness(bdev); 1699 int ret; 1700 1701 ssd130x->contrast = brightness; 1702 1703 ret = ssd130x_write_cmd(ssd130x, 1, SSD13XX_CONTRAST); 1704 if (ret < 0) 1705 return ret; 1706 1707 ret = ssd130x_write_cmd(ssd130x, 1, ssd130x->contrast); 1708 if (ret < 0) 1709 return ret; 1710 1711 return 0; 1712 } 1713 1714 static int ssd133x_update_bl(struct backlight_device *bdev) 1715 { 1716 struct ssd130x_device *ssd130x = bl_get_data(bdev); 1717 1718 ssd130x->contrast = backlight_get_brightness(bdev); 1719 1720 return ssd133x_set_contrast(ssd130x, ssd130x->contrast); 1721 } 1722 1723 static const struct backlight_ops ssd130xfb_bl_ops[] = { 1724 [SSD130X_FAMILY] = { 1725 .update_status = ssd130x_update_bl, 1726 }, 1727 [SSD132X_FAMILY] = { 1728 .update_status = ssd130x_update_bl, 1729 }, 1730 [SSD133X_FAMILY] = { 1731 .update_status = ssd133x_update_bl, 1732 }, 1733 }; 1734 1735 static void ssd130x_parse_properties(struct ssd130x_device *ssd130x) 1736 { 1737 struct device *dev = ssd130x->dev; 1738 1739 if (device_property_read_u32(dev, "solomon,width", &ssd130x->width)) 1740 ssd130x->width = ssd130x->device_info->default_width; 1741 1742 if (device_property_read_u32(dev, "solomon,height", &ssd130x->height)) 1743 ssd130x->height = ssd130x->device_info->default_height; 1744 1745 if (device_property_read_u32(dev, "solomon,page-offset", &ssd130x->page_offset)) 1746 ssd130x->page_offset = 1; 1747 1748 if (device_property_read_u32(dev, "solomon,col-offset", &ssd130x->col_offset)) 1749 ssd130x->col_offset = 0; 1750 1751 if (device_property_read_u32(dev, "solomon,com-offset", &ssd130x->com_offset)) 1752 ssd130x->com_offset = 0; 1753 1754 if (device_property_read_u32(dev, "solomon,prechargep1", &ssd130x->prechargep1)) 1755 ssd130x->prechargep1 = 2; 1756 1757 if (device_property_read_u32(dev, "solomon,prechargep2", &ssd130x->prechargep2)) 1758 ssd130x->prechargep2 = 2; 1759 1760 if (!device_property_read_u8_array(dev, "solomon,lookup-table", 1761 ssd130x->lookup_table, 1762 ARRAY_SIZE(ssd130x->lookup_table))) 1763 ssd130x->lookup_table_set = 1; 1764 1765 ssd130x->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap"); 1766 ssd130x->com_seq = device_property_read_bool(dev, "solomon,com-seq"); 1767 ssd130x->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap"); 1768 ssd130x->com_invdir = device_property_read_bool(dev, "solomon,com-invdir"); 1769 ssd130x->area_color_enable = 1770 device_property_read_bool(dev, "solomon,area-color-enable"); 1771 ssd130x->low_power = device_property_read_bool(dev, "solomon,low-power"); 1772 1773 ssd130x->contrast = 127; 1774 ssd130x->vcomh = ssd130x->device_info->default_vcomh; 1775 1776 /* Setup display timing */ 1777 if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div)) 1778 ssd130x->dclk_div = ssd130x->device_info->default_dclk_div; 1779 if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq)) 1780 ssd130x->dclk_frq = ssd130x->device_info->default_dclk_frq; 1781 } 1782 1783 static int ssd130x_init_modeset(struct ssd130x_device *ssd130x) 1784 { 1785 enum ssd130x_family_ids family_id = ssd130x->device_info->family_id; 1786 struct drm_display_mode *mode = &ssd130x->mode; 1787 struct device *dev = ssd130x->dev; 1788 struct drm_device *drm = &ssd130x->drm; 1789 unsigned long max_width, max_height; 1790 struct drm_plane *primary_plane; 1791 struct drm_crtc *crtc; 1792 struct drm_encoder *encoder; 1793 struct drm_connector *connector; 1794 int ret; 1795 1796 /* 1797 * Modesetting 1798 */ 1799 1800 ret = drmm_mode_config_init(drm); 1801 if (ret) { 1802 dev_err(dev, "DRM mode config init failed: %d\n", ret); 1803 return ret; 1804 } 1805 1806 mode->type = DRM_MODE_TYPE_DRIVER; 1807 mode->clock = 1; 1808 mode->hdisplay = ssd130x->width; 1809 mode->htotal = ssd130x->width; 1810 mode->hsync_start = ssd130x->width; 1811 mode->hsync_end = ssd130x->width; 1812 mode->vdisplay = ssd130x->height; 1813 mode->vtotal = ssd130x->height; 1814 mode->vsync_start = ssd130x->height; 1815 mode->vsync_end = ssd130x->height; 1816 mode->width_mm = 27; 1817 mode->height_mm = 27; 1818 1819 max_width = max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH); 1820 max_height = max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT); 1821 1822 drm->mode_config.min_width = mode->hdisplay; 1823 drm->mode_config.max_width = max_width; 1824 drm->mode_config.min_height = mode->vdisplay; 1825 drm->mode_config.max_height = max_height; 1826 drm->mode_config.preferred_depth = 24; 1827 drm->mode_config.funcs = &ssd130x_mode_config_funcs; 1828 1829 /* Primary plane */ 1830 1831 primary_plane = &ssd130x->primary_plane; 1832 ret = drm_universal_plane_init(drm, primary_plane, 0, &ssd130x_primary_plane_funcs, 1833 ssd130x_formats, ARRAY_SIZE(ssd130x_formats), 1834 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1835 if (ret) { 1836 dev_err(dev, "DRM primary plane init failed: %d\n", ret); 1837 return ret; 1838 } 1839 1840 drm_plane_helper_add(primary_plane, &ssd130x_primary_plane_helper_funcs[family_id]); 1841 1842 drm_plane_enable_fb_damage_clips(primary_plane); 1843 1844 /* CRTC */ 1845 1846 crtc = &ssd130x->crtc; 1847 ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1848 &ssd130x_crtc_funcs, NULL); 1849 if (ret) { 1850 dev_err(dev, "DRM crtc init failed: %d\n", ret); 1851 return ret; 1852 } 1853 1854 drm_crtc_helper_add(crtc, &ssd130x_crtc_helper_funcs[family_id]); 1855 1856 /* Encoder */ 1857 1858 encoder = &ssd130x->encoder; 1859 ret = drm_encoder_init(drm, encoder, &ssd130x_encoder_funcs, 1860 DRM_MODE_ENCODER_NONE, NULL); 1861 if (ret) { 1862 dev_err(dev, "DRM encoder init failed: %d\n", ret); 1863 return ret; 1864 } 1865 1866 drm_encoder_helper_add(encoder, &ssd130x_encoder_helper_funcs[family_id]); 1867 1868 encoder->possible_crtcs = drm_crtc_mask(crtc); 1869 1870 /* Connector */ 1871 1872 connector = &ssd130x->connector; 1873 ret = drm_connector_init(drm, connector, &ssd130x_connector_funcs, 1874 DRM_MODE_CONNECTOR_Unknown); 1875 if (ret) { 1876 dev_err(dev, "DRM connector init failed: %d\n", ret); 1877 return ret; 1878 } 1879 1880 drm_connector_helper_add(connector, &ssd130x_connector_helper_funcs); 1881 1882 ret = drm_connector_attach_encoder(connector, encoder); 1883 if (ret) { 1884 dev_err(dev, "DRM attach connector to encoder failed: %d\n", ret); 1885 return ret; 1886 } 1887 1888 drm_mode_config_reset(drm); 1889 1890 return 0; 1891 } 1892 1893 static int ssd130x_get_resources(struct ssd130x_device *ssd130x) 1894 { 1895 struct device *dev = ssd130x->dev; 1896 1897 ssd130x->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1898 if (IS_ERR(ssd130x->reset)) 1899 return dev_err_probe(dev, PTR_ERR(ssd130x->reset), 1900 "Failed to get reset gpio\n"); 1901 1902 ssd130x->vcc_reg = devm_regulator_get(dev, "vcc"); 1903 if (IS_ERR(ssd130x->vcc_reg)) 1904 return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg), 1905 "Failed to get VCC regulator\n"); 1906 1907 return 0; 1908 } 1909 1910 struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap) 1911 { 1912 struct ssd130x_device *ssd130x; 1913 struct backlight_device *bl; 1914 struct drm_device *drm; 1915 int ret; 1916 1917 ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver, 1918 struct ssd130x_device, drm); 1919 if (IS_ERR(ssd130x)) 1920 return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x), 1921 "Failed to allocate DRM device\n")); 1922 1923 drm = &ssd130x->drm; 1924 1925 ssd130x->dev = dev; 1926 ssd130x->regmap = regmap; 1927 ssd130x->device_info = device_get_match_data(dev); 1928 1929 if (ssd130x->device_info->page_mode_only) 1930 ssd130x->page_address_mode = 1; 1931 1932 ssd130x_parse_properties(ssd130x); 1933 1934 ret = ssd130x_get_resources(ssd130x); 1935 if (ret) 1936 return ERR_PTR(ret); 1937 1938 bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x, 1939 &ssd130xfb_bl_ops[ssd130x->device_info->family_id], 1940 NULL); 1941 if (IS_ERR(bl)) 1942 return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl), 1943 "Unable to register backlight device\n")); 1944 1945 bl->props.brightness = ssd130x->contrast; 1946 bl->props.max_brightness = MAX_CONTRAST; 1947 ssd130x->bl_dev = bl; 1948 1949 ret = ssd130x_init_modeset(ssd130x); 1950 if (ret) 1951 return ERR_PTR(ret); 1952 1953 ret = drm_dev_register(drm, 0); 1954 if (ret) 1955 return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n")); 1956 1957 drm_client_setup(drm, NULL); 1958 1959 return ssd130x; 1960 } 1961 EXPORT_SYMBOL_GPL(ssd130x_probe); 1962 1963 void ssd130x_remove(struct ssd130x_device *ssd130x) 1964 { 1965 drm_dev_unplug(&ssd130x->drm); 1966 drm_atomic_helper_shutdown(&ssd130x->drm); 1967 } 1968 EXPORT_SYMBOL_GPL(ssd130x_remove); 1969 1970 void ssd130x_shutdown(struct ssd130x_device *ssd130x) 1971 { 1972 drm_atomic_helper_shutdown(&ssd130x->drm); 1973 } 1974 EXPORT_SYMBOL_GPL(ssd130x_shutdown); 1975 1976 MODULE_DESCRIPTION(DRIVER_DESC); 1977 MODULE_AUTHOR("Javier Martinez Canillas <javierm@redhat.com>"); 1978 MODULE_LICENSE("GPL v2"); 1979