1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_plane.h> 15 #include <drm/drm_print.h> 16 17 #include "rockchip_drm_vop.h" 18 #include "rockchip_vop_reg.h" 19 #include "rockchip_drm_drv.h" 20 21 #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ 22 { \ 23 .offset = off, \ 24 .mask = _mask, \ 25 .shift = _shift, \ 26 .write_mask = _write_mask, \ 27 .relaxed = _relaxed, \ 28 } 29 30 #define VOP_REG(off, _mask, _shift) \ 31 _VOP_REG(off, _mask, _shift, false, true) 32 33 #define VOP_REG_SYNC(off, _mask, _shift) \ 34 _VOP_REG(off, _mask, _shift, false, false) 35 36 #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ 37 _VOP_REG(off, _mask, _shift, true, false) 38 39 static const uint32_t formats_win_full[] = { 40 DRM_FORMAT_XRGB8888, 41 DRM_FORMAT_ARGB8888, 42 DRM_FORMAT_XBGR8888, 43 DRM_FORMAT_ABGR8888, 44 DRM_FORMAT_RGB888, 45 DRM_FORMAT_BGR888, 46 DRM_FORMAT_RGB565, 47 DRM_FORMAT_BGR565, 48 DRM_FORMAT_NV12, 49 DRM_FORMAT_NV21, 50 DRM_FORMAT_NV16, 51 DRM_FORMAT_NV61, 52 DRM_FORMAT_NV24, 53 DRM_FORMAT_NV42, 54 }; 55 56 static const uint32_t formats_win_full_10[] = { 57 DRM_FORMAT_XRGB8888, 58 DRM_FORMAT_ARGB8888, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB888, 62 DRM_FORMAT_BGR888, 63 DRM_FORMAT_RGB565, 64 DRM_FORMAT_BGR565, 65 DRM_FORMAT_NV12, 66 DRM_FORMAT_NV21, 67 DRM_FORMAT_NV16, 68 DRM_FORMAT_NV61, 69 DRM_FORMAT_NV24, 70 DRM_FORMAT_NV42, 71 DRM_FORMAT_NV15, 72 DRM_FORMAT_NV20, 73 DRM_FORMAT_NV30, 74 }; 75 76 static const uint64_t format_modifiers_win_full[] = { 77 DRM_FORMAT_MOD_LINEAR, 78 DRM_FORMAT_MOD_INVALID, 79 }; 80 81 static const uint64_t format_modifiers_win_full_afbc[] = { 82 ROCKCHIP_AFBC_MOD, 83 DRM_FORMAT_MOD_LINEAR, 84 DRM_FORMAT_MOD_INVALID, 85 }; 86 87 static const uint32_t formats_win_lite[] = { 88 DRM_FORMAT_XRGB8888, 89 DRM_FORMAT_ARGB8888, 90 DRM_FORMAT_XBGR8888, 91 DRM_FORMAT_ABGR8888, 92 DRM_FORMAT_RGB888, 93 DRM_FORMAT_BGR888, 94 DRM_FORMAT_RGB565, 95 DRM_FORMAT_BGR565, 96 }; 97 98 static const uint64_t format_modifiers_win_lite[] = { 99 DRM_FORMAT_MOD_LINEAR, 100 DRM_FORMAT_MOD_INVALID, 101 }; 102 103 static const struct vop_scl_regs rk3036_win0_scl = { 104 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 105 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 106 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 107 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 108 }; 109 110 static const struct vop_scl_regs rk3036_win1_scl = { 111 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0), 112 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16), 113 }; 114 115 static const struct vop_win_phy rk3036_win0_data = { 116 .scl = &rk3036_win0_scl, 117 .data_formats = formats_win_full, 118 .nformats = ARRAY_SIZE(formats_win_full), 119 .format_modifiers = format_modifiers_win_full, 120 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 121 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 122 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 123 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 124 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 125 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 126 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 127 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 128 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 129 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 130 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 131 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0), 132 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 133 }; 134 135 static const struct vop_win_phy rk3036_win1_data = { 136 .scl = &rk3036_win1_scl, 137 .data_formats = formats_win_lite, 138 .nformats = ARRAY_SIZE(formats_win_lite), 139 .format_modifiers = format_modifiers_win_lite, 140 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 141 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 142 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 143 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), 144 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), 145 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), 146 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), 147 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 148 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), 149 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), 150 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 151 }; 152 153 static const struct vop_win_data rk3036_vop_win_data[] = { 154 { .base = 0x00, .phy = &rk3036_win0_data, 155 .type = DRM_PLANE_TYPE_PRIMARY }, 156 { .base = 0x00, .phy = &rk3036_win1_data, 157 .type = DRM_PLANE_TYPE_CURSOR }, 158 }; 159 160 static const int rk3036_vop_intrs[] = { 161 DSP_HOLD_VALID_INTR, 162 FS_INTR, 163 LINE_FLAG_INTR, 164 BUS_ERROR_INTR, 165 }; 166 167 static const struct vop_intr rk3036_intr = { 168 .intrs = rk3036_vop_intrs, 169 .nintrs = ARRAY_SIZE(rk3036_vop_intrs), 170 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 171 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), 172 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), 173 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), 174 }; 175 176 static const struct vop_modeset rk3036_modeset = { 177 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 178 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 179 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 180 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 181 }; 182 183 static const struct vop_output rk3036_output = { 184 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 185 }; 186 187 static const struct vop_common rk3036_common = { 188 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), 189 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 190 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 191 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27), 192 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11), 193 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10), 194 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), 195 }; 196 197 static const struct vop_data rk3036_vop = { 198 .intr = &rk3036_intr, 199 .common = &rk3036_common, 200 .modeset = &rk3036_modeset, 201 .output = &rk3036_output, 202 .win = rk3036_vop_win_data, 203 .win_size = ARRAY_SIZE(rk3036_vop_win_data), 204 .max_output = { 1920, 1080 }, 205 }; 206 207 static const struct vop_win_phy rk3126_win1_data = { 208 .data_formats = formats_win_lite, 209 .nformats = ARRAY_SIZE(formats_win_lite), 210 .format_modifiers = format_modifiers_win_lite, 211 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 212 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 213 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 214 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 215 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 216 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 217 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 218 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), 219 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), 220 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 221 }; 222 223 static const struct vop_win_data rk3126_vop_win_data[] = { 224 { .base = 0x00, .phy = &rk3036_win0_data, 225 .type = DRM_PLANE_TYPE_PRIMARY }, 226 { .base = 0x00, .phy = &rk3126_win1_data, 227 .type = DRM_PLANE_TYPE_CURSOR }, 228 }; 229 230 static const struct vop_output rk3126_output = { 231 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 232 .hdmi_pin_pol = VOP_REG(RK3126_INT_SCALER, 0x7, 4), 233 .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22), 234 .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23), 235 .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24), 236 .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25), 237 .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28), 238 .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29), 239 }; 240 241 static const struct vop_data rk3126_vop = { 242 .intr = &rk3036_intr, 243 .common = &rk3036_common, 244 .modeset = &rk3036_modeset, 245 .output = &rk3126_output, 246 .win = rk3126_vop_win_data, 247 .win_size = ARRAY_SIZE(rk3126_vop_win_data), 248 .max_output = { 1920, 1080 }, 249 }; 250 251 static const int px30_vop_intrs[] = { 252 FS_INTR, 253 0, 0, 254 LINE_FLAG_INTR, 255 0, 256 BUS_ERROR_INTR, 257 0, 0, 258 DSP_HOLD_VALID_INTR, 259 }; 260 261 static const struct vop_intr px30_intr = { 262 .intrs = px30_vop_intrs, 263 .nintrs = ARRAY_SIZE(px30_vop_intrs), 264 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0), 265 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0), 266 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0), 267 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0), 268 }; 269 270 static const struct vop_common px30_common = { 271 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), 272 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), 273 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), 274 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), 275 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7), 276 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6), 277 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), 278 }; 279 280 static const struct vop_modeset px30_modeset = { 281 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 282 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), 283 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 284 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), 285 }; 286 287 static const struct vop_output px30_output = { 288 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1), 289 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2), 290 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 291 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25), 292 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26), 293 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 294 }; 295 296 static const struct vop_scl_regs px30_win_scl = { 297 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 298 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 299 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 300 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 301 }; 302 303 static const struct vop_win_phy px30_win0_data = { 304 .scl = &px30_win_scl, 305 .data_formats = formats_win_full, 306 .nformats = ARRAY_SIZE(formats_win_full), 307 .format_modifiers = format_modifiers_win_full, 308 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), 309 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), 310 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), 311 .uv_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 15), 312 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), 313 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), 314 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), 315 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), 316 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), 317 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), 318 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), 319 .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2), 320 .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1), 321 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0), 322 }; 323 324 static const struct vop_win_phy px30_win1_data = { 325 .data_formats = formats_win_lite, 326 .nformats = ARRAY_SIZE(formats_win_lite), 327 .format_modifiers = format_modifiers_win_lite, 328 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), 329 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), 330 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), 331 .uv_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 15), 332 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), 333 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), 334 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), 335 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), 336 .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2), 337 .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1), 338 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0), 339 }; 340 341 static const struct vop_win_phy px30_win2_data = { 342 .data_formats = formats_win_lite, 343 .nformats = ARRAY_SIZE(formats_win_lite), 344 .format_modifiers = format_modifiers_win_lite, 345 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), 346 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), 347 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), 348 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), 349 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), 350 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), 351 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), 352 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), 353 .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2), 354 .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1), 355 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0), 356 }; 357 358 static const struct vop_win_data px30_vop_big_win_data[] = { 359 { .base = 0x00, .phy = &px30_win0_data, 360 .type = DRM_PLANE_TYPE_PRIMARY }, 361 { .base = 0x00, .phy = &px30_win1_data, 362 .type = DRM_PLANE_TYPE_OVERLAY }, 363 { .base = 0x00, .phy = &px30_win2_data, 364 .type = DRM_PLANE_TYPE_CURSOR }, 365 }; 366 367 static const struct vop_data px30_vop_big = { 368 .version = VOP_VERSION(2, 6), 369 .intr = &px30_intr, 370 .feature = VOP_FEATURE_INTERNAL_RGB, 371 .common = &px30_common, 372 .modeset = &px30_modeset, 373 .output = &px30_output, 374 .win = px30_vop_big_win_data, 375 .win_size = ARRAY_SIZE(px30_vop_big_win_data), 376 .max_output = { 1920, 1080 }, 377 }; 378 379 static const struct vop_win_data px30_vop_lit_win_data[] = { 380 { .base = 0x00, .phy = &px30_win1_data, 381 .type = DRM_PLANE_TYPE_PRIMARY }, 382 }; 383 384 static const struct vop_data px30_vop_lit = { 385 .version = VOP_VERSION(2, 5), 386 .intr = &px30_intr, 387 .feature = VOP_FEATURE_INTERNAL_RGB, 388 .common = &px30_common, 389 .modeset = &px30_modeset, 390 .output = &px30_output, 391 .win = px30_vop_lit_win_data, 392 .win_size = ARRAY_SIZE(px30_vop_lit_win_data), 393 .max_output = { 1920, 1080 }, 394 }; 395 396 static const struct vop_scl_regs rk3066_win_scl = { 397 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 398 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 399 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 400 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 401 }; 402 403 static const struct vop_win_phy rk3066_win0_data = { 404 .scl = &rk3066_win_scl, 405 .data_formats = formats_win_full, 406 .nformats = ARRAY_SIZE(formats_win_full), 407 .format_modifiers = format_modifiers_win_full, 408 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0), 409 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4), 410 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19), 411 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 22), 412 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0), 413 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0), 414 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0), 415 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0), 416 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0), 417 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0), 418 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16), 419 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21), 420 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0), 421 }; 422 423 static const struct vop_win_phy rk3066_win1_data = { 424 .data_formats = formats_win_full, 425 .nformats = ARRAY_SIZE(formats_win_full), 426 .format_modifiers = format_modifiers_win_full, 427 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1), 428 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7), 429 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23), 430 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 26), 431 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0), 432 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0), 433 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0), 434 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0), 435 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0), 436 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0), 437 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16), 438 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22), 439 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1), 440 }; 441 442 static const struct vop_win_phy rk3066_win2_data = { 443 .data_formats = formats_win_lite, 444 .nformats = ARRAY_SIZE(formats_win_lite), 445 .format_modifiers = format_modifiers_win_lite, 446 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2), 447 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10), 448 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27), 449 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0), 450 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0), 451 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0), 452 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0), 453 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23), 454 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2), 455 }; 456 457 static const struct vop_modeset rk3066_modeset = { 458 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 459 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0), 460 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 461 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0), 462 }; 463 464 static const struct vop_output rk3066_output = { 465 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4), 466 }; 467 468 static const struct vop_common rk3066_common = { 469 .dma_stop = VOP_REG(RK3066_SYS_CTRL0, 0x1, 0), 470 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1), 471 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0), 472 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0), 473 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11), 474 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10), 475 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24), 476 .dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9), 477 .dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31), 478 .data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25), 479 }; 480 481 static const struct vop_win_data rk3066_vop_win_data[] = { 482 { .base = 0x00, .phy = &rk3066_win0_data, 483 .type = DRM_PLANE_TYPE_PRIMARY }, 484 { .base = 0x00, .phy = &rk3066_win1_data, 485 .type = DRM_PLANE_TYPE_OVERLAY }, 486 { .base = 0x00, .phy = &rk3066_win2_data, 487 .type = DRM_PLANE_TYPE_CURSOR }, 488 }; 489 490 static const int rk3066_vop_intrs[] = { 491 /* 492 * hs_start interrupt fires at frame-start, so serves 493 * the same purpose as dsp_hold in the driver. 494 */ 495 DSP_HOLD_VALID_INTR, 496 FS_INTR, 497 LINE_FLAG_INTR, 498 BUS_ERROR_INTR, 499 }; 500 501 static const struct vop_intr rk3066_intr = { 502 .intrs = rk3066_vop_intrs, 503 .nintrs = ARRAY_SIZE(rk3066_vop_intrs), 504 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12), 505 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0), 506 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4), 507 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8), 508 }; 509 510 static const struct vop_data rk3066_vop = { 511 .version = VOP_VERSION(2, 1), 512 .intr = &rk3066_intr, 513 .common = &rk3066_common, 514 .modeset = &rk3066_modeset, 515 .output = &rk3066_output, 516 .win = rk3066_vop_win_data, 517 .win_size = ARRAY_SIZE(rk3066_vop_win_data), 518 .feature = VOP_FEATURE_INTERNAL_RGB, 519 .max_output = { 1920, 1080 }, 520 }; 521 522 static const struct vop_scl_regs rk3188_win_scl = { 523 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 524 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 525 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 526 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 527 }; 528 529 static const struct vop_win_phy rk3188_win0_data = { 530 .scl = &rk3188_win_scl, 531 .data_formats = formats_win_full, 532 .nformats = ARRAY_SIZE(formats_win_full), 533 .format_modifiers = format_modifiers_win_full, 534 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0), 535 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3), 536 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15), 537 .uv_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 18), 538 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0), 539 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0), 540 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0), 541 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0), 542 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0), 543 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0), 544 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18), 545 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0), 546 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), 547 }; 548 549 static const struct vop_win_phy rk3188_win1_data = { 550 .data_formats = formats_win_lite, 551 .nformats = ARRAY_SIZE(formats_win_lite), 552 .format_modifiers = format_modifiers_win_lite, 553 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1), 554 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6), 555 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19), 556 /* no act_info on window1 */ 557 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0), 558 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0), 559 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0), 560 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16), 561 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19), 562 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1), 563 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), 564 }; 565 566 static const struct vop_modeset rk3188_modeset = { 567 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 568 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0), 569 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 570 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0), 571 }; 572 573 static const struct vop_output rk3188_output = { 574 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4), 575 }; 576 577 static const struct vop_common rk3188_common = { 578 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31), 579 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30), 580 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0), 581 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0), 582 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27), 583 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11), 584 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10), 585 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24), 586 .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9), 587 .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28), 588 .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25), 589 }; 590 591 static const struct vop_win_data rk3188_vop_win_data[] = { 592 { .base = 0x00, .phy = &rk3188_win0_data, 593 .type = DRM_PLANE_TYPE_PRIMARY }, 594 { .base = 0x00, .phy = &rk3188_win1_data, 595 .type = DRM_PLANE_TYPE_CURSOR }, 596 }; 597 598 static const int rk3188_vop_intrs[] = { 599 /* 600 * hs_start interrupt fires at frame-start, so serves 601 * the same purpose as dsp_hold in the driver. 602 */ 603 DSP_HOLD_VALID_INTR, 604 FS_INTR, 605 LINE_FLAG_INTR, 606 BUS_ERROR_INTR, 607 }; 608 609 static const struct vop_intr rk3188_vop_intr = { 610 .intrs = rk3188_vop_intrs, 611 .nintrs = ARRAY_SIZE(rk3188_vop_intrs), 612 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12), 613 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0), 614 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4), 615 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8), 616 }; 617 618 static const struct vop_data rk3188_vop = { 619 .intr = &rk3188_vop_intr, 620 .common = &rk3188_common, 621 .modeset = &rk3188_modeset, 622 .output = &rk3188_output, 623 .win = rk3188_vop_win_data, 624 .win_size = ARRAY_SIZE(rk3188_vop_win_data), 625 .feature = VOP_FEATURE_INTERNAL_RGB, 626 .max_output = { 2048, 1536 }, 627 }; 628 629 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 630 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 631 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 632 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 633 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 634 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 635 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 636 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 637 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 638 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 639 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 640 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 641 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 642 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 643 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 644 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 645 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 646 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 647 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 648 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 649 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 650 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 651 }; 652 653 static const struct vop_scl_regs rk3288_win_full_scl = { 654 .ext = &rk3288_win_full_scl_ext, 655 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 656 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 657 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 658 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 659 }; 660 661 static const struct vop_win_phy rk3288_win01_data = { 662 .scl = &rk3288_win_full_scl, 663 .data_formats = formats_win_full_10, 664 .nformats = ARRAY_SIZE(formats_win_full_10), 665 .format_modifiers = format_modifiers_win_full, 666 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 667 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 668 .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), 669 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 670 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), 671 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 672 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 673 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 674 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 675 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 676 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 677 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 678 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 679 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), 680 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), 681 }; 682 683 static const struct vop_win_phy rk3288_win23_data = { 684 .data_formats = formats_win_lite, 685 .nformats = ARRAY_SIZE(formats_win_lite), 686 .format_modifiers = format_modifiers_win_lite, 687 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4), 688 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 689 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1), 690 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12), 691 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0), 692 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0), 693 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0), 694 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0), 695 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 696 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), 697 }; 698 699 static const struct vop_modeset rk3288_modeset = { 700 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 701 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 702 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 703 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 704 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 705 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 706 }; 707 708 static const struct vop_output rk3288_output = { 709 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), 710 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 711 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 712 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 713 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 714 }; 715 716 static const struct vop_common rk3288_common = { 717 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), 718 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 719 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), 720 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4), 721 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3), 722 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2), 723 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), 724 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 725 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 726 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), 727 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 728 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 729 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), 730 }; 731 732 /* 733 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 734 * special support to get alpha blending working. For now, just use overlay 735 * window 3 for the drm cursor. 736 * 737 */ 738 static const struct vop_win_data rk3288_vop_win_data[] = { 739 { .base = 0x00, .phy = &rk3288_win01_data, 740 .type = DRM_PLANE_TYPE_PRIMARY }, 741 { .base = 0x40, .phy = &rk3288_win01_data, 742 .type = DRM_PLANE_TYPE_OVERLAY }, 743 { .base = 0x00, .phy = &rk3288_win23_data, 744 .type = DRM_PLANE_TYPE_OVERLAY }, 745 { .base = 0x50, .phy = &rk3288_win23_data, 746 .type = DRM_PLANE_TYPE_CURSOR }, 747 }; 748 749 static const int rk3288_vop_intrs[] = { 750 DSP_HOLD_VALID_INTR, 751 FS_INTR, 752 LINE_FLAG_INTR, 753 BUS_ERROR_INTR, 754 }; 755 756 static const struct vop_intr rk3288_vop_intr = { 757 .intrs = rk3288_vop_intrs, 758 .nintrs = ARRAY_SIZE(rk3288_vop_intrs), 759 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 760 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0), 761 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4), 762 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), 763 }; 764 765 static const struct vop_data rk3288_vop = { 766 .version = VOP_VERSION(3, 1), 767 .feature = VOP_FEATURE_OUTPUT_RGB10, 768 .intr = &rk3288_vop_intr, 769 .common = &rk3288_common, 770 .modeset = &rk3288_modeset, 771 .output = &rk3288_output, 772 .win = rk3288_vop_win_data, 773 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 774 .lut_size = 1024, 775 /* 776 * This is the maximum resolution for the VOPB, the VOPL can only do 777 * 2560x1600, but we can't distinguish them as they have the same 778 * compatible. 779 */ 780 .max_output = { 3840, 2160 }, 781 }; 782 783 static const int rk3368_vop_intrs[] = { 784 FS_INTR, 785 0, 0, 786 LINE_FLAG_INTR, 787 0, 788 BUS_ERROR_INTR, 789 0, 0, 0, 0, 0, 0, 0, 790 DSP_HOLD_VALID_INTR, 791 }; 792 793 static const struct vop_intr rk3368_vop_intr = { 794 .intrs = rk3368_vop_intrs, 795 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 796 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 797 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 798 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), 799 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), 800 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), 801 }; 802 803 static const struct vop_win_phy rk3368_win01_data = { 804 .scl = &rk3288_win_full_scl, 805 .data_formats = formats_win_full, 806 .nformats = ARRAY_SIZE(formats_win_full), 807 .format_modifiers = format_modifiers_win_full, 808 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), 809 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), 810 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), 811 .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), 812 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), 813 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), 814 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0), 815 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0), 816 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0), 817 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0), 818 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0), 819 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0), 820 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16), 821 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 822 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0), 823 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0), 824 }; 825 826 static const struct vop_win_phy rk3368_win23_data = { 827 .data_formats = formats_win_lite, 828 .nformats = ARRAY_SIZE(formats_win_lite), 829 .format_modifiers = format_modifiers_win_lite, 830 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), 831 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 832 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 833 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 834 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 835 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 836 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 837 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 838 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 839 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 840 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), 841 }; 842 843 static const struct vop_win_data rk3368_vop_win_data[] = { 844 { .base = 0x00, .phy = &rk3368_win01_data, 845 .type = DRM_PLANE_TYPE_PRIMARY }, 846 { .base = 0x40, .phy = &rk3368_win01_data, 847 .type = DRM_PLANE_TYPE_OVERLAY }, 848 { .base = 0x00, .phy = &rk3368_win23_data, 849 .type = DRM_PLANE_TYPE_OVERLAY }, 850 { .base = 0x50, .phy = &rk3368_win23_data, 851 .type = DRM_PLANE_TYPE_CURSOR }, 852 }; 853 854 static const struct vop_output rk3368_output = { 855 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), 856 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), 857 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), 858 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), 859 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), 860 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), 861 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), 862 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), 863 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 864 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 865 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 866 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 867 }; 868 869 static const struct vop_misc rk3368_misc = { 870 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), 871 }; 872 873 static const struct vop_data rk3368_vop = { 874 .version = VOP_VERSION(3, 2), 875 .intr = &rk3368_vop_intr, 876 .common = &rk3288_common, 877 .modeset = &rk3288_modeset, 878 .output = &rk3368_output, 879 .misc = &rk3368_misc, 880 .win = rk3368_vop_win_data, 881 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 882 .max_output = { 4096, 2160 }, 883 .lut_size = 1024, 884 }; 885 886 static const struct vop_intr rk3366_vop_intr = { 887 .intrs = rk3368_vop_intrs, 888 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 889 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 890 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 891 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), 892 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), 893 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), 894 }; 895 896 static const struct vop_data rk3366_vop = { 897 .version = VOP_VERSION(3, 4), 898 .intr = &rk3366_vop_intr, 899 .common = &rk3288_common, 900 .modeset = &rk3288_modeset, 901 .output = &rk3368_output, 902 .misc = &rk3368_misc, 903 .win = rk3368_vop_win_data, 904 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 905 .max_output = { 4096, 2160 }, 906 }; 907 908 static const struct vop_output rk3399_output = { 909 .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19), 910 .rgb_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19), 911 .hdmi_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 23), 912 .edp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 27), 913 .mipi_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 31), 914 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16), 915 .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16), 916 .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 20), 917 .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 24), 918 .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 28), 919 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 920 .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), 921 .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), 922 .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), 923 .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), 924 .mipi_dual_channel_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 3), 925 }; 926 927 static const struct vop_common rk3399_common = { 928 .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), 929 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), 930 .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), 931 .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), 932 .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), 933 .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), 934 .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), 935 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), 936 .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), 937 .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), 938 .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), 939 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), 940 .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), 941 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), 942 .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), 943 }; 944 945 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { 946 .y2r_coefficients = { 947 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), 948 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16), 949 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0), 950 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16), 951 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0), 952 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16), 953 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0), 954 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16), 955 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0), 956 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0), 957 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0), 958 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0), 959 }, 960 }; 961 962 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win23_data = { }; 963 964 static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { 965 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 966 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) }, 967 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data, 968 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) }, 969 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data }, 970 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data }, 971 972 }; 973 974 static const struct vop_win_phy rk3399_win0_data = { 975 .scl = &rk3288_win_full_scl, 976 .data_formats = formats_win_full_10, 977 .nformats = ARRAY_SIZE(formats_win_full_10), 978 .format_modifiers = format_modifiers_win_full_afbc, 979 .enable = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 0), 980 .format = VOP_REG(RK3399_WIN0_CTRL0, 0x7, 1), 981 .fmt_10 = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 4), 982 .rb_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 12), 983 .uv_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 15), 984 .x_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 21), 985 .y_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 22), 986 .act_info = VOP_REG(RK3399_WIN0_ACT_INFO, 0x1fff1fff, 0), 987 .dsp_info = VOP_REG(RK3399_WIN0_DSP_INFO, 0x0fff0fff, 0), 988 .dsp_st = VOP_REG(RK3399_WIN0_DSP_ST, 0x1fff1fff, 0), 989 .yrgb_mst = VOP_REG(RK3399_WIN0_YRGB_MST, 0xffffffff, 0), 990 .uv_mst = VOP_REG(RK3399_WIN0_CBR_MST, 0xffffffff, 0), 991 .yrgb_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 0), 992 .uv_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 16), 993 .src_alpha_ctl = VOP_REG(RK3399_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 994 .dst_alpha_ctl = VOP_REG(RK3399_WIN0_DST_ALPHA_CTRL, 0xff, 0), 995 .channel = VOP_REG(RK3399_WIN0_CTRL2, 0xff, 0), 996 }; 997 998 static const struct vop_win_phy rk3399_win1_data = { 999 .scl = &rk3288_win_full_scl, 1000 .data_formats = formats_win_full_10, 1001 .nformats = ARRAY_SIZE(formats_win_full_10), 1002 .format_modifiers = format_modifiers_win_full, 1003 .enable = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 0), 1004 .format = VOP_REG(RK3399_WIN0_CTRL0, 0x7, 1), 1005 .fmt_10 = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 4), 1006 .rb_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 12), 1007 .uv_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 15), 1008 .x_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 21), 1009 .y_mir_en = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 22), 1010 .act_info = VOP_REG(RK3399_WIN0_ACT_INFO, 0x1fff1fff, 0), 1011 .dsp_info = VOP_REG(RK3399_WIN0_DSP_INFO, 0x0fff0fff, 0), 1012 .dsp_st = VOP_REG(RK3399_WIN0_DSP_ST, 0x1fff1fff, 0), 1013 .yrgb_mst = VOP_REG(RK3399_WIN0_YRGB_MST, 0xffffffff, 0), 1014 .uv_mst = VOP_REG(RK3399_WIN0_CBR_MST, 0xffffffff, 0), 1015 .yrgb_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 0), 1016 .uv_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 16), 1017 .src_alpha_ctl = VOP_REG(RK3399_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 1018 .dst_alpha_ctl = VOP_REG(RK3399_WIN0_DST_ALPHA_CTRL, 0xff, 0), 1019 .channel = VOP_REG(RK3399_WIN0_CTRL2, 0xff, 0), 1020 }; 1021 1022 /* 1023 * rk3399 vop big windows register layout is same as rk3288, but we 1024 * have a separate rk3399 win data array here so that we can advertise 1025 * AFBC on the primary plane. 1026 */ 1027 static const struct vop_win_data rk3399_vop_win_data[] = { 1028 { .base = 0x00, .phy = &rk3399_win0_data, 1029 .type = DRM_PLANE_TYPE_PRIMARY }, 1030 { .base = 0x40, .phy = &rk3399_win1_data, 1031 .type = DRM_PLANE_TYPE_OVERLAY }, 1032 { .base = 0x00, .phy = &rk3368_win23_data, 1033 .type = DRM_PLANE_TYPE_OVERLAY }, 1034 { .base = 0x50, .phy = &rk3368_win23_data, 1035 .type = DRM_PLANE_TYPE_CURSOR }, 1036 }; 1037 1038 static const struct vop_afbc rk3399_vop_afbc = { 1039 .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3), 1040 .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0), 1041 .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1), 1042 .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16), 1043 .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21), 1044 .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0), 1045 .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0), 1046 }; 1047 1048 static const struct vop_data rk3399_vop_big = { 1049 .version = VOP_VERSION(3, 5), 1050 .feature = VOP_FEATURE_OUTPUT_RGB10, 1051 .intr = &rk3366_vop_intr, 1052 .common = &rk3399_common, 1053 .modeset = &rk3288_modeset, 1054 .output = &rk3399_output, 1055 .afbc = &rk3399_vop_afbc, 1056 .misc = &rk3368_misc, 1057 .win = rk3399_vop_win_data, 1058 .win_size = ARRAY_SIZE(rk3399_vop_win_data), 1059 .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, 1060 .lut_size = 1024, 1061 .max_output = { 4096, 2160 }, 1062 }; 1063 1064 static const struct vop_win_data rk3399_vop_lit_win_data[] = { 1065 { .base = 0x00, .phy = &rk3368_win01_data, 1066 .type = DRM_PLANE_TYPE_PRIMARY }, 1067 { .base = 0x00, .phy = &rk3368_win23_data, 1068 .type = DRM_PLANE_TYPE_CURSOR}, 1069 }; 1070 1071 static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { 1072 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 1073 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)}, 1074 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data }, 1075 }; 1076 1077 static const struct vop_data rk3399_vop_lit = { 1078 .version = VOP_VERSION(3, 6), 1079 .intr = &rk3366_vop_intr, 1080 .common = &rk3399_common, 1081 .modeset = &rk3288_modeset, 1082 .output = &rk3399_output, 1083 .misc = &rk3368_misc, 1084 .win = rk3399_vop_lit_win_data, 1085 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 1086 .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, 1087 .lut_size = 256, 1088 .max_output = { 2560, 1600 }, 1089 }; 1090 1091 static const struct vop_win_data rk3228_vop_win_data[] = { 1092 { .base = 0x00, .phy = &rk3288_win01_data, 1093 .type = DRM_PLANE_TYPE_PRIMARY }, 1094 { .base = 0x40, .phy = &rk3288_win01_data, 1095 .type = DRM_PLANE_TYPE_CURSOR }, 1096 }; 1097 1098 static const struct vop_data rk3228_vop = { 1099 .version = VOP_VERSION(3, 7), 1100 .feature = VOP_FEATURE_OUTPUT_RGB10, 1101 .intr = &rk3366_vop_intr, 1102 .common = &rk3288_common, 1103 .modeset = &rk3288_modeset, 1104 .output = &rk3399_output, 1105 .misc = &rk3368_misc, 1106 .win = rk3228_vop_win_data, 1107 .win_size = ARRAY_SIZE(rk3228_vop_win_data), 1108 .max_output = { 4096, 2160 }, 1109 }; 1110 1111 static const struct vop_modeset rk3328_modeset = { 1112 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 1113 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 1114 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 1115 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 1116 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 1117 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 1118 }; 1119 1120 static const struct vop_output rk3328_output = { 1121 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19), 1122 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23), 1123 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27), 1124 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31), 1125 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 1126 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 1127 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 1128 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 1129 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16), 1130 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20), 1131 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24), 1132 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28), 1133 }; 1134 1135 static const struct vop_misc rk3328_misc = { 1136 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 1137 }; 1138 1139 static const struct vop_common rk3328_common = { 1140 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), 1141 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4), 1142 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3), 1143 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2), 1144 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1), 1145 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 1146 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 1147 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 1148 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), 1149 }; 1150 1151 static const struct vop_intr rk3328_vop_intr = { 1152 .intrs = rk3368_vop_intrs, 1153 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 1154 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 1155 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 1156 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), 1157 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), 1158 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), 1159 }; 1160 1161 static const struct vop_win_data rk3328_vop_win_data[] = { 1162 { .base = 0xd0, .phy = &rk3399_win1_data, 1163 .type = DRM_PLANE_TYPE_PRIMARY }, 1164 { .base = 0x1d0, .phy = &rk3399_win1_data, 1165 .type = DRM_PLANE_TYPE_OVERLAY }, 1166 { .base = 0x2d0, .phy = &rk3399_win1_data, 1167 .type = DRM_PLANE_TYPE_CURSOR }, 1168 }; 1169 1170 static const struct vop_data rk3328_vop = { 1171 .version = VOP_VERSION(3, 8), 1172 .feature = VOP_FEATURE_OUTPUT_RGB10, 1173 .intr = &rk3328_vop_intr, 1174 .common = &rk3328_common, 1175 .modeset = &rk3328_modeset, 1176 .output = &rk3328_output, 1177 .misc = &rk3328_misc, 1178 .win = rk3328_vop_win_data, 1179 .win_size = ARRAY_SIZE(rk3328_vop_win_data), 1180 .max_output = { 4096, 2160 }, 1181 }; 1182 1183 static const struct vop_common rv1126_common = { 1184 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), 1185 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), 1186 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), 1187 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), 1188 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7), 1189 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6), 1190 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), 1191 .dither_up = VOP_REG(PX30_DSP_CTRL2, 0x1, 2), 1192 .dsp_lut_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 5), 1193 .gate_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 0), 1194 }; 1195 1196 static const struct vop_modeset rv1126_modeset = { 1197 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 1198 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), 1199 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 1200 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), 1201 }; 1202 1203 static const struct vop_output rv1126_output = { 1204 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1), 1205 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2), 1206 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 1207 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25), 1208 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26), 1209 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 1210 }; 1211 1212 static const struct vop_misc rv1126_misc = { 1213 .global_regdone_en = VOP_REG(PX30_SYS_CTRL2, 0x1, 13), 1214 }; 1215 1216 static const struct vop_win_data rv1126_vop_win_data[] = { 1217 { .base = 0x00, .phy = &px30_win0_data, 1218 .type = DRM_PLANE_TYPE_OVERLAY }, 1219 { .base = 0x00, .phy = &px30_win2_data, 1220 .type = DRM_PLANE_TYPE_PRIMARY }, 1221 }; 1222 1223 static const struct vop_data rv1126_vop = { 1224 .version = VOP_VERSION(2, 0xb), 1225 .intr = &px30_intr, 1226 .common = &rv1126_common, 1227 .modeset = &rv1126_modeset, 1228 .output = &rv1126_output, 1229 .misc = &rv1126_misc, 1230 .win = rv1126_vop_win_data, 1231 .win_size = ARRAY_SIZE(rv1126_vop_win_data), 1232 .max_output = { 1920, 1080 }, 1233 .lut_size = 1024, 1234 }; 1235 1236 static const struct of_device_id vop_driver_dt_match[] = { 1237 { .compatible = "rockchip,rk3036-vop", 1238 .data = &rk3036_vop }, 1239 { .compatible = "rockchip,rk3126-vop", 1240 .data = &rk3126_vop }, 1241 { .compatible = "rockchip,px30-vop-big", 1242 .data = &px30_vop_big }, 1243 { .compatible = "rockchip,px30-vop-lit", 1244 .data = &px30_vop_lit }, 1245 { .compatible = "rockchip,rk3066-vop", 1246 .data = &rk3066_vop }, 1247 { .compatible = "rockchip,rk3188-vop", 1248 .data = &rk3188_vop }, 1249 { .compatible = "rockchip,rk3288-vop", 1250 .data = &rk3288_vop }, 1251 { .compatible = "rockchip,rk3368-vop", 1252 .data = &rk3368_vop }, 1253 { .compatible = "rockchip,rk3366-vop", 1254 .data = &rk3366_vop }, 1255 { .compatible = "rockchip,rk3399-vop-big", 1256 .data = &rk3399_vop_big }, 1257 { .compatible = "rockchip,rk3399-vop-lit", 1258 .data = &rk3399_vop_lit }, 1259 { .compatible = "rockchip,rk3228-vop", 1260 .data = &rk3228_vop }, 1261 { .compatible = "rockchip,rk3328-vop", 1262 .data = &rk3328_vop }, 1263 { .compatible = "rockchip,rv1126-vop", 1264 .data = &rv1126_vop }, 1265 {}, 1266 }; 1267 MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 1268 1269 static int vop_probe(struct platform_device *pdev) 1270 { 1271 struct device *dev = &pdev->dev; 1272 1273 if (!dev->of_node) { 1274 DRM_DEV_ERROR(dev, "can't find vop devices\n"); 1275 return -ENODEV; 1276 } 1277 1278 return component_add(dev, &vop_component_ops); 1279 } 1280 1281 static void vop_remove(struct platform_device *pdev) 1282 { 1283 component_del(&pdev->dev, &vop_component_ops); 1284 } 1285 1286 struct platform_driver vop_platform_driver = { 1287 .probe = vop_probe, 1288 .remove = vop_remove, 1289 .driver = { 1290 .name = "rockchip-vop", 1291 .of_match_table = vop_driver_dt_match, 1292 }, 1293 }; 1294