1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: 5 * Sandy Huang <hjc@rock-chips.com> 6 * Mark Yao <mark.yao@rock-chips.com> 7 */ 8 9 #ifndef _ROCKCHIP_LVDS_ 10 #define _ROCKCHIP_LVDS_ 11 12 #include <linux/bits.h> 13 #include <linux/hw_bitfield.h> 14 15 #define RK3288_LVDS_CH0_REG0 0x00 16 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7) 17 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6) 18 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5) 19 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4) 20 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3) 21 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2) 22 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1) 23 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0) 24 25 #define RK3288_LVDS_CH0_REG1 0x04 26 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5) 27 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4) 28 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3) 29 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2) 30 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1) 31 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0) 32 33 #define RK3288_LVDS_CH0_REG2 0x08 34 #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7) 35 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6) 36 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5) 37 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4) 38 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3) 39 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2) 40 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1) 41 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0) 42 43 #define RK3288_LVDS_CH0_REG3 0x0c 44 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff 45 46 #define RK3288_LVDS_CH0_REG4 0x10 47 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5) 48 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4) 49 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3) 50 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2) 51 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1) 52 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0) 53 54 #define RK3288_LVDS_CH0_REG5 0x14 55 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5) 56 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4) 57 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3) 58 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2) 59 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1) 60 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0) 61 62 #define RK3288_LVDS_CFG_REGC 0x30 63 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00 64 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff 65 66 #define RK3288_LVDS_CH0_REGD 0x34 67 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f 68 69 #define RK3288_LVDS_CH0_REG20 0x80 70 #define RK3288_LVDS_CH0_REG20_MSB 0x45 71 #define RK3288_LVDS_CH0_REG20_LSB 0x44 72 73 #define RK3288_LVDS_CFG_REG21 0x84 74 #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92 75 #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00 76 #define RK3288_LVDS_CH1_OFFSET 0x100 77 78 #define RK3288_LVDS_GRF_SOC_CON6 0x025C 79 #define RK3288_LVDS_GRF_SOC_CON7 0x0260 80 81 /* fbdiv value is split over 2 registers, with bit8 in reg2 */ 82 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ 83 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0) 84 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \ 85 (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK) 86 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \ 87 (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK) 88 89 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3) 90 91 #define LVDS_FMT_MASK (0x07 << 16) 92 #define LVDS_MSB BIT(3) 93 #define LVDS_DUAL BIT(4) 94 #define LVDS_FMT_1 BIT(5) 95 #define LVDS_TTL_EN BIT(6) 96 #define LVDS_START_PHASE_RST_1 BIT(7) 97 #define LVDS_DCLK_INV BIT(8) 98 #define LVDS_CH0_EN BIT(11) 99 #define LVDS_CH1_EN BIT(12) 100 #define LVDS_PWRDN BIT(15) 101 102 #define LVDS_24BIT (0 << 1) 103 #define LVDS_18BIT (1 << 1) 104 #define LVDS_FORMAT_VESA (0 << 0) 105 #define LVDS_FORMAT_JEIDA (1 << 0) 106 107 #define LVDS_VESA_24 0 108 #define LVDS_JEIDA_24 1 109 #define LVDS_VESA_18 2 110 #define LVDS_JEIDA_18 3 111 112 #define PX30_LVDS_GRF_PD_VO_CON0 0x434 113 #define PX30_LVDS_TIE_CLKS(val) FIELD_PREP_WM16(BIT(8), (val)) 114 #define PX30_LVDS_INVERT_CLKS(val) FIELD_PREP_WM16(BIT(9), (val)) 115 #define PX30_LVDS_INVERT_DCLK(val) FIELD_PREP_WM16(BIT(5), (val)) 116 117 #define PX30_LVDS_GRF_PD_VO_CON1 0x438 118 #define PX30_LVDS_FORMAT(val) FIELD_PREP_WM16(GENMASK(14, 13), (val)) 119 #define PX30_LVDS_MODE_EN(val) FIELD_PREP_WM16(BIT(12), (val)) 120 #define PX30_LVDS_MSBSEL(val) FIELD_PREP_WM16(BIT(11), (val)) 121 #define PX30_LVDS_P2S_EN(val) FIELD_PREP_WM16(BIT(6), (val)) 122 #define PX30_LVDS_VOP_SEL(val) FIELD_PREP_WM16(BIT(1), (val)) 123 124 #endif /* _ROCKCHIP_LVDS_ */ 125