1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_DRM_VOP2_H 8 #define _ROCKCHIP_DRM_VOP2_H 9 10 #include <linux/regmap.h> 11 #include <drm/drm_modes.h> 12 #include "rockchip_drm_vop.h" 13 14 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 15 16 #define WIN_FEATURE_AFBDC BIT(0) 17 #define WIN_FEATURE_CLUSTER BIT(1) 18 19 /* 20 * the delay number of a window in different mode. 21 */ 22 enum win_dly_mode { 23 VOP2_DLY_MODE_DEFAULT, /**< default mode */ 24 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ 25 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ 26 VOP2_DLY_MODE_MAX, 27 }; 28 29 enum vop2_scale_up_mode { 30 VOP2_SCALE_UP_NRST_NBOR, 31 VOP2_SCALE_UP_BIL, 32 VOP2_SCALE_UP_BIC, 33 }; 34 35 enum vop2_scale_down_mode { 36 VOP2_SCALE_DOWN_NRST_NBOR, 37 VOP2_SCALE_DOWN_BIL, 38 VOP2_SCALE_DOWN_AVG, 39 }; 40 41 enum vop2_win_regs { 42 VOP2_WIN_ENABLE, 43 VOP2_WIN_FORMAT, 44 VOP2_WIN_CSC_MODE, 45 VOP2_WIN_XMIRROR, 46 VOP2_WIN_YMIRROR, 47 VOP2_WIN_RB_SWAP, 48 VOP2_WIN_UV_SWAP, 49 VOP2_WIN_ACT_INFO, 50 VOP2_WIN_DSP_INFO, 51 VOP2_WIN_DSP_ST, 52 VOP2_WIN_YRGB_MST, 53 VOP2_WIN_UV_MST, 54 VOP2_WIN_YRGB_VIR, 55 VOP2_WIN_UV_VIR, 56 VOP2_WIN_YUV_CLIP, 57 VOP2_WIN_Y2R_EN, 58 VOP2_WIN_R2Y_EN, 59 VOP2_WIN_COLOR_KEY, 60 VOP2_WIN_COLOR_KEY_EN, 61 VOP2_WIN_DITHER_UP, 62 63 /* scale regs */ 64 VOP2_WIN_SCALE_YRGB_X, 65 VOP2_WIN_SCALE_YRGB_Y, 66 VOP2_WIN_SCALE_CBCR_X, 67 VOP2_WIN_SCALE_CBCR_Y, 68 VOP2_WIN_YRGB_HOR_SCL_MODE, 69 VOP2_WIN_YRGB_HSCL_FILTER_MODE, 70 VOP2_WIN_YRGB_VER_SCL_MODE, 71 VOP2_WIN_YRGB_VSCL_FILTER_MODE, 72 VOP2_WIN_CBCR_VER_SCL_MODE, 73 VOP2_WIN_CBCR_HSCL_FILTER_MODE, 74 VOP2_WIN_CBCR_HOR_SCL_MODE, 75 VOP2_WIN_CBCR_VSCL_FILTER_MODE, 76 VOP2_WIN_VSD_CBCR_GT2, 77 VOP2_WIN_VSD_CBCR_GT4, 78 VOP2_WIN_VSD_YRGB_GT2, 79 VOP2_WIN_VSD_YRGB_GT4, 80 VOP2_WIN_BIC_COE_SEL, 81 82 /* cluster regs */ 83 VOP2_WIN_CLUSTER_ENABLE, 84 VOP2_WIN_AFBC_ENABLE, 85 VOP2_WIN_CLUSTER_LB_MODE, 86 87 /* afbc regs */ 88 VOP2_WIN_AFBC_FORMAT, 89 VOP2_WIN_AFBC_RB_SWAP, 90 VOP2_WIN_AFBC_UV_SWAP, 91 VOP2_WIN_AFBC_AUTO_GATING_EN, 92 VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 93 VOP2_WIN_AFBC_PIC_VIR_WIDTH, 94 VOP2_WIN_AFBC_TILE_NUM, 95 VOP2_WIN_AFBC_PIC_OFFSET, 96 VOP2_WIN_AFBC_PIC_SIZE, 97 VOP2_WIN_AFBC_DSP_OFFSET, 98 VOP2_WIN_AFBC_TRANSFORM_OFFSET, 99 VOP2_WIN_AFBC_HDR_PTR, 100 VOP2_WIN_AFBC_HALF_BLOCK_EN, 101 VOP2_WIN_AFBC_ROTATE_270, 102 VOP2_WIN_AFBC_ROTATE_90, 103 VOP2_WIN_MAX_REG, 104 }; 105 106 struct vop2_win_data { 107 const char *name; 108 unsigned int phys_id; 109 110 u32 base; 111 enum drm_plane_type type; 112 113 u32 nformats; 114 const u32 *formats; 115 const uint64_t *format_modifiers; 116 const unsigned int supported_rotations; 117 118 /** 119 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 120 */ 121 unsigned int layer_sel_id; 122 uint64_t feature; 123 124 unsigned int max_upscale_factor; 125 unsigned int max_downscale_factor; 126 const u8 dly[VOP2_DLY_MODE_MAX]; 127 }; 128 129 struct vop2_video_port_data { 130 unsigned int id; 131 u32 feature; 132 u16 gamma_lut_len; 133 u16 cubic_lut_len; 134 struct vop_rect max_output; 135 const u8 pre_scan_max_dly[4]; 136 unsigned int offset; 137 }; 138 139 struct vop2_data { 140 u8 nr_vps; 141 const struct vop2_win_data *win; 142 const struct vop2_video_port_data *vp; 143 struct vop_rect max_input; 144 struct vop_rect max_output; 145 146 unsigned int win_size; 147 unsigned int soc_id; 148 }; 149 150 /* interrupt define */ 151 #define FS_NEW_INTR BIT(4) 152 #define ADDR_SAME_INTR BIT(5) 153 #define LINE_FLAG1_INTR BIT(6) 154 #define WIN0_EMPTY_INTR BIT(7) 155 #define WIN1_EMPTY_INTR BIT(8) 156 #define WIN2_EMPTY_INTR BIT(9) 157 #define WIN3_EMPTY_INTR BIT(10) 158 #define HWC_EMPTY_INTR BIT(11) 159 #define POST_BUF_EMPTY_INTR BIT(12) 160 #define PWM_GEN_INTR BIT(13) 161 #define DMA_FINISH_INTR BIT(14) 162 #define FS_FIELD_INTR BIT(15) 163 #define FE_INTR BIT(16) 164 #define WB_UV_FIFO_FULL_INTR BIT(17) 165 #define WB_YRGB_FIFO_FULL_INTR BIT(18) 166 #define WB_COMPLETE_INTR BIT(19) 167 168 169 enum vop_csc_format { 170 CSC_BT601L, 171 CSC_BT709L, 172 CSC_BT601F, 173 CSC_BT2020, 174 }; 175 176 enum src_factor_mode { 177 SRC_FAC_ALPHA_ZERO, 178 SRC_FAC_ALPHA_ONE, 179 SRC_FAC_ALPHA_DST, 180 SRC_FAC_ALPHA_DST_INVERSE, 181 SRC_FAC_ALPHA_SRC, 182 SRC_FAC_ALPHA_SRC_GLOBAL, 183 }; 184 185 enum dst_factor_mode { 186 DST_FAC_ALPHA_ZERO, 187 DST_FAC_ALPHA_ONE, 188 DST_FAC_ALPHA_SRC, 189 DST_FAC_ALPHA_SRC_INVERSE, 190 DST_FAC_ALPHA_DST, 191 DST_FAC_ALPHA_DST_GLOBAL, 192 }; 193 194 #define RK3568_GRF_VO_CON1 0x0364 195 /* System registers definition */ 196 #define RK3568_REG_CFG_DONE 0x000 197 #define RK3568_VERSION_INFO 0x004 198 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 199 #define RK3568_SYS_AXI_LUT_CTRL 0x024 200 #define RK3568_DSP_IF_EN 0x028 201 #define RK3568_DSP_IF_CTRL 0x02c 202 #define RK3568_DSP_IF_POL 0x030 203 #define RK3568_WB_CTRL 0x40 204 #define RK3568_WB_XSCAL_FACTOR 0x44 205 #define RK3568_WB_YRGB_MST 0x48 206 #define RK3568_WB_CBR_MST 0x4C 207 #define RK3568_OTP_WIN_EN 0x050 208 #define RK3568_LUT_PORT_SEL 0x058 209 #define RK3568_SYS_STATUS0 0x060 210 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) 211 #define RK3568_SYS0_INT_EN 0x80 212 #define RK3568_SYS0_INT_CLR 0x84 213 #define RK3568_SYS0_INT_STATUS 0x88 214 #define RK3568_SYS1_INT_EN 0x90 215 #define RK3568_SYS1_INT_CLR 0x94 216 #define RK3568_SYS1_INT_STATUS 0x98 217 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) 218 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) 219 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) 220 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) 221 222 /* Video Port registers definition */ 223 #define RK3568_VP_DSP_CTRL 0x00 224 #define RK3568_VP_MIPI_CTRL 0x04 225 #define RK3568_VP_COLOR_BAR_CTRL 0x08 226 #define RK3568_VP_3D_LUT_CTRL 0x10 227 #define RK3568_VP_3D_LUT_MST 0x20 228 #define RK3568_VP_DSP_BG 0x2C 229 #define RK3568_VP_PRE_SCAN_HTIMING 0x30 230 #define RK3568_VP_POST_DSP_HACT_INFO 0x34 231 #define RK3568_VP_POST_DSP_VACT_INFO 0x38 232 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C 233 #define RK3568_VP_POST_SCL_CTRL 0x40 234 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 235 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48 236 #define RK3568_VP_DSP_HACT_ST_END 0x4C 237 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50 238 #define RK3568_VP_DSP_VACT_ST_END 0x54 239 #define RK3568_VP_DSP_VS_ST_END_F1 0x58 240 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C 241 #define RK3568_VP_BCSH_CTRL 0x60 242 #define RK3568_VP_BCSH_BCS 0x64 243 #define RK3568_VP_BCSH_H 0x68 244 #define RK3568_VP_BCSH_COLOR_BAR 0x6C 245 246 /* Overlay registers definition */ 247 #define RK3568_OVL_CTRL 0x600 248 #define RK3568_OVL_LAYER_SEL 0x604 249 #define RK3568_OVL_PORT_SEL 0x608 250 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 251 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 252 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 253 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 254 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 255 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 256 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 257 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 258 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 259 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 260 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 261 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 262 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) 263 #define RK3568_CLUSTER_DLY_NUM 0x6F0 264 #define RK3568_SMART_DLY_NUM 0x6F8 265 266 /* Cluster register definition, offset relative to window base */ 267 #define RK3568_CLUSTER_WIN_CTRL0 0x00 268 #define RK3568_CLUSTER_WIN_CTRL1 0x04 269 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10 270 #define RK3568_CLUSTER_WIN_CBR_MST 0x14 271 #define RK3568_CLUSTER_WIN_VIR 0x18 272 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20 273 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24 274 #define RK3568_CLUSTER_WIN_DSP_ST 0x28 275 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 276 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C 277 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 278 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 279 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 280 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C 281 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 282 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 283 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 284 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C 285 286 #define RK3568_CLUSTER_CTRL 0x100 287 288 /* (E)smart register definition, offset relative to window base */ 289 #define RK3568_SMART_CTRL0 0x00 290 #define RK3568_SMART_CTRL1 0x04 291 #define RK3568_SMART_REGION0_CTRL 0x10 292 #define RK3568_SMART_REGION0_YRGB_MST 0x14 293 #define RK3568_SMART_REGION0_CBR_MST 0x18 294 #define RK3568_SMART_REGION0_VIR 0x1C 295 #define RK3568_SMART_REGION0_ACT_INFO 0x20 296 #define RK3568_SMART_REGION0_DSP_INFO 0x24 297 #define RK3568_SMART_REGION0_DSP_ST 0x28 298 #define RK3568_SMART_REGION0_SCL_CTRL 0x30 299 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 300 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 301 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C 302 #define RK3568_SMART_REGION1_CTRL 0x40 303 #define RK3568_SMART_REGION1_YRGB_MST 0x44 304 #define RK3568_SMART_REGION1_CBR_MST 0x48 305 #define RK3568_SMART_REGION1_VIR 0x4C 306 #define RK3568_SMART_REGION1_ACT_INFO 0x50 307 #define RK3568_SMART_REGION1_DSP_INFO 0x54 308 #define RK3568_SMART_REGION1_DSP_ST 0x58 309 #define RK3568_SMART_REGION1_SCL_CTRL 0x60 310 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 311 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 312 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C 313 #define RK3568_SMART_REGION2_CTRL 0x70 314 #define RK3568_SMART_REGION2_YRGB_MST 0x74 315 #define RK3568_SMART_REGION2_CBR_MST 0x78 316 #define RK3568_SMART_REGION2_VIR 0x7C 317 #define RK3568_SMART_REGION2_ACT_INFO 0x80 318 #define RK3568_SMART_REGION2_DSP_INFO 0x84 319 #define RK3568_SMART_REGION2_DSP_ST 0x88 320 #define RK3568_SMART_REGION2_SCL_CTRL 0x90 321 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 322 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 323 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C 324 #define RK3568_SMART_REGION3_CTRL 0xA0 325 #define RK3568_SMART_REGION3_YRGB_MST 0xA4 326 #define RK3568_SMART_REGION3_CBR_MST 0xA8 327 #define RK3568_SMART_REGION3_VIR 0xAC 328 #define RK3568_SMART_REGION3_ACT_INFO 0xB0 329 #define RK3568_SMART_REGION3_DSP_INFO 0xB4 330 #define RK3568_SMART_REGION3_DSP_ST 0xB8 331 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0 332 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 333 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 334 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC 335 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0 336 337 /* HDR register definition */ 338 #define RK3568_HDR_LUT_CTRL 0x2000 339 #define RK3568_HDR_LUT_MST 0x2004 340 #define RK3568_SDR2HDR_CTRL 0x2010 341 #define RK3568_HDR2SDR_CTRL 0x2020 342 #define RK3568_HDR2SDR_SRC_RANGE 0x2024 343 #define RK3568_HDR2SDR_NORMFACEETF 0x2028 344 #define RK3568_HDR2SDR_DST_RANGE 0x202C 345 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 346 #define RK3568_HDR_EETF_OETF_Y0 0x203C 347 #define RK3568_HDR_SAT_Y0 0x20C0 348 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 349 #define RK3568_HDR_OETF_DX_POW1 0x2200 350 #define RK3568_HDR_OETF_XN1 0x2300 351 352 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) 353 354 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31) 355 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) 356 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) 357 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) 358 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) 359 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) 360 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) 361 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) 362 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) 363 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) 364 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) 365 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) 366 367 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) 368 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) 369 370 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) 371 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) 372 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 373 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) 374 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) 375 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) 376 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) 377 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) 378 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) 379 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) 380 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) 381 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) 382 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) 383 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) 384 385 #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) 386 #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) 387 #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) 388 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) 389 390 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) 391 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) 392 393 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) 394 395 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) 396 397 #define VOP2_SYS_AXI_BUS_NUM 2 398 399 #define VOP2_CLUSTER_YUV444_10 0x12 400 401 #define VOP2_COLOR_KEY_MASK BIT(31) 402 403 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) 404 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) 405 406 #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) 407 408 #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) 409 #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) 410 #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) 411 #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) 412 #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) 413 #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) 414 #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) 415 #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) 416 #define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) 417 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) 418 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) 419 420 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) 421 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) 422 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) 423 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) 424 425 #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) 426 #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) 427 #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) 428 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) 429 430 #define VP_INT_DSP_HOLD_VALID BIT(6) 431 #define VP_INT_FS_FIELD BIT(5) 432 #define VP_INT_POST_BUF_EMPTY BIT(4) 433 #define VP_INT_LINE_FLAG1 BIT(3) 434 #define VP_INT_LINE_FLAG0 BIT(2) 435 #define VOP2_INT_BUS_ERRPR BIT(1) 436 #define VP_INT_FS BIT(0) 437 438 #define POLFLAG_DCLK_INV BIT(3) 439 440 enum vop2_layer_phy_id { 441 ROCKCHIP_VOP2_CLUSTER0 = 0, 442 ROCKCHIP_VOP2_CLUSTER1, 443 ROCKCHIP_VOP2_ESMART0, 444 ROCKCHIP_VOP2_ESMART1, 445 ROCKCHIP_VOP2_SMART0, 446 ROCKCHIP_VOP2_SMART1, 447 ROCKCHIP_VOP2_CLUSTER2, 448 ROCKCHIP_VOP2_CLUSTER3, 449 ROCKCHIP_VOP2_ESMART2, 450 ROCKCHIP_VOP2_ESMART3, 451 ROCKCHIP_VOP2_PHY_ID_INVALID = -1, 452 }; 453 454 extern const struct component_ops vop2_component_ops; 455 456 #endif /* _ROCKCHIP_DRM_VOP2_H */ 457