1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_DRM_VOP2_H 8 #define _ROCKCHIP_DRM_VOP2_H 9 10 #include "rockchip_drm_vop.h" 11 12 #include <linux/regmap.h> 13 #include <drm/drm_modes.h> 14 15 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 16 17 #define WIN_FEATURE_AFBDC BIT(0) 18 #define WIN_FEATURE_CLUSTER BIT(1) 19 20 /* 21 * the delay number of a window in different mode. 22 */ 23 enum win_dly_mode { 24 VOP2_DLY_MODE_DEFAULT, /**< default mode */ 25 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ 26 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ 27 VOP2_DLY_MODE_MAX, 28 }; 29 30 struct vop_rect { 31 int width; 32 int height; 33 }; 34 35 enum vop2_scale_up_mode { 36 VOP2_SCALE_UP_NRST_NBOR, 37 VOP2_SCALE_UP_BIL, 38 VOP2_SCALE_UP_BIC, 39 }; 40 41 enum vop2_scale_down_mode { 42 VOP2_SCALE_DOWN_NRST_NBOR, 43 VOP2_SCALE_DOWN_BIL, 44 VOP2_SCALE_DOWN_AVG, 45 }; 46 47 enum vop2_win_regs { 48 VOP2_WIN_ENABLE, 49 VOP2_WIN_FORMAT, 50 VOP2_WIN_CSC_MODE, 51 VOP2_WIN_XMIRROR, 52 VOP2_WIN_YMIRROR, 53 VOP2_WIN_RB_SWAP, 54 VOP2_WIN_UV_SWAP, 55 VOP2_WIN_ACT_INFO, 56 VOP2_WIN_DSP_INFO, 57 VOP2_WIN_DSP_ST, 58 VOP2_WIN_YRGB_MST, 59 VOP2_WIN_UV_MST, 60 VOP2_WIN_YRGB_VIR, 61 VOP2_WIN_UV_VIR, 62 VOP2_WIN_YUV_CLIP, 63 VOP2_WIN_Y2R_EN, 64 VOP2_WIN_R2Y_EN, 65 VOP2_WIN_COLOR_KEY, 66 VOP2_WIN_COLOR_KEY_EN, 67 VOP2_WIN_DITHER_UP, 68 69 /* scale regs */ 70 VOP2_WIN_SCALE_YRGB_X, 71 VOP2_WIN_SCALE_YRGB_Y, 72 VOP2_WIN_SCALE_CBCR_X, 73 VOP2_WIN_SCALE_CBCR_Y, 74 VOP2_WIN_YRGB_HOR_SCL_MODE, 75 VOP2_WIN_YRGB_HSCL_FILTER_MODE, 76 VOP2_WIN_YRGB_VER_SCL_MODE, 77 VOP2_WIN_YRGB_VSCL_FILTER_MODE, 78 VOP2_WIN_CBCR_VER_SCL_MODE, 79 VOP2_WIN_CBCR_HSCL_FILTER_MODE, 80 VOP2_WIN_CBCR_HOR_SCL_MODE, 81 VOP2_WIN_CBCR_VSCL_FILTER_MODE, 82 VOP2_WIN_VSD_CBCR_GT2, 83 VOP2_WIN_VSD_CBCR_GT4, 84 VOP2_WIN_VSD_YRGB_GT2, 85 VOP2_WIN_VSD_YRGB_GT4, 86 VOP2_WIN_BIC_COE_SEL, 87 88 /* cluster regs */ 89 VOP2_WIN_CLUSTER_ENABLE, 90 VOP2_WIN_AFBC_ENABLE, 91 VOP2_WIN_CLUSTER_LB_MODE, 92 93 /* afbc regs */ 94 VOP2_WIN_AFBC_FORMAT, 95 VOP2_WIN_AFBC_RB_SWAP, 96 VOP2_WIN_AFBC_UV_SWAP, 97 VOP2_WIN_AFBC_AUTO_GATING_EN, 98 VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 99 VOP2_WIN_AFBC_PIC_VIR_WIDTH, 100 VOP2_WIN_AFBC_TILE_NUM, 101 VOP2_WIN_AFBC_PIC_OFFSET, 102 VOP2_WIN_AFBC_PIC_SIZE, 103 VOP2_WIN_AFBC_DSP_OFFSET, 104 VOP2_WIN_AFBC_TRANSFORM_OFFSET, 105 VOP2_WIN_AFBC_HDR_PTR, 106 VOP2_WIN_AFBC_HALF_BLOCK_EN, 107 VOP2_WIN_AFBC_ROTATE_270, 108 VOP2_WIN_AFBC_ROTATE_90, 109 VOP2_WIN_MAX_REG, 110 }; 111 112 struct vop2_win_data { 113 const char *name; 114 unsigned int phys_id; 115 116 u32 base; 117 enum drm_plane_type type; 118 119 u32 nformats; 120 const u32 *formats; 121 const uint64_t *format_modifiers; 122 const unsigned int supported_rotations; 123 124 /** 125 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 126 */ 127 unsigned int layer_sel_id; 128 uint64_t feature; 129 130 unsigned int max_upscale_factor; 131 unsigned int max_downscale_factor; 132 const u8 dly[VOP2_DLY_MODE_MAX]; 133 }; 134 135 struct vop2_video_port_data { 136 unsigned int id; 137 u32 feature; 138 u16 gamma_lut_len; 139 u16 cubic_lut_len; 140 struct vop_rect max_output; 141 const u8 pre_scan_max_dly[4]; 142 const struct vop2_video_port_regs *regs; 143 unsigned int offset; 144 }; 145 146 struct vop2_data { 147 u8 nr_vps; 148 const struct vop2_ctrl *ctrl; 149 const struct vop2_win_data *win; 150 const struct vop2_video_port_data *vp; 151 const struct vop_csc_table *csc_table; 152 struct vop_rect max_input; 153 struct vop_rect max_output; 154 155 unsigned int win_size; 156 unsigned int soc_id; 157 }; 158 159 /* interrupt define */ 160 #define FS_NEW_INTR BIT(4) 161 #define ADDR_SAME_INTR BIT(5) 162 #define LINE_FLAG1_INTR BIT(6) 163 #define WIN0_EMPTY_INTR BIT(7) 164 #define WIN1_EMPTY_INTR BIT(8) 165 #define WIN2_EMPTY_INTR BIT(9) 166 #define WIN3_EMPTY_INTR BIT(10) 167 #define HWC_EMPTY_INTR BIT(11) 168 #define POST_BUF_EMPTY_INTR BIT(12) 169 #define PWM_GEN_INTR BIT(13) 170 #define DMA_FINISH_INTR BIT(14) 171 #define FS_FIELD_INTR BIT(15) 172 #define FE_INTR BIT(16) 173 #define WB_UV_FIFO_FULL_INTR BIT(17) 174 #define WB_YRGB_FIFO_FULL_INTR BIT(18) 175 #define WB_COMPLETE_INTR BIT(19) 176 177 /* 178 * display output interface supported by rockchip lcdc 179 */ 180 #define ROCKCHIP_OUT_MODE_P888 0 181 #define ROCKCHIP_OUT_MODE_BT1120 0 182 #define ROCKCHIP_OUT_MODE_P666 1 183 #define ROCKCHIP_OUT_MODE_P565 2 184 #define ROCKCHIP_OUT_MODE_BT656 5 185 #define ROCKCHIP_OUT_MODE_S888 8 186 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 187 #define ROCKCHIP_OUT_MODE_YUV420 14 188 /* for use special outface */ 189 #define ROCKCHIP_OUT_MODE_AAAA 15 190 191 enum vop_csc_format { 192 CSC_BT601L, 193 CSC_BT709L, 194 CSC_BT601F, 195 CSC_BT2020, 196 }; 197 198 enum src_factor_mode { 199 SRC_FAC_ALPHA_ZERO, 200 SRC_FAC_ALPHA_ONE, 201 SRC_FAC_ALPHA_DST, 202 SRC_FAC_ALPHA_DST_INVERSE, 203 SRC_FAC_ALPHA_SRC, 204 SRC_FAC_ALPHA_SRC_GLOBAL, 205 }; 206 207 enum dst_factor_mode { 208 DST_FAC_ALPHA_ZERO, 209 DST_FAC_ALPHA_ONE, 210 DST_FAC_ALPHA_SRC, 211 DST_FAC_ALPHA_SRC_INVERSE, 212 DST_FAC_ALPHA_DST, 213 DST_FAC_ALPHA_DST_GLOBAL, 214 }; 215 216 #define RK3568_GRF_VO_CON1 0x0364 217 /* System registers definition */ 218 #define RK3568_REG_CFG_DONE 0x000 219 #define RK3568_VERSION_INFO 0x004 220 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 221 #define RK3568_SYS_AXI_LUT_CTRL 0x024 222 #define RK3568_DSP_IF_EN 0x028 223 #define RK3568_DSP_IF_CTRL 0x02c 224 #define RK3568_DSP_IF_POL 0x030 225 #define RK3568_WB_CTRL 0x40 226 #define RK3568_WB_XSCAL_FACTOR 0x44 227 #define RK3568_WB_YRGB_MST 0x48 228 #define RK3568_WB_CBR_MST 0x4C 229 #define RK3568_OTP_WIN_EN 0x050 230 #define RK3568_LUT_PORT_SEL 0x058 231 #define RK3568_SYS_STATUS0 0x060 232 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) 233 #define RK3568_SYS0_INT_EN 0x80 234 #define RK3568_SYS0_INT_CLR 0x84 235 #define RK3568_SYS0_INT_STATUS 0x88 236 #define RK3568_SYS1_INT_EN 0x90 237 #define RK3568_SYS1_INT_CLR 0x94 238 #define RK3568_SYS1_INT_STATUS 0x98 239 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) 240 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) 241 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) 242 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) 243 244 /* Video Port registers definition */ 245 #define RK3568_VP_DSP_CTRL 0x00 246 #define RK3568_VP_MIPI_CTRL 0x04 247 #define RK3568_VP_COLOR_BAR_CTRL 0x08 248 #define RK3568_VP_3D_LUT_CTRL 0x10 249 #define RK3568_VP_3D_LUT_MST 0x20 250 #define RK3568_VP_DSP_BG 0x2C 251 #define RK3568_VP_PRE_SCAN_HTIMING 0x30 252 #define RK3568_VP_POST_DSP_HACT_INFO 0x34 253 #define RK3568_VP_POST_DSP_VACT_INFO 0x38 254 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C 255 #define RK3568_VP_POST_SCL_CTRL 0x40 256 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 257 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48 258 #define RK3568_VP_DSP_HACT_ST_END 0x4C 259 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50 260 #define RK3568_VP_DSP_VACT_ST_END 0x54 261 #define RK3568_VP_DSP_VS_ST_END_F1 0x58 262 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C 263 #define RK3568_VP_BCSH_CTRL 0x60 264 #define RK3568_VP_BCSH_BCS 0x64 265 #define RK3568_VP_BCSH_H 0x68 266 #define RK3568_VP_BCSH_COLOR_BAR 0x6C 267 268 /* Overlay registers definition */ 269 #define RK3568_OVL_CTRL 0x600 270 #define RK3568_OVL_LAYER_SEL 0x604 271 #define RK3568_OVL_PORT_SEL 0x608 272 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 273 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 274 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 275 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 276 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 277 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 278 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 279 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 280 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 281 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 282 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 283 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 284 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) 285 #define RK3568_CLUSTER_DLY_NUM 0x6F0 286 #define RK3568_SMART_DLY_NUM 0x6F8 287 288 /* Cluster register definition, offset relative to window base */ 289 #define RK3568_CLUSTER_WIN_CTRL0 0x00 290 #define RK3568_CLUSTER_WIN_CTRL1 0x04 291 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10 292 #define RK3568_CLUSTER_WIN_CBR_MST 0x14 293 #define RK3568_CLUSTER_WIN_VIR 0x18 294 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20 295 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24 296 #define RK3568_CLUSTER_WIN_DSP_ST 0x28 297 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 298 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C 299 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 300 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 301 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 302 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C 303 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 304 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 305 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 306 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C 307 308 #define RK3568_CLUSTER_CTRL 0x100 309 310 /* (E)smart register definition, offset relative to window base */ 311 #define RK3568_SMART_CTRL0 0x00 312 #define RK3568_SMART_CTRL1 0x04 313 #define RK3568_SMART_REGION0_CTRL 0x10 314 #define RK3568_SMART_REGION0_YRGB_MST 0x14 315 #define RK3568_SMART_REGION0_CBR_MST 0x18 316 #define RK3568_SMART_REGION0_VIR 0x1C 317 #define RK3568_SMART_REGION0_ACT_INFO 0x20 318 #define RK3568_SMART_REGION0_DSP_INFO 0x24 319 #define RK3568_SMART_REGION0_DSP_ST 0x28 320 #define RK3568_SMART_REGION0_SCL_CTRL 0x30 321 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 322 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 323 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C 324 #define RK3568_SMART_REGION1_CTRL 0x40 325 #define RK3568_SMART_REGION1_YRGB_MST 0x44 326 #define RK3568_SMART_REGION1_CBR_MST 0x48 327 #define RK3568_SMART_REGION1_VIR 0x4C 328 #define RK3568_SMART_REGION1_ACT_INFO 0x50 329 #define RK3568_SMART_REGION1_DSP_INFO 0x54 330 #define RK3568_SMART_REGION1_DSP_ST 0x58 331 #define RK3568_SMART_REGION1_SCL_CTRL 0x60 332 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 333 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 334 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C 335 #define RK3568_SMART_REGION2_CTRL 0x70 336 #define RK3568_SMART_REGION2_YRGB_MST 0x74 337 #define RK3568_SMART_REGION2_CBR_MST 0x78 338 #define RK3568_SMART_REGION2_VIR 0x7C 339 #define RK3568_SMART_REGION2_ACT_INFO 0x80 340 #define RK3568_SMART_REGION2_DSP_INFO 0x84 341 #define RK3568_SMART_REGION2_DSP_ST 0x88 342 #define RK3568_SMART_REGION2_SCL_CTRL 0x90 343 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 344 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 345 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C 346 #define RK3568_SMART_REGION3_CTRL 0xA0 347 #define RK3568_SMART_REGION3_YRGB_MST 0xA4 348 #define RK3568_SMART_REGION3_CBR_MST 0xA8 349 #define RK3568_SMART_REGION3_VIR 0xAC 350 #define RK3568_SMART_REGION3_ACT_INFO 0xB0 351 #define RK3568_SMART_REGION3_DSP_INFO 0xB4 352 #define RK3568_SMART_REGION3_DSP_ST 0xB8 353 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0 354 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 355 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 356 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC 357 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0 358 359 /* HDR register definition */ 360 #define RK3568_HDR_LUT_CTRL 0x2000 361 #define RK3568_HDR_LUT_MST 0x2004 362 #define RK3568_SDR2HDR_CTRL 0x2010 363 #define RK3568_HDR2SDR_CTRL 0x2020 364 #define RK3568_HDR2SDR_SRC_RANGE 0x2024 365 #define RK3568_HDR2SDR_NORMFACEETF 0x2028 366 #define RK3568_HDR2SDR_DST_RANGE 0x202C 367 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 368 #define RK3568_HDR_EETF_OETF_Y0 0x203C 369 #define RK3568_HDR_SAT_Y0 0x20C0 370 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 371 #define RK3568_HDR_OETF_DX_POW1 0x2200 372 #define RK3568_HDR_OETF_XN1 0x2300 373 374 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) 375 376 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31) 377 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) 378 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) 379 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) 380 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) 381 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) 382 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) 383 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) 384 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) 385 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) 386 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) 387 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) 388 389 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) 390 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) 391 392 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) 393 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) 394 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) 395 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) 396 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) 397 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) 398 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) 399 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) 400 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) 401 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) 402 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) 403 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) 404 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) 405 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) 406 407 #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) 408 #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) 409 #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) 410 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) 411 412 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) 413 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) 414 415 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) 416 417 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) 418 419 #define VOP2_SYS_AXI_BUS_NUM 2 420 421 #define VOP2_CLUSTER_YUV444_10 0x12 422 423 #define VOP2_COLOR_KEY_MASK BIT(31) 424 425 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) 426 427 #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) 428 429 #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) 430 #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) 431 #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) 432 #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) 433 #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) 434 #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) 435 #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) 436 #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) 437 #define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) 438 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) 439 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) 440 441 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) 442 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) 443 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) 444 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) 445 446 #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) 447 #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) 448 #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) 449 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) 450 451 #define VP_INT_DSP_HOLD_VALID BIT(6) 452 #define VP_INT_FS_FIELD BIT(5) 453 #define VP_INT_POST_BUF_EMPTY BIT(4) 454 #define VP_INT_LINE_FLAG1 BIT(3) 455 #define VP_INT_LINE_FLAG0 BIT(2) 456 #define VOP2_INT_BUS_ERRPR BIT(1) 457 #define VP_INT_FS BIT(0) 458 459 #define POLFLAG_DCLK_INV BIT(3) 460 461 enum vop2_layer_phy_id { 462 ROCKCHIP_VOP2_CLUSTER0 = 0, 463 ROCKCHIP_VOP2_CLUSTER1, 464 ROCKCHIP_VOP2_ESMART0, 465 ROCKCHIP_VOP2_ESMART1, 466 ROCKCHIP_VOP2_SMART0, 467 ROCKCHIP_VOP2_SMART1, 468 ROCKCHIP_VOP2_CLUSTER2, 469 ROCKCHIP_VOP2_CLUSTER3, 470 ROCKCHIP_VOP2_ESMART2, 471 ROCKCHIP_VOP2_ESMART3, 472 ROCKCHIP_VOP2_PHY_ID_INVALID = -1, 473 }; 474 475 extern const struct component_ops vop2_component_ops; 476 477 #endif /* _ROCKCHIP_DRM_VOP2_H */ 478