1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/swab.h> 21 22 #include <drm/drm.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_uapi.h> 25 #include <drm/drm_blend.h> 26 #include <drm/drm_crtc.h> 27 #include <linux/debugfs.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_flip_work.h> 30 #include <drm/drm_framebuffer.h> 31 #include <drm/drm_gem_framebuffer_helper.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <uapi/linux/videodev2.h> 36 37 #include "rockchip_drm_gem.h" 38 #include "rockchip_drm_vop2.h" 39 #include "rockchip_rgb.h" 40 41 /* 42 * VOP2 architecture 43 * 44 +----------+ +-------------+ +-----------+ 45 | Cluster | | Sel 1 from 6| | 1 from 3 | 46 | window0 | | Layer0 | | RGB | 47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+ 48 +----------+ +-------------+ |N from 6 layers| | | 49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ 50 | window1 | | Layer1 | | | | | | 1 from 3 | 51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS | 52 +----------+ +-------------+ +-----------+ 53 | Esmart | | Sel 1 from 6| 54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ 55 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | 56 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | 57 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ 58 | Window1 | | Layer3 | +---------------+ +-------------+ 59 +----------+ +-------------+ +-----------+ 60 +----------+ +-------------+ | 1 from 3 | 61 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | 62 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ 63 +----------+ +-------------+ | Overlay2 +--->| Video Port2 | 64 +----------+ +-------------+ | | | | +-----------+ 65 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | 66 | Window1 | | Layer5 | | eDP | 67 +----------+ +-------------+ +-----------+ 68 * 69 */ 70 71 enum vop2_data_format { 72 VOP2_FMT_ARGB8888 = 0, 73 VOP2_FMT_RGB888, 74 VOP2_FMT_RGB565, 75 VOP2_FMT_XRGB101010, 76 VOP2_FMT_YUV420SP, 77 VOP2_FMT_YUV422SP, 78 VOP2_FMT_YUV444SP, 79 VOP2_FMT_YUYV422 = 8, 80 VOP2_FMT_YUYV420, 81 VOP2_FMT_VYUY422, 82 VOP2_FMT_VYUY420, 83 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, 84 VOP2_FMT_YUV420SP_TILE_16x2, 85 VOP2_FMT_YUV422SP_TILE_8x4, 86 VOP2_FMT_YUV422SP_TILE_16x2, 87 VOP2_FMT_YUV420SP_10, 88 VOP2_FMT_YUV422SP_10, 89 VOP2_FMT_YUV444SP_10, 90 }; 91 92 enum vop2_afbc_format { 93 VOP2_AFBC_FMT_RGB565, 94 VOP2_AFBC_FMT_ARGB2101010 = 2, 95 VOP2_AFBC_FMT_YUV420_10BIT, 96 VOP2_AFBC_FMT_RGB888, 97 VOP2_AFBC_FMT_ARGB8888, 98 VOP2_AFBC_FMT_YUV420 = 9, 99 VOP2_AFBC_FMT_YUV422 = 0xb, 100 VOP2_AFBC_FMT_YUV422_10BIT = 0xe, 101 VOP2_AFBC_FMT_INVALID = -1, 102 }; 103 104 #define VOP2_MAX_DCLK_RATE 600000000 105 106 /* 107 * bus-format types. 108 */ 109 struct drm_bus_format_enum_list { 110 int type; 111 const char *name; 112 }; 113 114 static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = { 115 { DRM_MODE_CONNECTOR_Unknown, "Unknown" }, 116 { MEDIA_BUS_FMT_RGB565_1X16, "RGB565_1X16" }, 117 { MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" }, 118 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" }, 119 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" }, 120 { MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" }, 121 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" }, 122 { MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" }, 123 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" }, 124 { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" }, 125 { MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" }, 126 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" }, 127 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" }, 128 { MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" }, 129 { MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" }, 130 { MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" }, 131 { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" }, 132 { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" }, 133 }; 134 135 static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list) 136 137 static const struct regmap_config vop2_regmap_config; 138 139 static void vop2_lock(struct vop2 *vop2) 140 { 141 mutex_lock(&vop2->vop2_lock); 142 } 143 144 static void vop2_unlock(struct vop2 *vop2) 145 { 146 mutex_unlock(&vop2->vop2_lock); 147 } 148 149 static void vop2_win_disable(struct vop2_win *win) 150 { 151 vop2_win_write(win, VOP2_WIN_ENABLE, 0); 152 153 if (vop2_cluster_window(win)) 154 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); 155 } 156 157 static u32 vop2_get_bpp(const struct drm_format_info *format) 158 { 159 switch (format->format) { 160 case DRM_FORMAT_YUV420_8BIT: 161 return 12; 162 case DRM_FORMAT_YUV420_10BIT: 163 return 15; 164 case DRM_FORMAT_VUY101010: 165 return 30; 166 default: 167 return drm_format_info_bpp(format, 0); 168 } 169 } 170 171 static enum vop2_data_format vop2_convert_format(u32 format) 172 { 173 switch (format) { 174 case DRM_FORMAT_XRGB2101010: 175 case DRM_FORMAT_ARGB2101010: 176 case DRM_FORMAT_XBGR2101010: 177 case DRM_FORMAT_ABGR2101010: 178 return VOP2_FMT_XRGB101010; 179 case DRM_FORMAT_XRGB8888: 180 case DRM_FORMAT_ARGB8888: 181 case DRM_FORMAT_XBGR8888: 182 case DRM_FORMAT_ABGR8888: 183 return VOP2_FMT_ARGB8888; 184 case DRM_FORMAT_RGB888: 185 case DRM_FORMAT_BGR888: 186 return VOP2_FMT_RGB888; 187 case DRM_FORMAT_RGB565: 188 case DRM_FORMAT_BGR565: 189 return VOP2_FMT_RGB565; 190 case DRM_FORMAT_NV12: 191 case DRM_FORMAT_NV21: 192 case DRM_FORMAT_YUV420_8BIT: 193 return VOP2_FMT_YUV420SP; 194 case DRM_FORMAT_NV15: 195 case DRM_FORMAT_YUV420_10BIT: 196 return VOP2_FMT_YUV420SP_10; 197 case DRM_FORMAT_NV16: 198 case DRM_FORMAT_NV61: 199 return VOP2_FMT_YUV422SP; 200 case DRM_FORMAT_NV20: 201 case DRM_FORMAT_Y210: 202 return VOP2_FMT_YUV422SP_10; 203 case DRM_FORMAT_NV24: 204 case DRM_FORMAT_NV42: 205 return VOP2_FMT_YUV444SP; 206 case DRM_FORMAT_NV30: 207 return VOP2_FMT_YUV444SP_10; 208 case DRM_FORMAT_YUYV: 209 case DRM_FORMAT_YVYU: 210 return VOP2_FMT_VYUY422; 211 case DRM_FORMAT_VYUY: 212 case DRM_FORMAT_UYVY: 213 return VOP2_FMT_YUYV422; 214 default: 215 DRM_ERROR("unsupported format[%08x]\n", format); 216 return -EINVAL; 217 } 218 } 219 220 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) 221 { 222 switch (format) { 223 case DRM_FORMAT_XRGB2101010: 224 case DRM_FORMAT_ARGB2101010: 225 case DRM_FORMAT_XBGR2101010: 226 case DRM_FORMAT_ABGR2101010: 227 return VOP2_AFBC_FMT_ARGB2101010; 228 case DRM_FORMAT_XRGB8888: 229 case DRM_FORMAT_ARGB8888: 230 case DRM_FORMAT_XBGR8888: 231 case DRM_FORMAT_ABGR8888: 232 return VOP2_AFBC_FMT_ARGB8888; 233 case DRM_FORMAT_RGB888: 234 case DRM_FORMAT_BGR888: 235 return VOP2_AFBC_FMT_RGB888; 236 case DRM_FORMAT_RGB565: 237 case DRM_FORMAT_BGR565: 238 return VOP2_AFBC_FMT_RGB565; 239 case DRM_FORMAT_YUV420_8BIT: 240 return VOP2_AFBC_FMT_YUV420; 241 case DRM_FORMAT_YUV420_10BIT: 242 return VOP2_AFBC_FMT_YUV420_10BIT; 243 case DRM_FORMAT_YVYU: 244 case DRM_FORMAT_YUYV: 245 case DRM_FORMAT_VYUY: 246 case DRM_FORMAT_UYVY: 247 return VOP2_AFBC_FMT_YUV422; 248 case DRM_FORMAT_Y210: 249 return VOP2_AFBC_FMT_YUV422_10BIT; 250 default: 251 return VOP2_AFBC_FMT_INVALID; 252 } 253 254 return VOP2_AFBC_FMT_INVALID; 255 } 256 257 static bool vop2_win_rb_swap(u32 format) 258 { 259 switch (format) { 260 case DRM_FORMAT_XBGR2101010: 261 case DRM_FORMAT_ABGR2101010: 262 case DRM_FORMAT_XBGR8888: 263 case DRM_FORMAT_ABGR8888: 264 case DRM_FORMAT_BGR888: 265 case DRM_FORMAT_BGR565: 266 return true; 267 default: 268 return false; 269 } 270 } 271 272 static bool vop2_afbc_uv_swap(u32 format) 273 { 274 switch (format) { 275 case DRM_FORMAT_YUYV: 276 case DRM_FORMAT_Y210: 277 case DRM_FORMAT_YUV420_8BIT: 278 case DRM_FORMAT_YUV420_10BIT: 279 return true; 280 default: 281 return false; 282 } 283 } 284 285 static bool vop2_win_uv_swap(u32 format) 286 { 287 switch (format) { 288 case DRM_FORMAT_NV12: 289 case DRM_FORMAT_NV16: 290 case DRM_FORMAT_NV24: 291 case DRM_FORMAT_NV15: 292 case DRM_FORMAT_NV20: 293 case DRM_FORMAT_NV30: 294 case DRM_FORMAT_YUYV: 295 case DRM_FORMAT_UYVY: 296 return true; 297 default: 298 return false; 299 } 300 } 301 302 static bool vop2_win_dither_up(u32 format) 303 { 304 switch (format) { 305 case DRM_FORMAT_BGR565: 306 case DRM_FORMAT_RGB565: 307 return true; 308 default: 309 return false; 310 } 311 } 312 313 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) 314 { 315 /* 316 * FIXME: 317 * 318 * There is no media type for YUV444 output, 319 * so when out_mode is AAAA or P888, assume output is YUV444 on 320 * yuv format. 321 * 322 * From H/W testing, YUV444 mode need a rb swap. 323 */ 324 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 325 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 326 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 327 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 328 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 329 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 330 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 331 output_mode == ROCKCHIP_OUT_MODE_P888))) 332 return true; 333 else 334 return false; 335 } 336 337 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format) 338 { 339 if (vop2->version == VOP_VERSION_RK3588) { 340 if (bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 341 bus_format == MEDIA_BUS_FMT_YUV10_1X30) 342 return true; 343 } 344 345 return false; 346 } 347 348 static bool is_yuv_output(u32 bus_format) 349 { 350 switch (bus_format) { 351 case MEDIA_BUS_FMT_YUV8_1X24: 352 case MEDIA_BUS_FMT_YUV10_1X30: 353 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 354 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 355 case MEDIA_BUS_FMT_YUYV8_2X8: 356 case MEDIA_BUS_FMT_YVYU8_2X8: 357 case MEDIA_BUS_FMT_UYVY8_2X8: 358 case MEDIA_BUS_FMT_VYUY8_2X8: 359 case MEDIA_BUS_FMT_YUYV8_1X16: 360 case MEDIA_BUS_FMT_YVYU8_1X16: 361 case MEDIA_BUS_FMT_UYVY8_1X16: 362 case MEDIA_BUS_FMT_VYUY8_1X16: 363 return true; 364 default: 365 return false; 366 } 367 } 368 369 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) 370 { 371 int i; 372 373 if (modifier == DRM_FORMAT_MOD_LINEAR) 374 return false; 375 376 for (i = 0 ; i < plane->modifier_count; i++) 377 if (plane->modifiers[i] == modifier) 378 return true; 379 380 return false; 381 } 382 383 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, 384 u64 modifier) 385 { 386 struct vop2_win *win = to_vop2_win(plane); 387 struct vop2 *vop2 = win->vop2; 388 389 if (modifier == DRM_FORMAT_MOD_INVALID) 390 return false; 391 392 if (vop2->version == VOP_VERSION_RK3568) { 393 if (vop2_cluster_window(win)) { 394 if (modifier == DRM_FORMAT_MOD_LINEAR) { 395 drm_dbg_kms(vop2->drm, 396 "Cluster window only supports format with afbc\n"); 397 return false; 398 } 399 } 400 } 401 402 if (format == DRM_FORMAT_XRGB2101010 || format == DRM_FORMAT_XBGR2101010) { 403 if (vop2->version == VOP_VERSION_RK3588) { 404 if (!rockchip_afbc(plane, modifier)) { 405 drm_dbg_kms(vop2->drm, "Only support 32 bpp format with afbc\n"); 406 return false; 407 } 408 } 409 } 410 411 if (modifier == DRM_FORMAT_MOD_LINEAR) 412 return true; 413 414 if (!rockchip_afbc(plane, modifier)) { 415 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n", 416 modifier); 417 418 return false; 419 } 420 421 return vop2_convert_afbc_format(format) >= 0; 422 } 423 424 /* 425 * 0: Full mode, 16 lines for one tail 426 * 1: half block mode, 8 lines one tail 427 */ 428 static bool vop2_half_block_enable(struct drm_plane_state *pstate) 429 { 430 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) 431 return false; 432 else 433 return true; 434 } 435 436 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, 437 bool afbc_half_block_en) 438 { 439 struct drm_rect *src = &pstate->src; 440 struct drm_framebuffer *fb = pstate->fb; 441 u32 bpp = vop2_get_bpp(fb->format); 442 u32 vir_width = (fb->pitches[0] << 3) / bpp; 443 u32 width = drm_rect_width(src) >> 16; 444 u32 height = drm_rect_height(src) >> 16; 445 u32 act_xoffset = src->x1 >> 16; 446 u32 act_yoffset = src->y1 >> 16; 447 u32 align16_crop = 0; 448 u32 align64_crop = 0; 449 u32 height_tmp; 450 u8 tx, ty; 451 u8 bottom_crop_line_num = 0; 452 453 /* 16 pixel align */ 454 if (height & 0xf) 455 align16_crop = 16 - (height & 0xf); 456 457 height_tmp = height + align16_crop; 458 459 /* 64 pixel align */ 460 if (height_tmp & 0x3f) 461 align64_crop = 64 - (height_tmp & 0x3f); 462 463 bottom_crop_line_num = align16_crop + align64_crop; 464 465 switch (pstate->rotation & 466 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | 467 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { 468 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: 469 tx = 16 - ((act_xoffset + width) & 0xf); 470 ty = bottom_crop_line_num - act_yoffset; 471 break; 472 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: 473 tx = bottom_crop_line_num - act_yoffset; 474 ty = vir_width - width - act_xoffset; 475 break; 476 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: 477 tx = act_yoffset; 478 ty = act_xoffset; 479 break; 480 case DRM_MODE_REFLECT_X: 481 tx = 16 - ((act_xoffset + width) & 0xf); 482 ty = act_yoffset; 483 break; 484 case DRM_MODE_REFLECT_Y: 485 tx = act_xoffset; 486 ty = bottom_crop_line_num - act_yoffset; 487 break; 488 case DRM_MODE_ROTATE_90: 489 tx = bottom_crop_line_num - act_yoffset; 490 ty = act_xoffset; 491 break; 492 case DRM_MODE_ROTATE_270: 493 tx = act_yoffset; 494 ty = vir_width - width - act_xoffset; 495 break; 496 case 0: 497 tx = act_xoffset; 498 ty = act_yoffset; 499 break; 500 } 501 502 if (afbc_half_block_en) 503 ty &= 0x7f; 504 505 #define TRANSFORM_XOFFSET GENMASK(7, 0) 506 #define TRANSFORM_YOFFSET GENMASK(23, 16) 507 return FIELD_PREP(TRANSFORM_XOFFSET, tx) | 508 FIELD_PREP(TRANSFORM_YOFFSET, ty); 509 } 510 511 /* 512 * A Cluster window has 2048 x 16 line buffer, which can 513 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. 514 * for Cluster_lb_mode register: 515 * 0: half mode, for plane input width range 2048 ~ 4096 516 * 1: half mode, for cluster work at 2 * 2048 plane mode 517 * 2: half mode, for rotate_90/270 mode 518 * 519 */ 520 static int vop2_get_cluster_lb_mode(struct vop2_win *win, 521 struct drm_plane_state *pstate) 522 { 523 if ((pstate->rotation & DRM_MODE_ROTATE_270) || 524 (pstate->rotation & DRM_MODE_ROTATE_90)) 525 return 2; 526 else 527 return 0; 528 } 529 530 static u16 vop2_scale_factor(u32 src, u32 dst) 531 { 532 u32 fac; 533 int shift; 534 535 if (src == dst) 536 return 0; 537 538 if (dst < 2) 539 return U16_MAX; 540 541 if (src < 2) 542 return 0; 543 544 if (src > dst) 545 shift = 12; 546 else 547 shift = 16; 548 549 src--; 550 dst--; 551 552 fac = DIV_ROUND_UP(src << shift, dst) - 1; 553 554 if (fac > U16_MAX) 555 return U16_MAX; 556 557 return fac; 558 } 559 560 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, 561 u32 src_w, u32 src_h, u32 dst_w, 562 u32 dst_h, u32 pixel_format) 563 { 564 const struct drm_format_info *info; 565 u16 hor_scl_mode, ver_scl_mode; 566 u16 hscl_filter_mode, vscl_filter_mode; 567 uint16_t cbcr_src_w = src_w; 568 uint16_t cbcr_src_h = src_h; 569 u8 gt2 = 0; 570 u8 gt4 = 0; 571 u32 val; 572 573 info = drm_format_info(pixel_format); 574 575 if (src_h >= (4 * dst_h)) { 576 gt4 = 1; 577 src_h >>= 2; 578 } else if (src_h >= (2 * dst_h)) { 579 gt2 = 1; 580 src_h >>= 1; 581 } 582 583 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 584 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 585 586 if (hor_scl_mode == SCALE_UP) 587 hscl_filter_mode = VOP2_SCALE_UP_BIC; 588 else 589 hscl_filter_mode = VOP2_SCALE_DOWN_BIL; 590 591 if (ver_scl_mode == SCALE_UP) 592 vscl_filter_mode = VOP2_SCALE_UP_BIL; 593 else 594 vscl_filter_mode = VOP2_SCALE_DOWN_BIL; 595 596 /* 597 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 598 * at scale down mode 599 */ 600 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 601 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 602 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", 603 win->data->name, dst_w); 604 dst_w++; 605 } 606 } 607 608 val = vop2_scale_factor(src_w, dst_w); 609 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); 610 val = vop2_scale_factor(src_h, dst_h); 611 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); 612 613 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); 614 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); 615 616 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); 617 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); 618 619 if (vop2_cluster_window(win)) 620 return; 621 622 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); 623 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); 624 625 if (info->is_yuv) { 626 cbcr_src_w /= info->hsub; 627 cbcr_src_h /= info->vsub; 628 629 gt4 = 0; 630 gt2 = 0; 631 632 if (cbcr_src_h >= (4 * dst_h)) { 633 gt4 = 1; 634 cbcr_src_h >>= 2; 635 } else if (cbcr_src_h >= (2 * dst_h)) { 636 gt2 = 1; 637 cbcr_src_h >>= 1; 638 } 639 640 hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 641 ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 642 643 val = vop2_scale_factor(cbcr_src_w, dst_w); 644 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); 645 646 val = vop2_scale_factor(cbcr_src_h, dst_h); 647 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); 648 649 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); 650 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); 651 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); 652 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); 653 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); 654 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); 655 } 656 } 657 658 static int vop2_convert_csc_mode(int csc_mode) 659 { 660 switch (csc_mode) { 661 case V4L2_COLORSPACE_SMPTE170M: 662 case V4L2_COLORSPACE_470_SYSTEM_M: 663 case V4L2_COLORSPACE_470_SYSTEM_BG: 664 return CSC_BT601L; 665 case V4L2_COLORSPACE_REC709: 666 case V4L2_COLORSPACE_SMPTE240M: 667 case V4L2_COLORSPACE_DEFAULT: 668 return CSC_BT709L; 669 case V4L2_COLORSPACE_JPEG: 670 return CSC_BT601F; 671 case V4L2_COLORSPACE_BT2020: 672 return CSC_BT2020; 673 default: 674 return CSC_BT709L; 675 } 676 } 677 678 /* 679 * colorspace path: 680 * Input Win csc Output 681 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) 682 * RGB --> R2Y __/ 683 * 684 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) 685 * RGB --> 709To2020->R2Y __/ 686 * 687 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) 688 * RGB --> R2Y __/ 689 * 690 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) 691 * RGB --> 709To2020->R2Y __/ 692 * 693 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) 694 * RGB --> R2Y __/ 695 * 696 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) 697 * RGB --> R2Y(601) __/ 698 * 699 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) 700 * RGB --> bypass __/ 701 * 702 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) 703 * 704 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) 705 * 706 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) 707 * 708 * 11. RGB --> bypass --> RGB_OUTPUT(709) 709 */ 710 711 static void vop2_setup_csc_mode(struct vop2_video_port *vp, 712 struct vop2_win *win, 713 struct drm_plane_state *pstate) 714 { 715 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); 716 int is_input_yuv = pstate->fb->format->is_yuv; 717 int is_output_yuv = is_yuv_output(vcstate->bus_format); 718 int input_csc = V4L2_COLORSPACE_DEFAULT; 719 int output_csc = vcstate->color_space; 720 bool r2y_en, y2r_en; 721 int csc_mode; 722 723 if (is_input_yuv && !is_output_yuv) { 724 y2r_en = true; 725 r2y_en = false; 726 csc_mode = vop2_convert_csc_mode(input_csc); 727 } else if (!is_input_yuv && is_output_yuv) { 728 y2r_en = false; 729 r2y_en = true; 730 csc_mode = vop2_convert_csc_mode(output_csc); 731 } else { 732 y2r_en = false; 733 r2y_en = false; 734 csc_mode = false; 735 } 736 737 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); 738 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); 739 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); 740 } 741 742 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) 743 { 744 struct vop2 *vop2 = vp->vop2; 745 746 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); 747 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); 748 } 749 750 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) 751 { 752 struct vop2 *vop2 = vp->vop2; 753 754 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); 755 } 756 757 static int vop2_core_clks_prepare_enable(struct vop2 *vop2) 758 { 759 int ret; 760 761 ret = clk_prepare_enable(vop2->hclk); 762 if (ret < 0) { 763 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); 764 return ret; 765 } 766 767 ret = clk_prepare_enable(vop2->aclk); 768 if (ret < 0) { 769 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); 770 goto err; 771 } 772 773 ret = clk_prepare_enable(vop2->pclk); 774 if (ret < 0) { 775 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret); 776 goto err1; 777 } 778 779 return 0; 780 err1: 781 clk_disable_unprepare(vop2->aclk); 782 err: 783 clk_disable_unprepare(vop2->hclk); 784 785 return ret; 786 } 787 788 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) 789 { 790 u32 pd; 791 792 pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL); 793 pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 | 794 VOP2_PD_CLUSTER3 | VOP2_PD_ESMART); 795 796 vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); 797 } 798 799 static void vop2_enable(struct vop2 *vop2) 800 { 801 int ret; 802 u32 version; 803 804 ret = pm_runtime_resume_and_get(vop2->dev); 805 if (ret < 0) { 806 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); 807 return; 808 } 809 810 ret = vop2_core_clks_prepare_enable(vop2); 811 if (ret) { 812 pm_runtime_put_sync(vop2->dev); 813 return; 814 } 815 816 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); 817 if (ret) { 818 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); 819 return; 820 } 821 822 version = vop2_readl(vop2, RK3568_VERSION_INFO); 823 if (version != vop2->version) { 824 drm_err(vop2->drm, "Hardware version(0x%08x) mismatch\n", version); 825 return; 826 } 827 828 /* 829 * rk3566 share the same vop version with rk3568, so 830 * we need to use soc_id for identification here. 831 */ 832 if (vop2->data->soc_id == 3566) 833 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); 834 835 if (vop2->version == VOP_VERSION_RK3588) 836 rk3588_vop2_power_domain_enable_all(vop2); 837 838 if (vop2->version <= VOP_VERSION_RK3588) { 839 vop2->old_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); 840 vop2->old_port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); 841 } 842 843 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 844 845 /* 846 * Disable auto gating, this is a workaround to 847 * avoid display image shift when a window enabled. 848 */ 849 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, 850 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); 851 852 vop2_writel(vop2, RK3568_SYS0_INT_CLR, 853 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 854 vop2_writel(vop2, RK3568_SYS0_INT_EN, 855 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 856 vop2_writel(vop2, RK3568_SYS1_INT_CLR, 857 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 858 vop2_writel(vop2, RK3568_SYS1_INT_EN, 859 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 860 } 861 862 static void vop2_disable(struct vop2 *vop2) 863 { 864 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); 865 866 pm_runtime_put_sync(vop2->dev); 867 868 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); 869 870 clk_disable_unprepare(vop2->pclk); 871 clk_disable_unprepare(vop2->aclk); 872 clk_disable_unprepare(vop2->hclk); 873 } 874 875 static bool vop2_vp_dsp_lut_is_enabled(struct vop2_video_port *vp) 876 { 877 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 878 879 return dsp_ctrl & RK3568_VP_DSP_CTRL__DSP_LUT_EN; 880 } 881 882 static void vop2_vp_dsp_lut_disable(struct vop2_video_port *vp) 883 { 884 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 885 886 dsp_ctrl &= ~RK3568_VP_DSP_CTRL__DSP_LUT_EN; 887 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 888 } 889 890 static bool vop2_vp_dsp_lut_poll_disabled(struct vop2_video_port *vp) 891 { 892 u32 dsp_ctrl; 893 int ret = readx_poll_timeout(vop2_vp_dsp_lut_is_enabled, vp, dsp_ctrl, 894 !dsp_ctrl, 5, 30 * 1000); 895 if (ret) { 896 drm_err(vp->vop2->drm, "display LUT RAM enable timeout!\n"); 897 return false; 898 } 899 900 return true; 901 } 902 903 static void vop2_vp_dsp_lut_enable(struct vop2_video_port *vp) 904 { 905 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 906 907 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_LUT_EN; 908 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 909 } 910 911 static void vop2_vp_dsp_lut_update_enable(struct vop2_video_port *vp) 912 { 913 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 914 915 dsp_ctrl |= RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN; 916 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 917 } 918 919 static inline bool vop2_supports_seamless_gamma_lut_update(struct vop2 *vop2) 920 { 921 return vop2->version != VOP_VERSION_RK3568; 922 } 923 924 static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp) 925 { 926 const int nr_vps = vop2->data->nr_vps; 927 int gamma_en_vp_id; 928 929 for (gamma_en_vp_id = 0; gamma_en_vp_id < nr_vps; gamma_en_vp_id++) 930 if (vop2_vp_dsp_lut_is_enabled(&vop2->vps[gamma_en_vp_id])) 931 break; 932 933 return gamma_en_vp_id != nr_vps && gamma_en_vp_id != vp->id; 934 } 935 936 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, 937 struct drm_atomic_state *state) 938 { 939 struct vop2_video_port *vp = to_vop2_video_port(crtc); 940 struct vop2 *vop2 = vp->vop2; 941 struct drm_crtc_state *old_crtc_state; 942 int ret; 943 944 vop2_lock(vop2); 945 946 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 947 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 948 949 drm_crtc_vblank_off(crtc); 950 951 /* 952 * Vop standby will take effect at end of current frame, 953 * if dsp hold valid irq happen, it means standby complete. 954 * 955 * we must wait standby complete when we want to disable aclk, 956 * if not, memory bus maybe dead. 957 */ 958 reinit_completion(&vp->dsp_hold_completion); 959 960 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); 961 962 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); 963 964 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, 965 msecs_to_jiffies(50)); 966 if (!ret) 967 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); 968 969 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); 970 971 if (vp->dclk_src) 972 clk_set_parent(vp->dclk, vp->dclk_src); 973 974 clk_disable_unprepare(vp->dclk); 975 976 vop2->enable_count--; 977 978 if (!vop2->enable_count) 979 vop2_disable(vop2); 980 981 vop2_unlock(vop2); 982 983 if (crtc->state->event && !crtc->state->active) { 984 spin_lock_irq(&crtc->dev->event_lock); 985 drm_crtc_send_vblank_event(crtc, crtc->state->event); 986 spin_unlock_irq(&crtc->dev->event_lock); 987 988 crtc->state->event = NULL; 989 } 990 } 991 992 static int vop2_plane_atomic_check(struct drm_plane *plane, 993 struct drm_atomic_state *astate) 994 { 995 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); 996 struct drm_framebuffer *fb = pstate->fb; 997 struct drm_crtc *crtc = pstate->crtc; 998 struct drm_crtc_state *cstate; 999 struct vop2_video_port *vp; 1000 struct vop2 *vop2; 1001 const struct vop2_data *vop2_data; 1002 struct drm_rect *dest = &pstate->dst; 1003 struct drm_rect *src = &pstate->src; 1004 int min_scale = FRAC_16_16(1, 8); 1005 int max_scale = FRAC_16_16(8, 1); 1006 int src_x, src_w, src_h; 1007 int dest_w, dest_h; 1008 int format; 1009 int ret; 1010 1011 if (!crtc) 1012 return 0; 1013 1014 vp = to_vop2_video_port(crtc); 1015 vop2 = vp->vop2; 1016 vop2_data = vop2->data; 1017 1018 cstate = drm_atomic_get_new_crtc_state(pstate->state, crtc); 1019 if (WARN_ON(!cstate)) 1020 return -EINVAL; 1021 1022 ret = drm_atomic_helper_check_plane_state(pstate, cstate, 1023 min_scale, max_scale, 1024 true, true); 1025 if (ret) 1026 return ret; 1027 1028 if (!pstate->visible) 1029 return 0; 1030 1031 format = vop2_convert_format(fb->format->format); 1032 if (format < 0) 1033 return format; 1034 1035 /* Co-ordinates have now been clipped */ 1036 src_x = src->x1 >> 16; 1037 src_w = drm_rect_width(src) >> 16; 1038 src_h = drm_rect_height(src) >> 16; 1039 dest_w = drm_rect_width(dest); 1040 dest_h = drm_rect_height(dest); 1041 1042 if (src_w < 4 || src_h < 4 || dest_w < 4 || dest_h < 4) { 1043 drm_dbg_kms(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", 1044 src_w, src_h, dest_w, dest_h); 1045 return -EINVAL; 1046 } 1047 1048 if (src_w > vop2_data->max_input.width || 1049 src_h > vop2_data->max_input.height) { 1050 drm_dbg_kms(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", 1051 src_w, src_h, 1052 vop2_data->max_input.width, 1053 vop2_data->max_input.height); 1054 return -EINVAL; 1055 } 1056 1057 /* 1058 * Src.x1 can be odd when do clip, but yuv plane start point 1059 * need align with 2 pixel. 1060 */ 1061 if (fb->format->is_yuv && src_x % 2) { 1062 drm_dbg_kms(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); 1063 return -EINVAL; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static void vop2_plane_atomic_disable(struct drm_plane *plane, 1070 struct drm_atomic_state *state) 1071 { 1072 struct drm_plane_state *old_pstate = NULL; 1073 struct vop2_win *win = to_vop2_win(plane); 1074 struct vop2 *vop2 = win->vop2; 1075 1076 drm_dbg(vop2->drm, "%s disable\n", win->data->name); 1077 1078 if (state) 1079 old_pstate = drm_atomic_get_old_plane_state(state, plane); 1080 if (old_pstate && !old_pstate->crtc) 1081 return; 1082 1083 vop2_win_disable(win); 1084 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); 1085 } 1086 1087 /* 1088 * The color key is 10 bit, so all format should 1089 * convert to 10 bit here. 1090 */ 1091 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) 1092 { 1093 struct drm_plane_state *pstate = plane->state; 1094 struct drm_framebuffer *fb = pstate->fb; 1095 struct vop2_win *win = to_vop2_win(plane); 1096 u32 color_key_en = 0; 1097 u32 r = 0; 1098 u32 g = 0; 1099 u32 b = 0; 1100 1101 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { 1102 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); 1103 return; 1104 } 1105 1106 switch (fb->format->format) { 1107 case DRM_FORMAT_RGB565: 1108 case DRM_FORMAT_BGR565: 1109 r = (color_key & 0xf800) >> 11; 1110 g = (color_key & 0x7e0) >> 5; 1111 b = (color_key & 0x1f); 1112 r <<= 5; 1113 g <<= 4; 1114 b <<= 5; 1115 color_key_en = 1; 1116 break; 1117 case DRM_FORMAT_XRGB8888: 1118 case DRM_FORMAT_ARGB8888: 1119 case DRM_FORMAT_XBGR8888: 1120 case DRM_FORMAT_ABGR8888: 1121 case DRM_FORMAT_RGB888: 1122 case DRM_FORMAT_BGR888: 1123 r = (color_key & 0xff0000) >> 16; 1124 g = (color_key & 0xff00) >> 8; 1125 b = (color_key & 0xff); 1126 r <<= 2; 1127 g <<= 2; 1128 b <<= 2; 1129 color_key_en = 1; 1130 break; 1131 } 1132 1133 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); 1134 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); 1135 } 1136 1137 static void vop2_plane_atomic_update(struct drm_plane *plane, 1138 struct drm_atomic_state *state) 1139 { 1140 struct drm_plane_state *pstate = plane->state; 1141 struct drm_crtc *crtc = pstate->crtc; 1142 struct vop2_win *win = to_vop2_win(plane); 1143 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1144 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1145 struct vop2 *vop2 = win->vop2; 1146 struct drm_framebuffer *fb = pstate->fb; 1147 u32 bpp = vop2_get_bpp(fb->format); 1148 u32 src_w, src_h, dsp_w, dsp_h; 1149 u32 act_info, dsp_info; 1150 u32 format; 1151 u32 afbc_format; 1152 u32 rb_swap; 1153 u32 uv_swap; 1154 struct drm_rect *src = &pstate->src; 1155 struct drm_rect *dest = &pstate->dst; 1156 u32 afbc_tile_num; 1157 u32 transform_offset; 1158 bool dither_up; 1159 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1160 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1161 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1162 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1163 struct rockchip_gem_object *rk_obj; 1164 unsigned long offset; 1165 bool half_block_en; 1166 bool afbc_en; 1167 dma_addr_t yrgb_mst; 1168 dma_addr_t uv_mst; 1169 1170 /* 1171 * can't update plane when vop2 is disabled. 1172 */ 1173 if (WARN_ON(!crtc)) 1174 return; 1175 1176 if (!pstate->visible) { 1177 vop2_plane_atomic_disable(plane, state); 1178 return; 1179 } 1180 1181 afbc_en = rockchip_afbc(plane, fb->modifier); 1182 1183 offset = (src->x1 >> 16) * fb->format->cpp[0]; 1184 1185 /* 1186 * AFBC HDR_PTR must set to the zero offset of the framebuffer. 1187 */ 1188 if (afbc_en) 1189 offset = 0; 1190 else if (pstate->rotation & DRM_MODE_REFLECT_Y) 1191 offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; 1192 else 1193 offset += (src->y1 >> 16) * fb->pitches[0]; 1194 1195 rk_obj = to_rockchip_obj(fb->obj[0]); 1196 1197 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 1198 if (fb->format->is_yuv) { 1199 int hsub = fb->format->hsub; 1200 int vsub = fb->format->vsub; 1201 1202 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; 1203 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 1204 1205 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) 1206 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; 1207 1208 rk_obj = to_rockchip_obj(fb->obj[0]); 1209 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; 1210 } 1211 1212 src_w = drm_rect_width(src) >> 16; 1213 src_h = drm_rect_height(src) >> 16; 1214 dsp_w = drm_rect_width(dest); 1215 1216 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { 1217 drm_dbg_kms(vop2->drm, 1218 "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", 1219 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); 1220 dsp_w = adjusted_mode->hdisplay - dest->x1; 1221 if (dsp_w < 4) 1222 dsp_w = 4; 1223 src_w = dsp_w * src_w / drm_rect_width(dest); 1224 } 1225 1226 dsp_h = drm_rect_height(dest); 1227 1228 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { 1229 drm_dbg_kms(vop2->drm, 1230 "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", 1231 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); 1232 dsp_h = adjusted_mode->vdisplay - dest->y1; 1233 if (dsp_h < 4) 1234 dsp_h = 4; 1235 src_h = dsp_h * src_h / drm_rect_height(dest); 1236 } 1237 1238 /* 1239 * This is workaround solution for IC design: 1240 * esmart can't support scale down when src_w % 16 == 1. 1241 */ 1242 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 1243 if (src_w > dsp_w && (src_w & 0xf) == 1) { 1244 drm_dbg_kms(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", 1245 vp->id, win->data->name, src_w); 1246 src_w -= 1; 1247 } 1248 } 1249 1250 if (afbc_en && src_w % 4) { 1251 drm_dbg_kms(vop2->drm, "vp%d %s src_w[%d] not 4 pixel aligned\n", 1252 vp->id, win->data->name, src_w); 1253 src_w = ALIGN_DOWN(src_w, 4); 1254 } 1255 1256 act_info = (src_h - 1) << 16 | ((src_w - 1) & 0xffff); 1257 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); 1258 1259 format = vop2_convert_format(fb->format->format); 1260 half_block_en = vop2_half_block_enable(pstate); 1261 1262 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", 1263 vp->id, win->data->name, src_w, src_h, dsp_w, dsp_h, 1264 dest->x1, dest->y1, 1265 &fb->format->format, 1266 afbc_en ? "AFBC" : "", &yrgb_mst); 1267 1268 if (vop2->version > VOP_VERSION_RK3568) { 1269 vop2_win_write(win, VOP2_WIN_AXI_BUS_ID, win->data->axi_bus_id); 1270 vop2_win_write(win, VOP2_WIN_AXI_YRGB_R_ID, win->data->axi_yrgb_r_id); 1271 vop2_win_write(win, VOP2_WIN_AXI_UV_R_ID, win->data->axi_uv_r_id); 1272 } 1273 1274 if (vop2->version >= VOP_VERSION_RK3576) 1275 vop2_win_write(win, VOP2_WIN_VP_SEL, vp->id); 1276 1277 if (vop2_cluster_window(win)) 1278 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en); 1279 1280 if (afbc_en) { 1281 u32 stride, block_w; 1282 1283 /* the afbc superblock is 16 x 16 or 32 x 8 */ 1284 block_w = fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 ? 32 : 16; 1285 1286 afbc_format = vop2_convert_afbc_format(fb->format->format); 1287 1288 /* Enable color transform for YTR */ 1289 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 1290 afbc_format |= (1 << 4); 1291 1292 afbc_tile_num = ALIGN(src_w, block_w) / block_w; 1293 1294 /* 1295 * AFBC pic_vir_width is count by pixel, this is different 1296 * with WIN_VIR_STRIDE. 1297 */ 1298 stride = (fb->pitches[0] << 3) / bpp; 1299 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) 1300 drm_dbg_kms(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", 1301 vp->id, win->data->name, stride); 1302 1303 /* It's for head stride, each head size is 16 byte */ 1304 stride = ALIGN(stride, block_w) / block_w * 16; 1305 1306 uv_swap = vop2_afbc_uv_swap(fb->format->format); 1307 /* 1308 * This is a workaround for crazy IC design, Cluster 1309 * and Esmart/Smart use different format configuration map: 1310 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. 1311 * 1312 * This is one thing we can make the convert simple: 1313 * AFBCD decode all the YUV data to YUV444. So we just 1314 * set all the yuv 10 bit to YUV444_10. 1315 */ 1316 if (fb->format->is_yuv && bpp == 10) 1317 format = VOP2_CLUSTER_YUV444_10; 1318 1319 if (vop2_cluster_window(win)) 1320 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); 1321 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); 1322 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); 1323 /* 1324 * On rk3566/8, this bit is auto gating enable, 1325 * but this function is not work well so we need 1326 * to disable it for these two platform. 1327 * On rk3588, and the following new soc(rk3528/rk3576), 1328 * this bit is gating disable, we should write 1 to 1329 * disable gating when enable afbc. 1330 */ 1331 if (vop2->version == VOP_VERSION_RK3568) 1332 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); 1333 else 1334 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1); 1335 1336 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) 1337 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 1); 1338 else 1339 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); 1340 1341 if (vop2->version >= VOP_VERSION_RK3576) { 1342 vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET_EN, 1); 1343 vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET, yrgb_mst); 1344 } 1345 1346 transform_offset = vop2_afbc_transform_offset(pstate, half_block_en); 1347 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); 1348 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); 1349 vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, transform_offset); 1350 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); 1351 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); 1352 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); 1353 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); 1354 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); 1355 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); 1356 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); 1357 } else { 1358 if (vop2_cluster_window(win)) { 1359 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0); 1360 vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, 0); 1361 } 1362 1363 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); 1364 } 1365 1366 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); 1367 1368 if (rotate_90 || rotate_270) { 1369 act_info = swahw32(act_info); 1370 src_w = drm_rect_height(src) >> 16; 1371 src_h = drm_rect_width(src) >> 16; 1372 } 1373 1374 vop2_win_write(win, VOP2_WIN_FORMAT, format); 1375 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); 1376 1377 rb_swap = vop2_win_rb_swap(fb->format->format); 1378 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); 1379 uv_swap = vop2_win_uv_swap(fb->format->format); 1380 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); 1381 1382 if (fb->format->is_yuv) { 1383 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); 1384 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); 1385 } 1386 1387 vop2_setup_scale(vop2, win, src_w, src_h, dsp_w, dsp_h, fb->format->format); 1388 if (!vop2_cluster_window(win)) 1389 vop2_plane_setup_color_key(plane, 0); 1390 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); 1391 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); 1392 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); 1393 1394 vop2_setup_csc_mode(vp, win, pstate); 1395 1396 dither_up = vop2_win_dither_up(fb->format->format); 1397 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); 1398 1399 vop2_win_write(win, VOP2_WIN_ENABLE, 1); 1400 1401 if (vop2_cluster_window(win)) { 1402 int lb_mode = vop2_get_cluster_lb_mode(win, pstate); 1403 1404 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); 1405 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); 1406 } 1407 } 1408 1409 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { 1410 .atomic_check = vop2_plane_atomic_check, 1411 .atomic_update = vop2_plane_atomic_update, 1412 .atomic_disable = vop2_plane_atomic_disable, 1413 }; 1414 1415 static const struct drm_plane_funcs vop2_plane_funcs = { 1416 .update_plane = drm_atomic_helper_update_plane, 1417 .disable_plane = drm_atomic_helper_disable_plane, 1418 .destroy = drm_plane_cleanup, 1419 .reset = drm_atomic_helper_plane_reset, 1420 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1421 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1422 .format_mod_supported = rockchip_vop2_mod_supported, 1423 }; 1424 1425 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) 1426 { 1427 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1428 1429 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); 1430 1431 return 0; 1432 } 1433 1434 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) 1435 { 1436 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1437 1438 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); 1439 } 1440 1441 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, 1442 const struct drm_display_mode *mode, 1443 struct drm_display_mode *adj_mode) 1444 { 1445 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | 1446 CRTC_STEREO_DOUBLE); 1447 1448 return true; 1449 } 1450 1451 static void vop2_crtc_write_gamma_lut(struct vop2 *vop2, struct drm_crtc *crtc) 1452 { 1453 const struct vop2_video_port *vp = to_vop2_video_port(crtc); 1454 const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id]; 1455 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1456 unsigned int i, bpc = ilog2(vp_data->gamma_lut_len); 1457 u32 word; 1458 1459 for (i = 0; i < crtc->gamma_size; i++) { 1460 word = (drm_color_lut_extract(lut[i].blue, bpc) << (2 * bpc)) | 1461 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1462 drm_color_lut_extract(lut[i].red, bpc); 1463 1464 writel(word, vop2->lut_regs + i * 4); 1465 } 1466 } 1467 1468 static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2, 1469 struct vop2_video_port *vp, 1470 struct drm_crtc *crtc) 1471 { 1472 vop2_writel(vop2, RK3568_LUT_PORT_SEL, 1473 FIELD_PREP(RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, vp->id)); 1474 vop2_vp_dsp_lut_enable(vp); 1475 vop2_crtc_write_gamma_lut(vop2, crtc); 1476 vop2_vp_dsp_lut_update_enable(vp); 1477 } 1478 1479 static void vop2_crtc_atomic_set_gamma_rk356x(struct vop2 *vop2, 1480 struct vop2_video_port *vp, 1481 struct drm_crtc *crtc) 1482 { 1483 vop2_vp_dsp_lut_disable(vp); 1484 vop2_cfg_done(vp); 1485 if (!vop2_vp_dsp_lut_poll_disabled(vp)) 1486 return; 1487 1488 vop2_writel(vop2, RK3568_LUT_PORT_SEL, vp->id); 1489 vop2_crtc_write_gamma_lut(vop2, crtc); 1490 vop2_vp_dsp_lut_enable(vp); 1491 } 1492 1493 static void vop2_crtc_atomic_try_set_gamma(struct vop2 *vop2, 1494 struct vop2_video_port *vp, 1495 struct drm_crtc *crtc, 1496 struct drm_crtc_state *crtc_state) 1497 { 1498 if (!vop2->lut_regs) 1499 return; 1500 1501 if (!crtc_state->gamma_lut) { 1502 vop2_vp_dsp_lut_disable(vp); 1503 return; 1504 } 1505 1506 if (vop2_supports_seamless_gamma_lut_update(vop2)) 1507 vop2_crtc_atomic_set_gamma_seamless(vop2, vp, crtc); 1508 else 1509 vop2_crtc_atomic_set_gamma_rk356x(vop2, vp, crtc); 1510 } 1511 1512 static inline void vop2_crtc_atomic_try_set_gamma_locked(struct vop2 *vop2, 1513 struct vop2_video_port *vp, 1514 struct drm_crtc *crtc, 1515 struct drm_crtc_state *crtc_state) 1516 { 1517 vop2_lock(vop2); 1518 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); 1519 vop2_unlock(vop2); 1520 } 1521 1522 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) 1523 { 1524 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1525 1526 switch (vcstate->bus_format) { 1527 case MEDIA_BUS_FMT_RGB565_1X16: 1528 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1529 break; 1530 case MEDIA_BUS_FMT_RGB666_1X18: 1531 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1532 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1533 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1534 *dsp_ctrl |= RGB888_TO_RGB666; 1535 break; 1536 case MEDIA_BUS_FMT_YUV8_1X24: 1537 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1538 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1539 break; 1540 default: 1541 break; 1542 } 1543 1544 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) 1545 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1546 1547 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, 1548 DITHER_DOWN_ALLEGRO); 1549 } 1550 1551 static void vop2_post_config(struct drm_crtc *crtc) 1552 { 1553 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1554 struct vop2 *vop2 = vp->vop2; 1555 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1556 u16 vtotal = mode->crtc_vtotal; 1557 u16 hdisplay = mode->crtc_hdisplay; 1558 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1559 u16 vdisplay = mode->crtc_vdisplay; 1560 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1561 u32 left_margin = 100, right_margin = 100; 1562 u32 top_margin = 100, bottom_margin = 100; 1563 u16 hsize = hdisplay * (left_margin + right_margin) / 200; 1564 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; 1565 u16 hact_end, vact_end; 1566 u32 val; 1567 1568 vop2->ops->setup_bg_dly(vp); 1569 1570 vsize = rounddown(vsize, 2); 1571 hsize = rounddown(hsize, 2); 1572 hact_st += hdisplay * (100 - left_margin) / 200; 1573 hact_end = hact_st + hsize; 1574 val = hact_st << 16; 1575 val |= hact_end; 1576 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); 1577 vact_st += vdisplay * (100 - top_margin) / 200; 1578 vact_end = vact_st + vsize; 1579 val = vact_st << 16; 1580 val |= vact_end; 1581 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); 1582 val = scl_cal_scale2(vdisplay, vsize) << 16; 1583 val |= scl_cal_scale2(hdisplay, hsize); 1584 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); 1585 1586 val = 0; 1587 if (hdisplay != hsize) 1588 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; 1589 if (vdisplay != vsize) 1590 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; 1591 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); 1592 1593 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1594 u16 vact_st_f1 = vtotal + vact_st + 1; 1595 u16 vact_end_f1 = vact_st_f1 + vsize; 1596 1597 val = vact_st_f1 << 16 | vact_end_f1; 1598 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); 1599 } 1600 1601 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); 1602 } 1603 1604 static int us_to_vertical_line(struct drm_display_mode *mode, int us) 1605 { 1606 return us * mode->clock / mode->htotal / 1000; 1607 } 1608 1609 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 1610 struct drm_atomic_state *state) 1611 { 1612 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1613 struct vop2 *vop2 = vp->vop2; 1614 const struct vop2_data *vop2_data = vop2->data; 1615 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 1616 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1617 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1618 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1619 unsigned long clock = mode->crtc_clock * 1000; 1620 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1621 u16 hdisplay = mode->crtc_hdisplay; 1622 u16 htotal = mode->crtc_htotal; 1623 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1624 u16 hact_end = hact_st + hdisplay; 1625 u16 vdisplay = mode->crtc_vdisplay; 1626 u16 vtotal = mode->crtc_vtotal; 1627 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1628 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1629 u16 vact_end = vact_st + vdisplay; 1630 u8 out_mode; 1631 u32 dsp_ctrl = 0; 1632 int act_end; 1633 u32 val, polflags; 1634 int ret; 1635 struct drm_encoder *encoder; 1636 1637 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", 1638 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1639 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); 1640 1641 vop2_lock(vop2); 1642 1643 ret = clk_prepare_enable(vp->dclk); 1644 if (ret < 0) { 1645 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", 1646 vp->id, ret); 1647 vop2_unlock(vop2); 1648 return; 1649 } 1650 1651 if (!vop2->enable_count) 1652 vop2_enable(vop2); 1653 1654 vop2->enable_count++; 1655 1656 vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format); 1657 1658 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); 1659 1660 polflags = 0; 1661 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 1662 polflags |= POLFLAG_DCLK_INV; 1663 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1664 polflags |= BIT(HSYNC_POSITIVE); 1665 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1666 polflags |= BIT(VSYNC_POSITIVE); 1667 1668 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1669 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1670 1671 /* 1672 * for drive a high resolution(4KP120, 8K), vop on rk3588/rk3576 need 1673 * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the 1674 * system cru may be the 1/2 or 1/4 of mode->clock. 1675 */ 1676 clock = vop2->ops->setup_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); 1677 } 1678 1679 if (!clock) { 1680 vop2_unlock(vop2); 1681 return; 1682 } 1683 1684 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1685 !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT)) 1686 out_mode = ROCKCHIP_OUT_MODE_P888; 1687 else 1688 out_mode = vcstate->output_mode; 1689 1690 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); 1691 1692 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) 1693 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; 1694 if (vop2_output_rg_swap(vop2, vcstate->bus_format)) 1695 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP; 1696 1697 if (vcstate->yuv_overlay) 1698 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; 1699 1700 vop2_dither_setup(crtc, &dsp_ctrl); 1701 1702 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); 1703 val = hact_st << 16; 1704 val |= hact_end; 1705 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); 1706 1707 val = vact_st << 16; 1708 val |= vact_end; 1709 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); 1710 1711 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1712 u16 vact_st_f1 = vtotal + vact_st + 1; 1713 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1714 1715 val = vact_st_f1 << 16 | vact_end_f1; 1716 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); 1717 1718 val = vtotal << 16 | (vtotal + vsync_len); 1719 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); 1720 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; 1721 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; 1722 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; 1723 vtotal += vtotal + 1; 1724 act_end = vact_end_f1; 1725 } else { 1726 act_end = vact_end; 1727 } 1728 1729 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), 1730 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); 1731 1732 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); 1733 1734 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1735 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; 1736 clock *= 2; 1737 } 1738 1739 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); 1740 1741 /* 1742 * Switch to HDMI PHY PLL as DCLK source for display modes up 1743 * to 4K@60Hz, if available, otherwise keep using the system CRU. 1744 */ 1745 if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { 1746 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1747 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1748 1749 if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { 1750 if (!vop2->pll_hdmiphy0) 1751 break; 1752 1753 if (!vp->dclk_src) 1754 vp->dclk_src = clk_get_parent(vp->dclk); 1755 1756 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); 1757 if (ret < 0) 1758 drm_warn(vop2->drm, 1759 "Could not switch to HDMI0 PHY PLL: %d\n", ret); 1760 break; 1761 } 1762 1763 if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { 1764 if (!vop2->pll_hdmiphy1) 1765 break; 1766 1767 if (!vp->dclk_src) 1768 vp->dclk_src = clk_get_parent(vp->dclk); 1769 1770 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); 1771 if (ret < 0) 1772 drm_warn(vop2->drm, 1773 "Could not switch to HDMI1 PHY PLL: %d\n", ret); 1774 break; 1775 } 1776 } 1777 } 1778 1779 clk_set_rate(vp->dclk, clock); 1780 1781 vop2_post_config(crtc); 1782 1783 vop2_cfg_done(vp); 1784 1785 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 1786 1787 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); 1788 1789 drm_crtc_vblank_on(crtc); 1790 1791 vop2_unlock(vop2); 1792 } 1793 1794 static int vop2_crtc_atomic_check_gamma(struct vop2_video_port *vp, 1795 struct drm_crtc *crtc, 1796 struct drm_atomic_state *state, 1797 struct drm_crtc_state *crtc_state) 1798 { 1799 struct vop2 *vop2 = vp->vop2; 1800 unsigned int len; 1801 1802 if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed || 1803 !crtc_state->gamma_lut) 1804 return 0; 1805 1806 len = drm_color_lut_size(crtc_state->gamma_lut); 1807 if (len != crtc->gamma_size) { 1808 drm_dbg(vop2->drm, "Invalid LUT size; got %d, expected %d\n", 1809 len, crtc->gamma_size); 1810 return -EINVAL; 1811 } 1812 1813 if (!vop2_supports_seamless_gamma_lut_update(vop2) && vop2_gamma_lut_in_use(vop2, vp)) { 1814 drm_info(vop2->drm, "Gamma LUT can be enabled for only one CRTC at a time\n"); 1815 return -EINVAL; 1816 } 1817 1818 return 0; 1819 } 1820 1821 static int vop2_crtc_atomic_check(struct drm_crtc *crtc, 1822 struct drm_atomic_state *state) 1823 { 1824 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1825 struct drm_plane *plane; 1826 int nplanes = 0; 1827 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1828 int ret; 1829 1830 ret = vop2_crtc_atomic_check_gamma(vp, crtc, state, crtc_state); 1831 if (ret) 1832 return ret; 1833 1834 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) 1835 nplanes++; 1836 1837 if (nplanes > vp->nlayers) 1838 return -EINVAL; 1839 1840 return 0; 1841 } 1842 1843 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, 1844 struct drm_atomic_state *state) 1845 { 1846 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1847 struct vop2 *vop2 = vp->vop2; 1848 1849 vop2->ops->setup_overlay(vp); 1850 } 1851 1852 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, 1853 struct drm_atomic_state *state) 1854 { 1855 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1856 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1857 struct vop2 *vop2 = vp->vop2; 1858 1859 /* In case of modeset, gamma lut update already happened in atomic enable */ 1860 if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_changed) 1861 vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); 1862 1863 vop2_post_config(crtc); 1864 1865 vop2_cfg_done(vp); 1866 1867 spin_lock_irq(&crtc->dev->event_lock); 1868 1869 if (crtc->state->event) { 1870 WARN_ON(drm_crtc_vblank_get(crtc)); 1871 vp->event = crtc->state->event; 1872 crtc->state->event = NULL; 1873 } 1874 1875 spin_unlock_irq(&crtc->dev->event_lock); 1876 } 1877 1878 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { 1879 .mode_fixup = vop2_crtc_mode_fixup, 1880 .atomic_check = vop2_crtc_atomic_check, 1881 .atomic_begin = vop2_crtc_atomic_begin, 1882 .atomic_flush = vop2_crtc_atomic_flush, 1883 .atomic_enable = vop2_crtc_atomic_enable, 1884 .atomic_disable = vop2_crtc_atomic_disable, 1885 }; 1886 1887 static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *s) 1888 { 1889 struct drm_connector_list_iter conn_iter; 1890 struct drm_connector *connector; 1891 1892 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 1893 drm_for_each_connector_iter(connector, &conn_iter) { 1894 if (crtc->state->connector_mask & drm_connector_mask(connector)) 1895 seq_printf(s, " Connector: %s\n", connector->name); 1896 } 1897 drm_connector_list_iter_end(&conn_iter); 1898 } 1899 1900 static int vop2_plane_state_dump(struct seq_file *s, struct drm_plane *plane) 1901 { 1902 struct vop2_win *win = to_vop2_win(plane); 1903 struct drm_plane_state *pstate = plane->state; 1904 struct drm_rect *src, *dst; 1905 struct drm_framebuffer *fb; 1906 struct drm_gem_object *obj; 1907 struct rockchip_gem_object *rk_obj; 1908 bool xmirror; 1909 bool ymirror; 1910 bool rotate_270; 1911 bool rotate_90; 1912 dma_addr_t fb_addr; 1913 int i; 1914 1915 seq_printf(s, " %s: %s\n", win->data->name, !pstate ? 1916 "DISABLED" : pstate->crtc ? "ACTIVE" : "DISABLED"); 1917 1918 if (!pstate || !pstate->fb) 1919 return 0; 1920 1921 fb = pstate->fb; 1922 src = &pstate->src; 1923 dst = &pstate->dst; 1924 xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1925 ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1926 rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1927 rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1928 1929 seq_printf(s, "\twin_id: %d\n", win->win_id); 1930 1931 seq_printf(s, "\tformat: %p4cc%s glb_alpha[0x%x]\n", 1932 &fb->format->format, 1933 drm_is_afbc(fb->modifier) ? "[AFBC]" : "", 1934 pstate->alpha >> 8); 1935 seq_printf(s, "\trotate: xmirror: %d ymirror: %d rotate_90: %d rotate_270: %d\n", 1936 xmirror, ymirror, rotate_90, rotate_270); 1937 seq_printf(s, "\tzpos: %d\n", pstate->normalized_zpos); 1938 seq_printf(s, "\tsrc: pos[%d, %d] rect[%d x %d]\n", src->x1 >> 16, 1939 src->y1 >> 16, drm_rect_width(src) >> 16, 1940 drm_rect_height(src) >> 16); 1941 seq_printf(s, "\tdst: pos[%d, %d] rect[%d x %d]\n", dst->x1, dst->y1, 1942 drm_rect_width(dst), drm_rect_height(dst)); 1943 1944 for (i = 0; i < fb->format->num_planes; i++) { 1945 obj = fb->obj[i]; 1946 rk_obj = to_rockchip_obj(obj); 1947 fb_addr = rk_obj->dma_addr + fb->offsets[i]; 1948 1949 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n", 1950 i, &fb_addr, fb->pitches[i], fb->offsets[i]); 1951 } 1952 1953 return 0; 1954 } 1955 1956 static int vop2_crtc_state_dump(struct drm_crtc *crtc, struct seq_file *s) 1957 { 1958 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1959 struct drm_crtc_state *cstate = crtc->state; 1960 struct rockchip_crtc_state *vcstate; 1961 struct drm_display_mode *mode; 1962 struct drm_plane *plane; 1963 bool interlaced; 1964 1965 seq_printf(s, "Video Port%d: %s\n", vp->id, !cstate ? 1966 "DISABLED" : cstate->active ? "ACTIVE" : "DISABLED"); 1967 1968 if (!cstate || !cstate->active) 1969 return 0; 1970 1971 mode = &crtc->state->adjusted_mode; 1972 vcstate = to_rockchip_crtc_state(cstate); 1973 interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1974 1975 vop2_dump_connector_on_crtc(crtc, s); 1976 seq_printf(s, "\tbus_format[%x]: %s\n", vcstate->bus_format, 1977 drm_get_bus_format_name(vcstate->bus_format)); 1978 seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode); 1979 seq_printf(s, " color_space[%d]\n", vcstate->color_space); 1980 seq_printf(s, " Display mode: %dx%d%s%d\n", 1981 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p", 1982 drm_mode_vrefresh(mode)); 1983 seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n", 1984 mode->clock, mode->crtc_clock, mode->type, mode->flags); 1985 seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start, 1986 mode->hsync_end, mode->htotal); 1987 seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start, 1988 mode->vsync_end, mode->vtotal); 1989 1990 drm_atomic_crtc_for_each_plane(plane, crtc) { 1991 vop2_plane_state_dump(s, plane); 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int vop2_summary_show(struct seq_file *s, void *data) 1998 { 1999 struct drm_info_node *node = s->private; 2000 struct drm_minor *minor = node->minor; 2001 struct drm_device *drm_dev = minor->dev; 2002 struct drm_crtc *crtc; 2003 2004 drm_modeset_lock_all(drm_dev); 2005 drm_for_each_crtc(crtc, drm_dev) { 2006 vop2_crtc_state_dump(crtc, s); 2007 } 2008 drm_modeset_unlock_all(drm_dev); 2009 2010 return 0; 2011 } 2012 2013 static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s, 2014 const struct vop2_regs_dump *dump, bool active_only) 2015 { 2016 resource_size_t start; 2017 u32 val; 2018 int i; 2019 2020 if (dump->en_mask && active_only) { 2021 val = vop2_readl(vop2, dump->base + dump->en_reg); 2022 if ((val & dump->en_mask) != dump->en_val) 2023 return; 2024 } 2025 2026 seq_printf(s, "\n%s:\n", dump->name); 2027 2028 start = vop2->res->start + dump->base; 2029 for (i = 0; i < dump->size >> 2; i += 4) { 2030 seq_printf(s, "%08x: %08x %08x %08x %08x\n", (u32)start + i * 4, 2031 vop2_readl(vop2, dump->base + (4 * i)), 2032 vop2_readl(vop2, dump->base + (4 * (i + 1))), 2033 vop2_readl(vop2, dump->base + (4 * (i + 2))), 2034 vop2_readl(vop2, dump->base + (4 * (i + 3)))); 2035 } 2036 } 2037 2038 static void __vop2_regs_dump(struct seq_file *s, bool active_only) 2039 { 2040 struct drm_info_node *node = s->private; 2041 struct vop2 *vop2 = node->info_ent->data; 2042 struct drm_minor *minor = node->minor; 2043 struct drm_device *drm_dev = minor->dev; 2044 const struct vop2_regs_dump *dump; 2045 unsigned int i; 2046 2047 drm_modeset_lock_all(drm_dev); 2048 2049 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); 2050 2051 if (vop2->enable_count) { 2052 for (i = 0; i < vop2->data->regs_dump_size; i++) { 2053 dump = &vop2->data->regs_dump[i]; 2054 vop2_regs_print(vop2, s, dump, active_only); 2055 } 2056 } else { 2057 seq_puts(s, "VOP disabled\n"); 2058 } 2059 drm_modeset_unlock_all(drm_dev); 2060 } 2061 2062 static int vop2_regs_show(struct seq_file *s, void *arg) 2063 { 2064 __vop2_regs_dump(s, false); 2065 2066 return 0; 2067 } 2068 2069 static int vop2_active_regs_show(struct seq_file *s, void *data) 2070 { 2071 __vop2_regs_dump(s, true); 2072 2073 return 0; 2074 } 2075 2076 static struct drm_info_list vop2_debugfs_list[] = { 2077 { "summary", vop2_summary_show, 0, NULL }, 2078 { "active_regs", vop2_active_regs_show, 0, NULL }, 2079 { "regs", vop2_regs_show, 0, NULL }, 2080 }; 2081 2082 static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor) 2083 { 2084 struct dentry *root; 2085 unsigned int i; 2086 2087 root = debugfs_create_dir("vop2", minor->debugfs_root); 2088 if (!IS_ERR(root)) { 2089 for (i = 0; i < ARRAY_SIZE(vop2_debugfs_list); i++) 2090 vop2_debugfs_list[i].data = vop2; 2091 2092 drm_debugfs_create_files(vop2_debugfs_list, 2093 ARRAY_SIZE(vop2_debugfs_list), 2094 root, minor); 2095 } 2096 } 2097 2098 static int vop2_crtc_late_register(struct drm_crtc *crtc) 2099 { 2100 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2101 struct vop2 *vop2 = vp->vop2; 2102 2103 if (drm_crtc_index(crtc) == 0) 2104 vop2_debugfs_init(vop2, crtc->dev->primary); 2105 2106 return 0; 2107 } 2108 2109 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) 2110 { 2111 struct rockchip_crtc_state *vcstate; 2112 2113 if (WARN_ON(!crtc->state)) 2114 return NULL; 2115 2116 vcstate = kmemdup(to_rockchip_crtc_state(crtc->state), 2117 sizeof(*vcstate), GFP_KERNEL); 2118 if (!vcstate) 2119 return NULL; 2120 2121 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); 2122 2123 return &vcstate->base; 2124 } 2125 2126 static void vop2_crtc_destroy_state(struct drm_crtc *crtc, 2127 struct drm_crtc_state *state) 2128 { 2129 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); 2130 2131 __drm_atomic_helper_crtc_destroy_state(&vcstate->base); 2132 kfree(vcstate); 2133 } 2134 2135 static void vop2_crtc_reset(struct drm_crtc *crtc) 2136 { 2137 struct rockchip_crtc_state *vcstate = 2138 kzalloc(sizeof(*vcstate), GFP_KERNEL); 2139 2140 if (crtc->state) 2141 vop2_crtc_destroy_state(crtc, crtc->state); 2142 2143 if (vcstate) 2144 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base); 2145 else 2146 __drm_atomic_helper_crtc_reset(crtc, NULL); 2147 } 2148 2149 static const struct drm_crtc_funcs vop2_crtc_funcs = { 2150 .set_config = drm_atomic_helper_set_config, 2151 .page_flip = drm_atomic_helper_page_flip, 2152 .destroy = drm_crtc_cleanup, 2153 .reset = vop2_crtc_reset, 2154 .atomic_duplicate_state = vop2_crtc_duplicate_state, 2155 .atomic_destroy_state = vop2_crtc_destroy_state, 2156 .enable_vblank = vop2_crtc_enable_vblank, 2157 .disable_vblank = vop2_crtc_disable_vblank, 2158 .late_register = vop2_crtc_late_register, 2159 }; 2160 2161 static irqreturn_t rk3576_vp_isr(int irq, void *data) 2162 { 2163 struct vop2_video_port *vp = data; 2164 struct vop2 *vop2 = vp->vop2; 2165 struct drm_crtc *crtc = &vp->crtc; 2166 uint32_t irqs; 2167 int ret = IRQ_NONE; 2168 2169 if (!pm_runtime_get_if_in_use(vop2->dev)) 2170 return IRQ_NONE; 2171 2172 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2173 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2174 2175 if (irqs & VP_INT_DSP_HOLD_VALID) { 2176 complete(&vp->dsp_hold_completion); 2177 ret = IRQ_HANDLED; 2178 } 2179 2180 if (irqs & VP_INT_FS_FIELD) { 2181 drm_crtc_handle_vblank(crtc); 2182 spin_lock(&crtc->dev->event_lock); 2183 if (vp->event) { 2184 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2185 2186 if (!(val & BIT(vp->id))) { 2187 drm_crtc_send_vblank_event(crtc, vp->event); 2188 vp->event = NULL; 2189 drm_crtc_vblank_put(crtc); 2190 } 2191 } 2192 spin_unlock(&crtc->dev->event_lock); 2193 2194 ret = IRQ_HANDLED; 2195 } 2196 2197 if (irqs & VP_INT_POST_BUF_EMPTY) { 2198 drm_err_ratelimited(vop2->drm, "POST_BUF_EMPTY irq err at vp%d\n", vp->id); 2199 ret = IRQ_HANDLED; 2200 } 2201 2202 pm_runtime_put(vop2->dev); 2203 2204 return ret; 2205 } 2206 2207 static irqreturn_t vop2_isr(int irq, void *data) 2208 { 2209 struct vop2 *vop2 = data; 2210 const struct vop2_data *vop2_data = vop2->data; 2211 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; 2212 int ret = IRQ_NONE; 2213 int i; 2214 2215 /* 2216 * The irq is shared with the iommu. If the runtime-pm state of the 2217 * vop2-device is disabled the irq has to be targeted at the iommu. 2218 */ 2219 if (!pm_runtime_get_if_in_use(vop2->dev)) 2220 return IRQ_NONE; 2221 2222 if (vop2->version < VOP_VERSION_RK3576) { 2223 for (i = 0; i < vop2_data->nr_vps; i++) { 2224 struct vop2_video_port *vp = &vop2->vps[i]; 2225 struct drm_crtc *crtc = &vp->crtc; 2226 u32 irqs; 2227 2228 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2229 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2230 2231 if (irqs & VP_INT_DSP_HOLD_VALID) { 2232 complete(&vp->dsp_hold_completion); 2233 ret = IRQ_HANDLED; 2234 } 2235 2236 if (irqs & VP_INT_FS_FIELD) { 2237 drm_crtc_handle_vblank(crtc); 2238 spin_lock(&crtc->dev->event_lock); 2239 if (vp->event) { 2240 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2241 2242 if (!(val & BIT(vp->id))) { 2243 drm_crtc_send_vblank_event(crtc, vp->event); 2244 vp->event = NULL; 2245 drm_crtc_vblank_put(crtc); 2246 } 2247 } 2248 spin_unlock(&crtc->dev->event_lock); 2249 2250 ret = IRQ_HANDLED; 2251 } 2252 2253 if (irqs & VP_INT_POST_BUF_EMPTY) { 2254 drm_err_ratelimited(vop2->drm, 2255 "POST_BUF_EMPTY irq err at vp%d\n", 2256 vp->id); 2257 ret = IRQ_HANDLED; 2258 } 2259 } 2260 } 2261 2262 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); 2263 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); 2264 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); 2265 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); 2266 2267 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { 2268 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { 2269 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); 2270 ret = IRQ_HANDLED; 2271 } 2272 } 2273 2274 pm_runtime_put(vop2->dev); 2275 2276 return ret; 2277 } 2278 2279 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, 2280 unsigned long possible_crtcs) 2281 { 2282 const struct vop2_win_data *win_data = win->data; 2283 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2284 BIT(DRM_MODE_BLEND_PREMULTI) | 2285 BIT(DRM_MODE_BLEND_COVERAGE); 2286 int ret; 2287 2288 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, 2289 &vop2_plane_funcs, win_data->formats, 2290 win_data->nformats, 2291 win_data->format_modifiers, 2292 win->type, win_data->name); 2293 if (ret) { 2294 drm_err(vop2->drm, "failed to initialize plane %d\n", ret); 2295 return ret; 2296 } 2297 2298 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); 2299 2300 if (win->data->supported_rotations) 2301 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, 2302 DRM_MODE_ROTATE_0 | 2303 win->data->supported_rotations); 2304 drm_plane_create_alpha_property(&win->base); 2305 drm_plane_create_blend_mode_property(&win->base, blend_caps); 2306 drm_plane_create_zpos_property(&win->base, win->win_id, 0, 2307 vop2->registered_num_wins - 1); 2308 2309 return 0; 2310 } 2311 2312 /* 2313 * On RK3566 these windows don't have an independent 2314 * framebuffer. They can only share/mirror the framebuffer 2315 * with smart0, esmart0 and cluster0 respectively. 2316 * And RK3566 share the same vop version with Rk3568, so we 2317 * need to use soc_id for identification here. 2318 */ 2319 static bool vop2_is_mirror_win(struct vop2_win *win) 2320 { 2321 struct vop2 *vop2 = win->vop2; 2322 2323 if (vop2->data->soc_id == 3566) { 2324 switch (win->data->phys_id) { 2325 case ROCKCHIP_VOP2_SMART1: 2326 case ROCKCHIP_VOP2_ESMART1: 2327 case ROCKCHIP_VOP2_CLUSTER1: 2328 return true; 2329 default: 2330 return false; 2331 } 2332 } else { 2333 return false; 2334 } 2335 } 2336 2337 static int vop2_create_crtcs(struct vop2 *vop2) 2338 { 2339 const struct vop2_data *vop2_data = vop2->data; 2340 struct drm_device *drm = vop2->drm; 2341 struct device *dev = vop2->dev; 2342 struct drm_plane *plane; 2343 struct device_node *port; 2344 struct vop2_video_port *vp; 2345 struct vop2_win *win; 2346 u32 possible_crtcs; 2347 int i, j, nvp, nvps = 0; 2348 int ret; 2349 2350 for (i = 0; i < vop2_data->nr_vps; i++) { 2351 const struct vop2_video_port_data *vp_data; 2352 struct device_node *np; 2353 char dclk_name[9]; 2354 2355 vp_data = &vop2_data->vp[i]; 2356 vp = &vop2->vps[i]; 2357 vp->vop2 = vop2; 2358 vp->id = vp_data->id; 2359 vp->data = vp_data; 2360 2361 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); 2362 vp->dclk = devm_clk_get(vop2->dev, dclk_name); 2363 if (IS_ERR(vp->dclk)) 2364 return dev_err_probe(drm->dev, PTR_ERR(vp->dclk), 2365 "failed to get %s\n", dclk_name); 2366 2367 np = of_graph_get_remote_node(dev->of_node, i, -1); 2368 if (!np) { 2369 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); 2370 continue; 2371 } 2372 of_node_put(np); 2373 2374 port = of_graph_get_port_by_id(dev->of_node, i); 2375 if (!port) 2376 return dev_err_probe(drm->dev, -ENOENT, 2377 "no port node found for video_port%d\n", i); 2378 vp->crtc.port = port; 2379 nvps++; 2380 } 2381 2382 nvp = 0; 2383 /* Register a primary plane for every crtc */ 2384 for (i = 0; i < vop2_data->nr_vps; i++) { 2385 vp = &vop2->vps[i]; 2386 2387 if (!vp->crtc.port) 2388 continue; 2389 2390 for (j = 0; j < vop2->registered_num_wins; j++) { 2391 win = &vop2->win[j]; 2392 2393 /* Aready registered as primary plane */ 2394 if (win->base.type == DRM_PLANE_TYPE_PRIMARY) 2395 continue; 2396 2397 /* If this win can not attached to this VP */ 2398 if (!(win->data->possible_vp_mask & BIT(vp->id))) 2399 continue; 2400 2401 if (vop2_is_mirror_win(win)) 2402 continue; 2403 2404 if (win->type == DRM_PLANE_TYPE_PRIMARY) { 2405 possible_crtcs = BIT(nvp); 2406 vp->primary_plane = win; 2407 ret = vop2_plane_init(vop2, win, possible_crtcs); 2408 if (ret) 2409 return dev_err_probe(drm->dev, ret, 2410 "failed to init primary plane %s\n", 2411 win->data->name); 2412 nvp++; 2413 break; 2414 } 2415 } 2416 2417 if (!vp->primary_plane) 2418 return dev_err_probe(drm->dev, -ENOENT, 2419 "no primary plane for vp %d\n", i); 2420 } 2421 2422 /* Register all unused window as overlay plane */ 2423 for (i = 0; i < vop2->registered_num_wins; i++) { 2424 win = &vop2->win[i]; 2425 2426 /* Aready registered as primary plane */ 2427 if (win->base.type == DRM_PLANE_TYPE_PRIMARY) 2428 continue; 2429 2430 if (vop2_is_mirror_win(win)) 2431 continue; 2432 2433 win->type = DRM_PLANE_TYPE_OVERLAY; 2434 2435 possible_crtcs = 0; 2436 nvp = 0; 2437 for (j = 0; j < vop2_data->nr_vps; j++) { 2438 vp = &vop2->vps[j]; 2439 2440 if (!vp->crtc.port) 2441 continue; 2442 2443 if (win->data->possible_vp_mask & BIT(vp->id)) 2444 possible_crtcs |= BIT(nvp); 2445 nvp++; 2446 } 2447 2448 ret = vop2_plane_init(vop2, win, possible_crtcs); 2449 if (ret) 2450 return dev_err_probe(drm->dev, ret, "failed to init overlay plane %s\n", 2451 win->data->name); 2452 } 2453 2454 for (i = 0; i < vop2_data->nr_vps; i++) { 2455 vp = &vop2->vps[i]; 2456 2457 if (!vp->crtc.port) 2458 continue; 2459 2460 plane = &vp->primary_plane->base; 2461 2462 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, 2463 &vop2_crtc_funcs, 2464 "video_port%d", vp->id); 2465 if (ret) 2466 return dev_err_probe(drm->dev, ret, 2467 "crtc init for video_port%d failed\n", i); 2468 2469 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); 2470 if (vop2->lut_regs) { 2471 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 2472 2473 drm_mode_crtc_set_gamma_size(&vp->crtc, vp_data->gamma_lut_len); 2474 drm_crtc_enable_color_mgmt(&vp->crtc, 0, false, vp_data->gamma_lut_len); 2475 } 2476 init_completion(&vp->dsp_hold_completion); 2477 } 2478 2479 /* 2480 * On the VOP2 it's very hard to change the number of layers on a VP 2481 * during runtime, so we distribute the layers equally over the used 2482 * VPs 2483 */ 2484 for (i = 0; i < vop2->data->nr_vps; i++) { 2485 struct vop2_video_port *vp = &vop2->vps[i]; 2486 2487 if (vp->crtc.port) 2488 vp->nlayers = vop2_data->win_size / nvps; 2489 } 2490 2491 return 0; 2492 } 2493 2494 static void vop2_destroy_crtcs(struct vop2 *vop2) 2495 { 2496 struct drm_device *drm = vop2->drm; 2497 struct list_head *crtc_list = &drm->mode_config.crtc_list; 2498 struct list_head *plane_list = &drm->mode_config.plane_list; 2499 struct drm_crtc *crtc, *tmpc; 2500 struct drm_plane *plane, *tmpp; 2501 2502 list_for_each_entry_safe(plane, tmpp, plane_list, head) 2503 drm_plane_cleanup(plane); 2504 2505 /* 2506 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() 2507 * references the CRTC. 2508 */ 2509 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) { 2510 of_node_put(crtc->port); 2511 drm_crtc_cleanup(crtc); 2512 } 2513 } 2514 2515 static int vop2_find_rgb_encoder(struct vop2 *vop2) 2516 { 2517 struct device_node *node = vop2->dev->of_node; 2518 struct device_node *endpoint; 2519 int i; 2520 2521 for (i = 0; i < vop2->data->nr_vps; i++) { 2522 endpoint = of_graph_get_endpoint_by_regs(node, i, 2523 ROCKCHIP_VOP2_EP_RGB0); 2524 if (!endpoint) 2525 continue; 2526 2527 of_node_put(endpoint); 2528 return i; 2529 } 2530 2531 return -ENOENT; 2532 } 2533 2534 static int vop2_regmap_init(struct vop2_win *win, const struct reg_field *regs, 2535 int nr_regs) 2536 { 2537 struct vop2 *vop2 = win->vop2; 2538 int i; 2539 2540 for (i = 0; i < nr_regs; i++) { 2541 const struct reg_field field = { 2542 .reg = (regs[i].reg != 0xffffffff) ? 2543 regs[i].reg + win->offset : regs[i].reg, 2544 .lsb = regs[i].lsb, 2545 .msb = regs[i].msb 2546 }; 2547 2548 win->reg[i] = devm_regmap_field_alloc(vop2->dev, vop2->map, field); 2549 if (IS_ERR(win->reg[i])) 2550 return PTR_ERR(win->reg[i]); 2551 } 2552 2553 return 0; 2554 }; 2555 2556 static int vop2_win_init(struct vop2 *vop2) 2557 { 2558 const struct vop2_data *vop2_data = vop2->data; 2559 struct vop2_win *win; 2560 int i, ret; 2561 2562 for (i = 0; i < vop2_data->win_size; i++) { 2563 const struct vop2_win_data *win_data = &vop2_data->win[i]; 2564 2565 win = &vop2->win[i]; 2566 win->data = win_data; 2567 win->type = win_data->type; 2568 win->offset = win_data->base; 2569 win->win_id = i; 2570 win->vop2 = vop2; 2571 if (vop2_cluster_window(win)) 2572 ret = vop2_regmap_init(win, vop2->data->cluster_reg, 2573 vop2->data->nr_cluster_regs); 2574 else 2575 ret = vop2_regmap_init(win, vop2->data->smart_reg, 2576 vop2->data->nr_smart_regs); 2577 if (ret) 2578 return ret; 2579 } 2580 2581 vop2->registered_num_wins = vop2_data->win_size; 2582 2583 return 0; 2584 } 2585 2586 /* 2587 * The window and video port registers are only updated when config 2588 * done is written. Until that they read back the old value. As we 2589 * read-modify-write these registers mark them as non-volatile. This 2590 * makes sure we read the new values from the regmap register cache. 2591 */ 2592 static const struct regmap_range vop2_nonvolatile_range[] = { 2593 regmap_reg_range(RK3568_VP0_CTRL_BASE, RK3588_VP3_CTRL_BASE + 255), 2594 regmap_reg_range(0x1000, 0x23ff), 2595 }; 2596 2597 static const struct regmap_access_table vop2_volatile_table = { 2598 .no_ranges = vop2_nonvolatile_range, 2599 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), 2600 }; 2601 2602 static const struct regmap_config vop2_regmap_config = { 2603 .reg_bits = 32, 2604 .val_bits = 32, 2605 .reg_stride = 4, 2606 .max_register = 0x3000, 2607 .name = "vop2", 2608 .volatile_table = &vop2_volatile_table, 2609 .cache_type = REGCACHE_MAPLE, 2610 }; 2611 2612 static int vop2_bind(struct device *dev, struct device *master, void *data) 2613 { 2614 struct platform_device *pdev = to_platform_device(dev); 2615 const struct vop2_data *vop2_data; 2616 struct drm_device *drm = data; 2617 struct vop2 *vop2; 2618 struct resource *res; 2619 size_t alloc_size; 2620 int ret; 2621 2622 vop2_data = of_device_get_match_data(dev); 2623 if (!vop2_data) 2624 return -ENODEV; 2625 2626 /* Allocate vop2 struct and its vop2_win array */ 2627 alloc_size = struct_size(vop2, win, vop2_data->win_size); 2628 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 2629 if (!vop2) 2630 return -ENOMEM; 2631 2632 vop2->dev = dev; 2633 vop2->data = vop2_data; 2634 vop2->ops = vop2_data->ops; 2635 vop2->version = vop2_data->version; 2636 vop2->drm = drm; 2637 2638 dev_set_drvdata(dev, vop2); 2639 2640 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop"); 2641 if (!res) 2642 return dev_err_probe(drm->dev, -EINVAL, 2643 "failed to get vop2 register byname\n"); 2644 2645 vop2->res = res; 2646 vop2->regs = devm_ioremap_resource(dev, res); 2647 if (IS_ERR(vop2->regs)) 2648 return PTR_ERR(vop2->regs); 2649 vop2->len = resource_size(res); 2650 2651 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); 2652 if (IS_ERR(vop2->map)) 2653 return PTR_ERR(vop2->map); 2654 2655 /* Set the bounds for framebuffer creation */ 2656 drm->mode_config.min_width = 4; 2657 drm->mode_config.min_height = 4; 2658 drm->mode_config.max_width = vop2_data->max_input.width; 2659 drm->mode_config.max_height = vop2_data->max_input.height; 2660 2661 ret = vop2_win_init(vop2); 2662 if (ret) 2663 return ret; 2664 2665 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut"); 2666 if (res) { 2667 vop2->lut_regs = devm_ioremap_resource(dev, res); 2668 if (IS_ERR(vop2->lut_regs)) 2669 return PTR_ERR(vop2->lut_regs); 2670 } 2671 if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_GRF) { 2672 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 2673 if (IS_ERR(vop2->sys_grf)) 2674 return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_grf), 2675 "cannot get sys_grf\n"); 2676 } 2677 2678 if (vop2_data->feature & VOP2_FEATURE_HAS_VOP_GRF) { 2679 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); 2680 if (IS_ERR(vop2->vop_grf)) 2681 return dev_err_probe(drm->dev, PTR_ERR(vop2->vop_grf), 2682 "cannot get vop_grf\n"); 2683 } 2684 2685 if (vop2_data->feature & VOP2_FEATURE_HAS_VO1_GRF) { 2686 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); 2687 if (IS_ERR(vop2->vo1_grf)) 2688 return dev_err_probe(drm->dev, PTR_ERR(vop2->vo1_grf), 2689 "cannot get vo1_grf\n"); 2690 } 2691 2692 if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_PMU) { 2693 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); 2694 if (IS_ERR(vop2->sys_pmu)) 2695 return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_pmu), 2696 "cannot get sys_pmu\n"); 2697 } 2698 2699 vop2->hclk = devm_clk_get(vop2->dev, "hclk"); 2700 if (IS_ERR(vop2->hclk)) 2701 return dev_err_probe(drm->dev, PTR_ERR(vop2->hclk), 2702 "failed to get hclk source\n"); 2703 2704 vop2->aclk = devm_clk_get(vop2->dev, "aclk"); 2705 if (IS_ERR(vop2->aclk)) 2706 return dev_err_probe(drm->dev, PTR_ERR(vop2->aclk), 2707 "failed to get aclk source\n"); 2708 2709 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); 2710 if (IS_ERR(vop2->pclk)) 2711 return dev_err_probe(drm->dev, PTR_ERR(vop2->pclk), 2712 "failed to get pclk source\n"); 2713 2714 vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0"); 2715 if (IS_ERR(vop2->pll_hdmiphy0)) 2716 return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy0), 2717 "failed to get pll_hdmiphy0\n"); 2718 2719 vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); 2720 if (IS_ERR(vop2->pll_hdmiphy1)) 2721 return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy1), 2722 "failed to get pll_hdmiphy1\n"); 2723 2724 vop2->irq = platform_get_irq(pdev, 0); 2725 if (vop2->irq < 0) 2726 return dev_err_probe(drm->dev, vop2->irq, "cannot find irq for vop2\n"); 2727 2728 mutex_init(&vop2->vop2_lock); 2729 mutex_init(&vop2->ovl_lock); 2730 2731 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); 2732 if (ret) 2733 return ret; 2734 2735 ret = vop2_create_crtcs(vop2); 2736 if (ret) 2737 return ret; 2738 2739 if (vop2->version >= VOP_VERSION_RK3576) { 2740 struct drm_crtc *crtc; 2741 2742 drm_for_each_crtc(crtc, drm) { 2743 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2744 int vp_irq; 2745 const char *irq_name = devm_kasprintf(dev, GFP_KERNEL, "vp%d", vp->id); 2746 2747 if (!irq_name) 2748 return -ENOMEM; 2749 2750 vp_irq = platform_get_irq_byname(pdev, irq_name); 2751 if (vp_irq < 0) 2752 return dev_err_probe(drm->dev, vp_irq, 2753 "cannot find irq for vop2 vp%d\n", vp->id); 2754 2755 ret = devm_request_irq(dev, vp_irq, rk3576_vp_isr, IRQF_SHARED, irq_name, 2756 vp); 2757 if (ret) 2758 dev_err_probe(drm->dev, ret, 2759 "request irq for vop2 vp%d failed\n", vp->id); 2760 } 2761 } 2762 2763 ret = vop2_find_rgb_encoder(vop2); 2764 if (ret >= 0) { 2765 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, 2766 vop2->drm, ret); 2767 if (IS_ERR(vop2->rgb)) { 2768 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { 2769 ret = PTR_ERR(vop2->rgb); 2770 goto err_crtcs; 2771 } 2772 vop2->rgb = NULL; 2773 } 2774 } 2775 2776 rockchip_drm_dma_init_device(vop2->drm, vop2->dev); 2777 2778 pm_runtime_enable(&pdev->dev); 2779 2780 return 0; 2781 2782 err_crtcs: 2783 vop2_destroy_crtcs(vop2); 2784 2785 return ret; 2786 } 2787 2788 static void vop2_unbind(struct device *dev, struct device *master, void *data) 2789 { 2790 struct vop2 *vop2 = dev_get_drvdata(dev); 2791 2792 pm_runtime_disable(dev); 2793 2794 if (vop2->rgb) 2795 rockchip_rgb_fini(vop2->rgb); 2796 2797 vop2_destroy_crtcs(vop2); 2798 } 2799 2800 const struct component_ops vop2_component_ops = { 2801 .bind = vop2_bind, 2802 .unbind = vop2_unbind, 2803 }; 2804 EXPORT_SYMBOL_GPL(vop2_component_ops); 2805