1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/swab.h> 21 22 #include <drm/drm.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_uapi.h> 25 #include <drm/drm_blend.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_debugfs.h> 28 #include <drm/drm_flip_work.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #include <uapi/linux/videodev2.h> 34 #include <dt-bindings/soc/rockchip,vop2.h> 35 36 #include "rockchip_drm_drv.h" 37 #include "rockchip_drm_gem.h" 38 #include "rockchip_drm_fb.h" 39 #include "rockchip_drm_vop2.h" 40 #include "rockchip_rgb.h" 41 42 /* 43 * VOP2 architecture 44 * 45 +----------+ +-------------+ +-----------+ 46 | Cluster | | Sel 1 from 6| | 1 from 3 | 47 | window0 | | Layer0 | | RGB | 48 +----------+ +-------------+ +---------------+ +-------------+ +-----------+ 49 +----------+ +-------------+ |N from 6 layers| | | 50 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ 51 | window1 | | Layer1 | | | | | | 1 from 3 | 52 +----------+ +-------------+ +---------------+ +-------------+ | LVDS | 53 +----------+ +-------------+ +-----------+ 54 | Esmart | | Sel 1 from 6| 55 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ 56 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | 57 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | 58 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ 59 | Window1 | | Layer3 | +---------------+ +-------------+ 60 +----------+ +-------------+ +-----------+ 61 +----------+ +-------------+ | 1 from 3 | 62 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | 63 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ 64 +----------+ +-------------+ | Overlay2 +--->| Video Port2 | 65 +----------+ +-------------+ | | | | +-----------+ 66 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | 67 | Window1 | | Layer5 | | eDP | 68 +----------+ +-------------+ +-----------+ 69 * 70 */ 71 72 enum vop2_data_format { 73 VOP2_FMT_ARGB8888 = 0, 74 VOP2_FMT_RGB888, 75 VOP2_FMT_RGB565, 76 VOP2_FMT_XRGB101010, 77 VOP2_FMT_YUV420SP, 78 VOP2_FMT_YUV422SP, 79 VOP2_FMT_YUV444SP, 80 VOP2_FMT_YUYV422 = 8, 81 VOP2_FMT_YUYV420, 82 VOP2_FMT_VYUY422, 83 VOP2_FMT_VYUY420, 84 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, 85 VOP2_FMT_YUV420SP_TILE_16x2, 86 VOP2_FMT_YUV422SP_TILE_8x4, 87 VOP2_FMT_YUV422SP_TILE_16x2, 88 VOP2_FMT_YUV420SP_10, 89 VOP2_FMT_YUV422SP_10, 90 VOP2_FMT_YUV444SP_10, 91 }; 92 93 enum vop2_afbc_format { 94 VOP2_AFBC_FMT_RGB565, 95 VOP2_AFBC_FMT_ARGB2101010 = 2, 96 VOP2_AFBC_FMT_YUV420_10BIT, 97 VOP2_AFBC_FMT_RGB888, 98 VOP2_AFBC_FMT_ARGB8888, 99 VOP2_AFBC_FMT_YUV420 = 9, 100 VOP2_AFBC_FMT_YUV422 = 0xb, 101 VOP2_AFBC_FMT_YUV422_10BIT = 0xe, 102 VOP2_AFBC_FMT_INVALID = -1, 103 }; 104 105 union vop2_alpha_ctrl { 106 u32 val; 107 struct { 108 /* [0:1] */ 109 u32 color_mode:1; 110 u32 alpha_mode:1; 111 /* [2:3] */ 112 u32 blend_mode:2; 113 u32 alpha_cal_mode:1; 114 /* [5:7] */ 115 u32 factor_mode:3; 116 /* [8:9] */ 117 u32 alpha_en:1; 118 u32 src_dst_swap:1; 119 u32 reserved:6; 120 /* [16:23] */ 121 u32 glb_alpha:8; 122 } bits; 123 }; 124 125 struct vop2_alpha { 126 union vop2_alpha_ctrl src_color_ctrl; 127 union vop2_alpha_ctrl dst_color_ctrl; 128 union vop2_alpha_ctrl src_alpha_ctrl; 129 union vop2_alpha_ctrl dst_alpha_ctrl; 130 }; 131 132 struct vop2_alpha_config { 133 bool src_premulti_en; 134 bool dst_premulti_en; 135 bool src_pixel_alpha_en; 136 bool dst_pixel_alpha_en; 137 u16 src_glb_alpha_value; 138 u16 dst_glb_alpha_value; 139 }; 140 141 struct vop2_win { 142 struct vop2 *vop2; 143 struct drm_plane base; 144 const struct vop2_win_data *data; 145 struct regmap_field *reg[VOP2_WIN_MAX_REG]; 146 147 /** 148 * @win_id: graphic window id, a cluster may be split into two 149 * graphics windows. 150 */ 151 u8 win_id; 152 u8 delay; 153 u32 offset; 154 155 enum drm_plane_type type; 156 }; 157 158 struct vop2_video_port { 159 struct drm_crtc crtc; 160 struct vop2 *vop2; 161 struct clk *dclk; 162 unsigned int id; 163 const struct vop2_video_port_regs *regs; 164 const struct vop2_video_port_data *data; 165 166 struct completion dsp_hold_completion; 167 168 /** 169 * @win_mask: Bitmask of windows attached to the video port; 170 */ 171 u32 win_mask; 172 173 struct vop2_win *primary_plane; 174 struct drm_pending_vblank_event *event; 175 176 unsigned int nlayers; 177 }; 178 179 struct vop2 { 180 struct device *dev; 181 struct drm_device *drm; 182 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; 183 184 const struct vop2_data *data; 185 /* 186 * Number of windows that are registered as plane, may be less than the 187 * total number of hardware windows. 188 */ 189 u32 registered_num_wins; 190 191 void __iomem *regs; 192 struct regmap *map; 193 194 struct regmap *grf; 195 196 /* physical map length of vop2 register */ 197 u32 len; 198 199 void __iomem *lut_regs; 200 201 /* protects crtc enable/disable */ 202 struct mutex vop2_lock; 203 204 int irq; 205 206 /* 207 * Some global resources are shared between all video ports(crtcs), so 208 * we need a ref counter here. 209 */ 210 unsigned int enable_count; 211 struct clk *hclk; 212 struct clk *aclk; 213 214 /* optional internal rgb encoder */ 215 struct rockchip_rgb *rgb; 216 217 /* must be put at the end of the struct */ 218 struct vop2_win win[]; 219 }; 220 221 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) 222 { 223 return container_of(crtc, struct vop2_video_port, crtc); 224 } 225 226 static struct vop2_win *to_vop2_win(struct drm_plane *p) 227 { 228 return container_of(p, struct vop2_win, base); 229 } 230 231 static void vop2_lock(struct vop2 *vop2) 232 { 233 mutex_lock(&vop2->vop2_lock); 234 } 235 236 static void vop2_unlock(struct vop2 *vop2) 237 { 238 mutex_unlock(&vop2->vop2_lock); 239 } 240 241 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 242 { 243 regmap_write(vop2->map, offset, v); 244 } 245 246 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) 247 { 248 regmap_write(vp->vop2->map, vp->data->offset + offset, v); 249 } 250 251 static u32 vop2_readl(struct vop2 *vop2, u32 offset) 252 { 253 u32 val; 254 255 regmap_read(vop2->map, offset, &val); 256 257 return val; 258 } 259 260 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) 261 { 262 regmap_field_write(win->reg[reg], v); 263 } 264 265 static bool vop2_cluster_window(const struct vop2_win *win) 266 { 267 return win->data->feature & WIN_FEATURE_CLUSTER; 268 } 269 270 static void vop2_cfg_done(struct vop2_video_port *vp) 271 { 272 struct vop2 *vop2 = vp->vop2; 273 274 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, 275 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 276 } 277 278 static void vop2_win_disable(struct vop2_win *win) 279 { 280 vop2_win_write(win, VOP2_WIN_ENABLE, 0); 281 282 if (vop2_cluster_window(win)) 283 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); 284 } 285 286 static enum vop2_data_format vop2_convert_format(u32 format) 287 { 288 switch (format) { 289 case DRM_FORMAT_XRGB8888: 290 case DRM_FORMAT_ARGB8888: 291 case DRM_FORMAT_XBGR8888: 292 case DRM_FORMAT_ABGR8888: 293 return VOP2_FMT_ARGB8888; 294 case DRM_FORMAT_RGB888: 295 case DRM_FORMAT_BGR888: 296 return VOP2_FMT_RGB888; 297 case DRM_FORMAT_RGB565: 298 case DRM_FORMAT_BGR565: 299 return VOP2_FMT_RGB565; 300 case DRM_FORMAT_NV12: 301 return VOP2_FMT_YUV420SP; 302 case DRM_FORMAT_NV16: 303 return VOP2_FMT_YUV422SP; 304 case DRM_FORMAT_NV24: 305 return VOP2_FMT_YUV444SP; 306 case DRM_FORMAT_YUYV: 307 case DRM_FORMAT_YVYU: 308 return VOP2_FMT_VYUY422; 309 case DRM_FORMAT_VYUY: 310 case DRM_FORMAT_UYVY: 311 return VOP2_FMT_YUYV422; 312 default: 313 DRM_ERROR("unsupported format[%08x]\n", format); 314 return -EINVAL; 315 } 316 } 317 318 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) 319 { 320 switch (format) { 321 case DRM_FORMAT_XRGB8888: 322 case DRM_FORMAT_ARGB8888: 323 case DRM_FORMAT_XBGR8888: 324 case DRM_FORMAT_ABGR8888: 325 return VOP2_AFBC_FMT_ARGB8888; 326 case DRM_FORMAT_RGB888: 327 case DRM_FORMAT_BGR888: 328 return VOP2_AFBC_FMT_RGB888; 329 case DRM_FORMAT_RGB565: 330 case DRM_FORMAT_BGR565: 331 return VOP2_AFBC_FMT_RGB565; 332 case DRM_FORMAT_NV12: 333 return VOP2_AFBC_FMT_YUV420; 334 case DRM_FORMAT_NV16: 335 return VOP2_AFBC_FMT_YUV422; 336 default: 337 return VOP2_AFBC_FMT_INVALID; 338 } 339 340 return VOP2_AFBC_FMT_INVALID; 341 } 342 343 static bool vop2_win_rb_swap(u32 format) 344 { 345 switch (format) { 346 case DRM_FORMAT_XBGR8888: 347 case DRM_FORMAT_ABGR8888: 348 case DRM_FORMAT_BGR888: 349 case DRM_FORMAT_BGR565: 350 return true; 351 default: 352 return false; 353 } 354 } 355 356 static bool vop2_afbc_rb_swap(u32 format) 357 { 358 switch (format) { 359 case DRM_FORMAT_NV24: 360 return true; 361 default: 362 return false; 363 } 364 } 365 366 static bool vop2_afbc_uv_swap(u32 format) 367 { 368 switch (format) { 369 case DRM_FORMAT_NV12: 370 case DRM_FORMAT_NV16: 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 static bool vop2_win_uv_swap(u32 format) 378 { 379 switch (format) { 380 case DRM_FORMAT_NV12: 381 case DRM_FORMAT_NV16: 382 case DRM_FORMAT_NV24: 383 return true; 384 default: 385 return false; 386 } 387 } 388 389 static bool vop2_win_dither_up(u32 format) 390 { 391 switch (format) { 392 case DRM_FORMAT_BGR565: 393 case DRM_FORMAT_RGB565: 394 return true; 395 default: 396 return false; 397 } 398 } 399 400 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) 401 { 402 /* 403 * FIXME: 404 * 405 * There is no media type for YUV444 output, 406 * so when out_mode is AAAA or P888, assume output is YUV444 on 407 * yuv format. 408 * 409 * From H/W testing, YUV444 mode need a rb swap. 410 */ 411 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 412 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 413 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 414 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 415 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 416 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 417 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 418 output_mode == ROCKCHIP_OUT_MODE_P888))) 419 return true; 420 else 421 return false; 422 } 423 424 static bool is_yuv_output(u32 bus_format) 425 { 426 switch (bus_format) { 427 case MEDIA_BUS_FMT_YUV8_1X24: 428 case MEDIA_BUS_FMT_YUV10_1X30: 429 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 430 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 431 case MEDIA_BUS_FMT_YUYV8_2X8: 432 case MEDIA_BUS_FMT_YVYU8_2X8: 433 case MEDIA_BUS_FMT_UYVY8_2X8: 434 case MEDIA_BUS_FMT_VYUY8_2X8: 435 case MEDIA_BUS_FMT_YUYV8_1X16: 436 case MEDIA_BUS_FMT_YVYU8_1X16: 437 case MEDIA_BUS_FMT_UYVY8_1X16: 438 case MEDIA_BUS_FMT_VYUY8_1X16: 439 return true; 440 default: 441 return false; 442 } 443 } 444 445 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) 446 { 447 int i; 448 449 if (modifier == DRM_FORMAT_MOD_LINEAR) 450 return false; 451 452 for (i = 0 ; i < plane->modifier_count; i++) 453 if (plane->modifiers[i] == modifier) 454 return true; 455 456 return false; 457 } 458 459 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, 460 u64 modifier) 461 { 462 struct vop2_win *win = to_vop2_win(plane); 463 struct vop2 *vop2 = win->vop2; 464 465 if (modifier == DRM_FORMAT_MOD_INVALID) 466 return false; 467 468 if (modifier == DRM_FORMAT_MOD_LINEAR) 469 return true; 470 471 if (!rockchip_afbc(plane, modifier)) { 472 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n", 473 modifier); 474 475 return false; 476 } 477 478 return vop2_convert_afbc_format(format) >= 0; 479 } 480 481 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, 482 bool afbc_half_block_en) 483 { 484 struct drm_rect *src = &pstate->src; 485 struct drm_framebuffer *fb = pstate->fb; 486 u32 bpp = fb->format->cpp[0] * 8; 487 u32 vir_width = (fb->pitches[0] << 3) / bpp; 488 u32 width = drm_rect_width(src) >> 16; 489 u32 height = drm_rect_height(src) >> 16; 490 u32 act_xoffset = src->x1 >> 16; 491 u32 act_yoffset = src->y1 >> 16; 492 u32 align16_crop = 0; 493 u32 align64_crop = 0; 494 u32 height_tmp; 495 u8 tx, ty; 496 u8 bottom_crop_line_num = 0; 497 498 /* 16 pixel align */ 499 if (height & 0xf) 500 align16_crop = 16 - (height & 0xf); 501 502 height_tmp = height + align16_crop; 503 504 /* 64 pixel align */ 505 if (height_tmp & 0x3f) 506 align64_crop = 64 - (height_tmp & 0x3f); 507 508 bottom_crop_line_num = align16_crop + align64_crop; 509 510 switch (pstate->rotation & 511 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | 512 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { 513 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: 514 tx = 16 - ((act_xoffset + width) & 0xf); 515 ty = bottom_crop_line_num - act_yoffset; 516 break; 517 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: 518 tx = bottom_crop_line_num - act_yoffset; 519 ty = vir_width - width - act_xoffset; 520 break; 521 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: 522 tx = act_yoffset; 523 ty = act_xoffset; 524 break; 525 case DRM_MODE_REFLECT_X: 526 tx = 16 - ((act_xoffset + width) & 0xf); 527 ty = act_yoffset; 528 break; 529 case DRM_MODE_REFLECT_Y: 530 tx = act_xoffset; 531 ty = bottom_crop_line_num - act_yoffset; 532 break; 533 case DRM_MODE_ROTATE_90: 534 tx = bottom_crop_line_num - act_yoffset; 535 ty = act_xoffset; 536 break; 537 case DRM_MODE_ROTATE_270: 538 tx = act_yoffset; 539 ty = vir_width - width - act_xoffset; 540 break; 541 case 0: 542 tx = act_xoffset; 543 ty = act_yoffset; 544 break; 545 } 546 547 if (afbc_half_block_en) 548 ty &= 0x7f; 549 550 #define TRANSFORM_XOFFSET GENMASK(7, 0) 551 #define TRANSFORM_YOFFSET GENMASK(23, 16) 552 return FIELD_PREP(TRANSFORM_XOFFSET, tx) | 553 FIELD_PREP(TRANSFORM_YOFFSET, ty); 554 } 555 556 /* 557 * A Cluster window has 2048 x 16 line buffer, which can 558 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. 559 * for Cluster_lb_mode register: 560 * 0: half mode, for plane input width range 2048 ~ 4096 561 * 1: half mode, for cluster work at 2 * 2048 plane mode 562 * 2: half mode, for rotate_90/270 mode 563 * 564 */ 565 static int vop2_get_cluster_lb_mode(struct vop2_win *win, 566 struct drm_plane_state *pstate) 567 { 568 if ((pstate->rotation & DRM_MODE_ROTATE_270) || 569 (pstate->rotation & DRM_MODE_ROTATE_90)) 570 return 2; 571 else 572 return 0; 573 } 574 575 static u16 vop2_scale_factor(u32 src, u32 dst) 576 { 577 u32 fac; 578 int shift; 579 580 if (src == dst) 581 return 0; 582 583 if (dst < 2) 584 return U16_MAX; 585 586 if (src < 2) 587 return 0; 588 589 if (src > dst) 590 shift = 12; 591 else 592 shift = 16; 593 594 src--; 595 dst--; 596 597 fac = DIV_ROUND_UP(src << shift, dst) - 1; 598 599 if (fac > U16_MAX) 600 return U16_MAX; 601 602 return fac; 603 } 604 605 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, 606 u32 src_w, u32 src_h, u32 dst_w, 607 u32 dst_h, u32 pixel_format) 608 { 609 const struct drm_format_info *info; 610 u16 hor_scl_mode, ver_scl_mode; 611 u16 hscl_filter_mode, vscl_filter_mode; 612 u8 gt2 = 0; 613 u8 gt4 = 0; 614 u32 val; 615 616 info = drm_format_info(pixel_format); 617 618 if (src_h >= (4 * dst_h)) { 619 gt4 = 1; 620 src_h >>= 2; 621 } else if (src_h >= (2 * dst_h)) { 622 gt2 = 1; 623 src_h >>= 1; 624 } 625 626 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 627 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 628 629 if (hor_scl_mode == SCALE_UP) 630 hscl_filter_mode = VOP2_SCALE_UP_BIC; 631 else 632 hscl_filter_mode = VOP2_SCALE_DOWN_BIL; 633 634 if (ver_scl_mode == SCALE_UP) 635 vscl_filter_mode = VOP2_SCALE_UP_BIL; 636 else 637 vscl_filter_mode = VOP2_SCALE_DOWN_BIL; 638 639 /* 640 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 641 * at scale down mode 642 */ 643 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 644 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 645 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", 646 win->data->name, dst_w); 647 dst_w++; 648 } 649 } 650 651 val = vop2_scale_factor(src_w, dst_w); 652 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); 653 val = vop2_scale_factor(src_h, dst_h); 654 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); 655 656 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); 657 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); 658 659 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); 660 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); 661 662 if (vop2_cluster_window(win)) 663 return; 664 665 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); 666 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); 667 668 if (info->is_yuv) { 669 src_w /= info->hsub; 670 src_h /= info->vsub; 671 672 gt4 = 0; 673 gt2 = 0; 674 675 if (src_h >= (4 * dst_h)) { 676 gt4 = 1; 677 src_h >>= 2; 678 } else if (src_h >= (2 * dst_h)) { 679 gt2 = 1; 680 src_h >>= 1; 681 } 682 683 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 684 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 685 686 val = vop2_scale_factor(src_w, dst_w); 687 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); 688 689 val = vop2_scale_factor(src_h, dst_h); 690 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); 691 692 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); 693 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); 694 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); 695 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); 696 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); 697 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); 698 } 699 } 700 701 static int vop2_convert_csc_mode(int csc_mode) 702 { 703 switch (csc_mode) { 704 case V4L2_COLORSPACE_SMPTE170M: 705 case V4L2_COLORSPACE_470_SYSTEM_M: 706 case V4L2_COLORSPACE_470_SYSTEM_BG: 707 return CSC_BT601L; 708 case V4L2_COLORSPACE_REC709: 709 case V4L2_COLORSPACE_SMPTE240M: 710 case V4L2_COLORSPACE_DEFAULT: 711 return CSC_BT709L; 712 case V4L2_COLORSPACE_JPEG: 713 return CSC_BT601F; 714 case V4L2_COLORSPACE_BT2020: 715 return CSC_BT2020; 716 default: 717 return CSC_BT709L; 718 } 719 } 720 721 /* 722 * colorspace path: 723 * Input Win csc Output 724 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) 725 * RGB --> R2Y __/ 726 * 727 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) 728 * RGB --> 709To2020->R2Y __/ 729 * 730 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) 731 * RGB --> R2Y __/ 732 * 733 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) 734 * RGB --> 709To2020->R2Y __/ 735 * 736 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) 737 * RGB --> R2Y __/ 738 * 739 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) 740 * RGB --> R2Y(601) __/ 741 * 742 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) 743 * RGB --> bypass __/ 744 * 745 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) 746 * 747 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) 748 * 749 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) 750 * 751 * 11. RGB --> bypass --> RGB_OUTPUT(709) 752 */ 753 754 static void vop2_setup_csc_mode(struct vop2_video_port *vp, 755 struct vop2_win *win, 756 struct drm_plane_state *pstate) 757 { 758 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); 759 int is_input_yuv = pstate->fb->format->is_yuv; 760 int is_output_yuv = is_yuv_output(vcstate->bus_format); 761 int input_csc = V4L2_COLORSPACE_DEFAULT; 762 int output_csc = vcstate->color_space; 763 bool r2y_en, y2r_en; 764 int csc_mode; 765 766 if (is_input_yuv && !is_output_yuv) { 767 y2r_en = true; 768 r2y_en = false; 769 csc_mode = vop2_convert_csc_mode(input_csc); 770 } else if (!is_input_yuv && is_output_yuv) { 771 y2r_en = false; 772 r2y_en = true; 773 csc_mode = vop2_convert_csc_mode(output_csc); 774 } else { 775 y2r_en = false; 776 r2y_en = false; 777 csc_mode = false; 778 } 779 780 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); 781 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); 782 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); 783 } 784 785 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) 786 { 787 struct vop2 *vop2 = vp->vop2; 788 789 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); 790 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); 791 } 792 793 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) 794 { 795 struct vop2 *vop2 = vp->vop2; 796 797 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); 798 } 799 800 static int vop2_core_clks_prepare_enable(struct vop2 *vop2) 801 { 802 int ret; 803 804 ret = clk_prepare_enable(vop2->hclk); 805 if (ret < 0) { 806 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); 807 return ret; 808 } 809 810 ret = clk_prepare_enable(vop2->aclk); 811 if (ret < 0) { 812 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); 813 goto err; 814 } 815 816 return 0; 817 err: 818 clk_disable_unprepare(vop2->hclk); 819 820 return ret; 821 } 822 823 static void vop2_enable(struct vop2 *vop2) 824 { 825 int ret; 826 827 ret = pm_runtime_resume_and_get(vop2->dev); 828 if (ret < 0) { 829 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); 830 return; 831 } 832 833 ret = vop2_core_clks_prepare_enable(vop2); 834 if (ret) { 835 pm_runtime_put_sync(vop2->dev); 836 return; 837 } 838 839 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); 840 if (ret) { 841 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); 842 return; 843 } 844 845 regcache_sync(vop2->map); 846 847 if (vop2->data->soc_id == 3566) 848 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); 849 850 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 851 852 /* 853 * Disable auto gating, this is a workaround to 854 * avoid display image shift when a window enabled. 855 */ 856 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, 857 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); 858 859 vop2_writel(vop2, RK3568_SYS0_INT_CLR, 860 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 861 vop2_writel(vop2, RK3568_SYS0_INT_EN, 862 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 863 vop2_writel(vop2, RK3568_SYS1_INT_CLR, 864 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 865 vop2_writel(vop2, RK3568_SYS1_INT_EN, 866 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 867 } 868 869 static void vop2_disable(struct vop2 *vop2) 870 { 871 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); 872 873 pm_runtime_put_sync(vop2->dev); 874 875 regcache_mark_dirty(vop2->map); 876 877 clk_disable_unprepare(vop2->aclk); 878 clk_disable_unprepare(vop2->hclk); 879 } 880 881 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, 882 struct drm_atomic_state *state) 883 { 884 struct vop2_video_port *vp = to_vop2_video_port(crtc); 885 struct vop2 *vop2 = vp->vop2; 886 struct drm_crtc_state *old_crtc_state; 887 int ret; 888 889 vop2_lock(vop2); 890 891 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 892 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 893 894 drm_crtc_vblank_off(crtc); 895 896 /* 897 * Vop standby will take effect at end of current frame, 898 * if dsp hold valid irq happen, it means standby complete. 899 * 900 * we must wait standby complete when we want to disable aclk, 901 * if not, memory bus maybe dead. 902 */ 903 reinit_completion(&vp->dsp_hold_completion); 904 905 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); 906 907 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); 908 909 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, 910 msecs_to_jiffies(50)); 911 if (!ret) 912 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); 913 914 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); 915 916 clk_disable_unprepare(vp->dclk); 917 918 vop2->enable_count--; 919 920 if (!vop2->enable_count) 921 vop2_disable(vop2); 922 923 vop2_unlock(vop2); 924 925 if (crtc->state->event && !crtc->state->active) { 926 spin_lock_irq(&crtc->dev->event_lock); 927 drm_crtc_send_vblank_event(crtc, crtc->state->event); 928 spin_unlock_irq(&crtc->dev->event_lock); 929 930 crtc->state->event = NULL; 931 } 932 } 933 934 static int vop2_plane_atomic_check(struct drm_plane *plane, 935 struct drm_atomic_state *astate) 936 { 937 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); 938 struct drm_framebuffer *fb = pstate->fb; 939 struct drm_crtc *crtc = pstate->crtc; 940 struct drm_crtc_state *cstate; 941 struct vop2_video_port *vp; 942 struct vop2 *vop2; 943 const struct vop2_data *vop2_data; 944 struct drm_rect *dest = &pstate->dst; 945 struct drm_rect *src = &pstate->src; 946 int min_scale = FRAC_16_16(1, 8); 947 int max_scale = FRAC_16_16(8, 1); 948 int format; 949 int ret; 950 951 if (!crtc) 952 return 0; 953 954 vp = to_vop2_video_port(crtc); 955 vop2 = vp->vop2; 956 vop2_data = vop2->data; 957 958 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); 959 if (WARN_ON(!cstate)) 960 return -EINVAL; 961 962 ret = drm_atomic_helper_check_plane_state(pstate, cstate, 963 min_scale, max_scale, 964 true, true); 965 if (ret) 966 return ret; 967 968 if (!pstate->visible) 969 return 0; 970 971 format = vop2_convert_format(fb->format->format); 972 if (format < 0) 973 return format; 974 975 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || 976 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { 977 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", 978 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, 979 drm_rect_width(dest), drm_rect_height(dest)); 980 pstate->visible = false; 981 return 0; 982 } 983 984 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || 985 drm_rect_height(src) >> 16 > vop2_data->max_input.height) { 986 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", 987 drm_rect_width(src) >> 16, 988 drm_rect_height(src) >> 16, 989 vop2_data->max_input.width, 990 vop2_data->max_input.height); 991 return -EINVAL; 992 } 993 994 /* 995 * Src.x1 can be odd when do clip, but yuv plane start point 996 * need align with 2 pixel. 997 */ 998 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { 999 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); 1000 return -EINVAL; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static void vop2_plane_atomic_disable(struct drm_plane *plane, 1007 struct drm_atomic_state *state) 1008 { 1009 struct drm_plane_state *old_pstate = NULL; 1010 struct vop2_win *win = to_vop2_win(plane); 1011 struct vop2 *vop2 = win->vop2; 1012 1013 drm_dbg(vop2->drm, "%s disable\n", win->data->name); 1014 1015 if (state) 1016 old_pstate = drm_atomic_get_old_plane_state(state, plane); 1017 if (old_pstate && !old_pstate->crtc) 1018 return; 1019 1020 vop2_win_disable(win); 1021 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); 1022 } 1023 1024 /* 1025 * The color key is 10 bit, so all format should 1026 * convert to 10 bit here. 1027 */ 1028 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) 1029 { 1030 struct drm_plane_state *pstate = plane->state; 1031 struct drm_framebuffer *fb = pstate->fb; 1032 struct vop2_win *win = to_vop2_win(plane); 1033 u32 color_key_en = 0; 1034 u32 r = 0; 1035 u32 g = 0; 1036 u32 b = 0; 1037 1038 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { 1039 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); 1040 return; 1041 } 1042 1043 switch (fb->format->format) { 1044 case DRM_FORMAT_RGB565: 1045 case DRM_FORMAT_BGR565: 1046 r = (color_key & 0xf800) >> 11; 1047 g = (color_key & 0x7e0) >> 5; 1048 b = (color_key & 0x1f); 1049 r <<= 5; 1050 g <<= 4; 1051 b <<= 5; 1052 color_key_en = 1; 1053 break; 1054 case DRM_FORMAT_XRGB8888: 1055 case DRM_FORMAT_ARGB8888: 1056 case DRM_FORMAT_XBGR8888: 1057 case DRM_FORMAT_ABGR8888: 1058 case DRM_FORMAT_RGB888: 1059 case DRM_FORMAT_BGR888: 1060 r = (color_key & 0xff0000) >> 16; 1061 g = (color_key & 0xff00) >> 8; 1062 b = (color_key & 0xff); 1063 r <<= 2; 1064 g <<= 2; 1065 b <<= 2; 1066 color_key_en = 1; 1067 break; 1068 } 1069 1070 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); 1071 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); 1072 } 1073 1074 static void vop2_plane_atomic_update(struct drm_plane *plane, 1075 struct drm_atomic_state *state) 1076 { 1077 struct drm_plane_state *pstate = plane->state; 1078 struct drm_crtc *crtc = pstate->crtc; 1079 struct vop2_win *win = to_vop2_win(plane); 1080 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1081 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1082 struct vop2 *vop2 = win->vop2; 1083 struct drm_framebuffer *fb = pstate->fb; 1084 u32 bpp = fb->format->cpp[0] * 8; 1085 u32 actual_w, actual_h, dsp_w, dsp_h; 1086 u32 act_info, dsp_info; 1087 u32 format; 1088 u32 afbc_format; 1089 u32 rb_swap; 1090 u32 uv_swap; 1091 struct drm_rect *src = &pstate->src; 1092 struct drm_rect *dest = &pstate->dst; 1093 u32 afbc_tile_num; 1094 u32 transform_offset; 1095 bool dither_up; 1096 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1097 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1098 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1099 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1100 struct rockchip_gem_object *rk_obj; 1101 unsigned long offset; 1102 bool afbc_en; 1103 dma_addr_t yrgb_mst; 1104 dma_addr_t uv_mst; 1105 1106 /* 1107 * can't update plane when vop2 is disabled. 1108 */ 1109 if (WARN_ON(!crtc)) 1110 return; 1111 1112 if (!pstate->visible) { 1113 vop2_plane_atomic_disable(plane, state); 1114 return; 1115 } 1116 1117 afbc_en = rockchip_afbc(plane, fb->modifier); 1118 1119 offset = (src->x1 >> 16) * fb->format->cpp[0]; 1120 1121 /* 1122 * AFBC HDR_PTR must set to the zero offset of the framebuffer. 1123 */ 1124 if (afbc_en) 1125 offset = 0; 1126 else if (pstate->rotation & DRM_MODE_REFLECT_Y) 1127 offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; 1128 else 1129 offset += (src->y1 >> 16) * fb->pitches[0]; 1130 1131 rk_obj = to_rockchip_obj(fb->obj[0]); 1132 1133 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 1134 if (fb->format->is_yuv) { 1135 int hsub = fb->format->hsub; 1136 int vsub = fb->format->vsub; 1137 1138 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; 1139 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 1140 1141 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) 1142 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; 1143 1144 rk_obj = to_rockchip_obj(fb->obj[0]); 1145 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; 1146 } 1147 1148 actual_w = drm_rect_width(src) >> 16; 1149 actual_h = drm_rect_height(src) >> 16; 1150 dsp_w = drm_rect_width(dest); 1151 1152 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { 1153 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", 1154 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); 1155 dsp_w = adjusted_mode->hdisplay - dest->x1; 1156 if (dsp_w < 4) 1157 dsp_w = 4; 1158 actual_w = dsp_w * actual_w / drm_rect_width(dest); 1159 } 1160 1161 dsp_h = drm_rect_height(dest); 1162 1163 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { 1164 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", 1165 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); 1166 dsp_h = adjusted_mode->vdisplay - dest->y1; 1167 if (dsp_h < 4) 1168 dsp_h = 4; 1169 actual_h = dsp_h * actual_h / drm_rect_height(dest); 1170 } 1171 1172 /* 1173 * This is workaround solution for IC design: 1174 * esmart can't support scale down when actual_w % 16 == 1. 1175 */ 1176 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 1177 if (actual_w > dsp_w && (actual_w & 0xf) == 1) { 1178 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", 1179 vp->id, win->data->name, actual_w); 1180 actual_w -= 1; 1181 } 1182 } 1183 1184 if (afbc_en && actual_w % 4) { 1185 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", 1186 vp->id, win->data->name, actual_w); 1187 actual_w = ALIGN_DOWN(actual_w, 4); 1188 } 1189 1190 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 1191 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); 1192 1193 format = vop2_convert_format(fb->format->format); 1194 1195 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", 1196 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, 1197 dest->x1, dest->y1, 1198 &fb->format->format, 1199 afbc_en ? "AFBC" : "", &yrgb_mst); 1200 1201 if (afbc_en) { 1202 u32 stride; 1203 1204 /* the afbc superblock is 16 x 16 */ 1205 afbc_format = vop2_convert_afbc_format(fb->format->format); 1206 1207 /* Enable color transform for YTR */ 1208 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 1209 afbc_format |= (1 << 4); 1210 1211 afbc_tile_num = ALIGN(actual_w, 16) >> 4; 1212 1213 /* 1214 * AFBC pic_vir_width is count by pixel, this is different 1215 * with WIN_VIR_STRIDE. 1216 */ 1217 stride = (fb->pitches[0] << 3) / bpp; 1218 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) 1219 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", 1220 vp->id, win->data->name, stride); 1221 1222 rb_swap = vop2_afbc_rb_swap(fb->format->format); 1223 uv_swap = vop2_afbc_uv_swap(fb->format->format); 1224 /* 1225 * This is a workaround for crazy IC design, Cluster 1226 * and Esmart/Smart use different format configuration map: 1227 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. 1228 * 1229 * This is one thing we can make the convert simple: 1230 * AFBCD decode all the YUV data to YUV444. So we just 1231 * set all the yuv 10 bit to YUV444_10. 1232 */ 1233 if (fb->format->is_yuv && bpp == 10) 1234 format = VOP2_CLUSTER_YUV444_10; 1235 1236 if (vop2_cluster_window(win)) 1237 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); 1238 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); 1239 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); 1240 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); 1241 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); 1242 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); 1243 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { 1244 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); 1245 transform_offset = vop2_afbc_transform_offset(pstate, false); 1246 } else { 1247 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); 1248 transform_offset = vop2_afbc_transform_offset(pstate, true); 1249 } 1250 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); 1251 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); 1252 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); 1253 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); 1254 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); 1255 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); 1256 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); 1257 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); 1258 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); 1259 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); 1260 } else { 1261 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); 1262 } 1263 1264 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); 1265 1266 if (rotate_90 || rotate_270) { 1267 act_info = swahw32(act_info); 1268 actual_w = drm_rect_height(src) >> 16; 1269 actual_h = drm_rect_width(src) >> 16; 1270 } 1271 1272 vop2_win_write(win, VOP2_WIN_FORMAT, format); 1273 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); 1274 1275 rb_swap = vop2_win_rb_swap(fb->format->format); 1276 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); 1277 if (!vop2_cluster_window(win)) { 1278 uv_swap = vop2_win_uv_swap(fb->format->format); 1279 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); 1280 } 1281 1282 if (fb->format->is_yuv) { 1283 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); 1284 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); 1285 } 1286 1287 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); 1288 if (!vop2_cluster_window(win)) 1289 vop2_plane_setup_color_key(plane, 0); 1290 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); 1291 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); 1292 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); 1293 1294 vop2_setup_csc_mode(vp, win, pstate); 1295 1296 dither_up = vop2_win_dither_up(fb->format->format); 1297 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); 1298 1299 vop2_win_write(win, VOP2_WIN_ENABLE, 1); 1300 1301 if (vop2_cluster_window(win)) { 1302 int lb_mode = vop2_get_cluster_lb_mode(win, pstate); 1303 1304 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); 1305 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); 1306 } 1307 } 1308 1309 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { 1310 .atomic_check = vop2_plane_atomic_check, 1311 .atomic_update = vop2_plane_atomic_update, 1312 .atomic_disable = vop2_plane_atomic_disable, 1313 }; 1314 1315 static const struct drm_plane_funcs vop2_plane_funcs = { 1316 .update_plane = drm_atomic_helper_update_plane, 1317 .disable_plane = drm_atomic_helper_disable_plane, 1318 .destroy = drm_plane_cleanup, 1319 .reset = drm_atomic_helper_plane_reset, 1320 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1321 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1322 .format_mod_supported = rockchip_vop2_mod_supported, 1323 }; 1324 1325 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) 1326 { 1327 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1328 1329 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); 1330 1331 return 0; 1332 } 1333 1334 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) 1335 { 1336 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1337 1338 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); 1339 } 1340 1341 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, 1342 const struct drm_display_mode *mode, 1343 struct drm_display_mode *adj_mode) 1344 { 1345 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | 1346 CRTC_STEREO_DOUBLE); 1347 1348 return true; 1349 } 1350 1351 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) 1352 { 1353 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1354 1355 switch (vcstate->bus_format) { 1356 case MEDIA_BUS_FMT_RGB565_1X16: 1357 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1358 break; 1359 case MEDIA_BUS_FMT_RGB666_1X18: 1360 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1361 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1362 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1363 *dsp_ctrl |= RGB888_TO_RGB666; 1364 break; 1365 case MEDIA_BUS_FMT_YUV8_1X24: 1366 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1367 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1368 break; 1369 default: 1370 break; 1371 } 1372 1373 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) 1374 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1375 1376 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, 1377 DITHER_DOWN_ALLEGRO); 1378 } 1379 1380 static void vop2_post_config(struct drm_crtc *crtc) 1381 { 1382 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1383 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1384 u16 vtotal = mode->crtc_vtotal; 1385 u16 hdisplay = mode->crtc_hdisplay; 1386 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1387 u16 vdisplay = mode->crtc_vdisplay; 1388 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1389 u32 left_margin = 100, right_margin = 100; 1390 u32 top_margin = 100, bottom_margin = 100; 1391 u16 hsize = hdisplay * (left_margin + right_margin) / 200; 1392 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; 1393 u16 hact_end, vact_end; 1394 u32 val; 1395 1396 vsize = rounddown(vsize, 2); 1397 hsize = rounddown(hsize, 2); 1398 hact_st += hdisplay * (100 - left_margin) / 200; 1399 hact_end = hact_st + hsize; 1400 val = hact_st << 16; 1401 val |= hact_end; 1402 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); 1403 vact_st += vdisplay * (100 - top_margin) / 200; 1404 vact_end = vact_st + vsize; 1405 val = vact_st << 16; 1406 val |= vact_end; 1407 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); 1408 val = scl_cal_scale2(vdisplay, vsize) << 16; 1409 val |= scl_cal_scale2(hdisplay, hsize); 1410 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); 1411 1412 val = 0; 1413 if (hdisplay != hsize) 1414 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; 1415 if (vdisplay != vsize) 1416 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; 1417 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); 1418 1419 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1420 u16 vact_st_f1 = vtotal + vact_st + 1; 1421 u16 vact_end_f1 = vact_st_f1 + vsize; 1422 1423 val = vact_st_f1 << 16 | vact_end_f1; 1424 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); 1425 } 1426 1427 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); 1428 } 1429 1430 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, 1431 u32 polflags) 1432 { 1433 struct vop2 *vop2 = vp->vop2; 1434 u32 die, dip; 1435 1436 die = vop2_readl(vop2, RK3568_DSP_IF_EN); 1437 dip = vop2_readl(vop2, RK3568_DSP_IF_POL); 1438 1439 switch (id) { 1440 case ROCKCHIP_VOP2_EP_RGB0: 1441 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX; 1442 die |= RK3568_SYS_DSP_INFACE_EN_RGB | 1443 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); 1444 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; 1445 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); 1446 if (polflags & POLFLAG_DCLK_INV) 1447 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); 1448 else 1449 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); 1450 break; 1451 case ROCKCHIP_VOP2_EP_HDMI0: 1452 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; 1453 die |= RK3568_SYS_DSP_INFACE_EN_HDMI | 1454 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); 1455 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL; 1456 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags); 1457 break; 1458 case ROCKCHIP_VOP2_EP_EDP0: 1459 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; 1460 die |= RK3568_SYS_DSP_INFACE_EN_EDP | 1461 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); 1462 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL; 1463 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags); 1464 break; 1465 case ROCKCHIP_VOP2_EP_MIPI0: 1466 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; 1467 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 | 1468 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); 1469 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; 1470 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); 1471 break; 1472 case ROCKCHIP_VOP2_EP_MIPI1: 1473 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX; 1474 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 | 1475 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); 1476 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; 1477 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); 1478 break; 1479 case ROCKCHIP_VOP2_EP_LVDS0: 1480 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX; 1481 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 | 1482 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); 1483 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; 1484 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); 1485 break; 1486 case ROCKCHIP_VOP2_EP_LVDS1: 1487 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX; 1488 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 | 1489 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); 1490 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; 1491 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); 1492 break; 1493 default: 1494 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); 1495 return; 1496 } 1497 1498 dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; 1499 1500 vop2_writel(vop2, RK3568_DSP_IF_EN, die); 1501 vop2_writel(vop2, RK3568_DSP_IF_POL, dip); 1502 } 1503 1504 static int us_to_vertical_line(struct drm_display_mode *mode, int us) 1505 { 1506 return us * mode->clock / mode->htotal / 1000; 1507 } 1508 1509 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 1510 struct drm_atomic_state *state) 1511 { 1512 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1513 struct vop2 *vop2 = vp->vop2; 1514 const struct vop2_data *vop2_data = vop2->data; 1515 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 1516 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1517 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1518 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1519 unsigned long clock = mode->crtc_clock * 1000; 1520 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1521 u16 hdisplay = mode->crtc_hdisplay; 1522 u16 htotal = mode->crtc_htotal; 1523 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1524 u16 hact_end = hact_st + hdisplay; 1525 u16 vdisplay = mode->crtc_vdisplay; 1526 u16 vtotal = mode->crtc_vtotal; 1527 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1528 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1529 u16 vact_end = vact_st + vdisplay; 1530 u8 out_mode; 1531 u32 dsp_ctrl = 0; 1532 int act_end; 1533 u32 val, polflags; 1534 int ret; 1535 struct drm_encoder *encoder; 1536 1537 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", 1538 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1539 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); 1540 1541 vop2_lock(vop2); 1542 1543 ret = clk_prepare_enable(vp->dclk); 1544 if (ret < 0) { 1545 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", 1546 vp->id, ret); 1547 vop2_unlock(vop2); 1548 return; 1549 } 1550 1551 if (!vop2->enable_count) 1552 vop2_enable(vop2); 1553 1554 vop2->enable_count++; 1555 1556 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); 1557 1558 polflags = 0; 1559 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 1560 polflags |= POLFLAG_DCLK_INV; 1561 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1562 polflags |= BIT(HSYNC_POSITIVE); 1563 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1564 polflags |= BIT(VSYNC_POSITIVE); 1565 1566 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1567 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1568 1569 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); 1570 } 1571 1572 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1573 !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 1574 out_mode = ROCKCHIP_OUT_MODE_P888; 1575 else 1576 out_mode = vcstate->output_mode; 1577 1578 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); 1579 1580 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) 1581 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; 1582 1583 if (is_yuv_output(vcstate->bus_format)) 1584 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; 1585 1586 vop2_dither_setup(crtc, &dsp_ctrl); 1587 1588 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); 1589 val = hact_st << 16; 1590 val |= hact_end; 1591 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); 1592 1593 val = vact_st << 16; 1594 val |= vact_end; 1595 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); 1596 1597 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1598 u16 vact_st_f1 = vtotal + vact_st + 1; 1599 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1600 1601 val = vact_st_f1 << 16 | vact_end_f1; 1602 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); 1603 1604 val = vtotal << 16 | (vtotal + vsync_len); 1605 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); 1606 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; 1607 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; 1608 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; 1609 vtotal += vtotal + 1; 1610 act_end = vact_end_f1; 1611 } else { 1612 act_end = vact_end; 1613 } 1614 1615 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), 1616 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); 1617 1618 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); 1619 1620 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1621 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; 1622 clock *= 2; 1623 } 1624 1625 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); 1626 1627 clk_set_rate(vp->dclk, clock); 1628 1629 vop2_post_config(crtc); 1630 1631 vop2_cfg_done(vp); 1632 1633 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 1634 1635 drm_crtc_vblank_on(crtc); 1636 1637 vop2_unlock(vop2); 1638 } 1639 1640 static int vop2_crtc_atomic_check(struct drm_crtc *crtc, 1641 struct drm_atomic_state *state) 1642 { 1643 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1644 struct drm_plane *plane; 1645 int nplanes = 0; 1646 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1647 1648 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) 1649 nplanes++; 1650 1651 if (nplanes > vp->nlayers) 1652 return -EINVAL; 1653 1654 return 0; 1655 } 1656 1657 static bool is_opaque(u16 alpha) 1658 { 1659 return (alpha >> 8) == 0xff; 1660 } 1661 1662 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config, 1663 struct vop2_alpha *alpha) 1664 { 1665 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; 1666 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; 1667 int src_color_mode = alpha_config->src_premulti_en ? 1668 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; 1669 int dst_color_mode = alpha_config->dst_premulti_en ? 1670 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; 1671 1672 alpha->src_color_ctrl.val = 0; 1673 alpha->dst_color_ctrl.val = 0; 1674 alpha->src_alpha_ctrl.val = 0; 1675 alpha->dst_alpha_ctrl.val = 0; 1676 1677 if (!alpha_config->src_pixel_alpha_en) 1678 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; 1679 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en) 1680 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX; 1681 else 1682 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; 1683 1684 alpha->src_color_ctrl.bits.alpha_en = 1; 1685 1686 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) { 1687 alpha->src_color_ctrl.bits.color_mode = src_color_mode; 1688 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; 1689 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) { 1690 alpha->src_color_ctrl.bits.color_mode = src_color_mode; 1691 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE; 1692 } else { 1693 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL; 1694 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; 1695 } 1696 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8; 1697 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1698 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1699 1700 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1701 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1702 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; 1703 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8; 1704 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode; 1705 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; 1706 1707 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1708 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode; 1709 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1710 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE; 1711 1712 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1713 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en) 1714 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX; 1715 else 1716 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; 1717 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION; 1718 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; 1719 } 1720 1721 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) 1722 { 1723 struct vop2_video_port *vp; 1724 int used_layer = 0; 1725 int i; 1726 1727 for (i = 0; i < port_id; i++) { 1728 vp = &vop2->vps[i]; 1729 used_layer += hweight32(vp->win_mask); 1730 } 1731 1732 return used_layer; 1733 } 1734 1735 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) 1736 { 1737 u32 offset = (main_win->data->phys_id * 0x10); 1738 struct vop2_alpha_config alpha_config; 1739 struct vop2_alpha alpha; 1740 struct drm_plane_state *bottom_win_pstate; 1741 bool src_pixel_alpha_en = false; 1742 u16 src_glb_alpha_val, dst_glb_alpha_val; 1743 bool premulti_en = false; 1744 bool swap = false; 1745 1746 /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */ 1747 bottom_win_pstate = main_win->base.state; 1748 src_glb_alpha_val = 0; 1749 dst_glb_alpha_val = main_win->base.state->alpha; 1750 1751 if (!bottom_win_pstate->fb) 1752 return; 1753 1754 alpha_config.src_premulti_en = premulti_en; 1755 alpha_config.dst_premulti_en = false; 1756 alpha_config.src_pixel_alpha_en = src_pixel_alpha_en; 1757 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ 1758 alpha_config.src_glb_alpha_value = src_glb_alpha_val; 1759 alpha_config.dst_glb_alpha_value = dst_glb_alpha_val; 1760 vop2_parse_alpha(&alpha_config, &alpha); 1761 1762 alpha.src_color_ctrl.bits.src_dst_swap = swap; 1763 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, 1764 alpha.src_color_ctrl.val); 1765 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, 1766 alpha.dst_color_ctrl.val); 1767 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, 1768 alpha.src_alpha_ctrl.val); 1769 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, 1770 alpha.dst_alpha_ctrl.val); 1771 } 1772 1773 static void vop2_setup_alpha(struct vop2_video_port *vp) 1774 { 1775 struct vop2 *vop2 = vp->vop2; 1776 struct drm_framebuffer *fb; 1777 struct vop2_alpha_config alpha_config; 1778 struct vop2_alpha alpha; 1779 struct drm_plane *plane; 1780 int pixel_alpha_en; 1781 int premulti_en, gpremulti_en = 0; 1782 int mixer_id; 1783 u32 offset; 1784 bool bottom_layer_alpha_en = false; 1785 u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; 1786 1787 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); 1788 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ 1789 1790 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1791 struct vop2_win *win = to_vop2_win(plane); 1792 1793 if (plane->state->normalized_zpos == 0 && 1794 !is_opaque(plane->state->alpha) && 1795 !vop2_cluster_window(win)) { 1796 /* 1797 * If bottom layer have global alpha effect [except cluster layer, 1798 * because cluster have deal with bottom layer global alpha value 1799 * at cluster mix], bottom layer mix need deal with global alpha. 1800 */ 1801 bottom_layer_alpha_en = true; 1802 dst_global_alpha = plane->state->alpha; 1803 } 1804 } 1805 1806 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1807 struct vop2_win *win = to_vop2_win(plane); 1808 int zpos = plane->state->normalized_zpos; 1809 1810 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) 1811 premulti_en = 1; 1812 else 1813 premulti_en = 0; 1814 1815 plane = &win->base; 1816 fb = plane->state->fb; 1817 1818 pixel_alpha_en = fb->format->has_alpha; 1819 1820 alpha_config.src_premulti_en = premulti_en; 1821 1822 if (bottom_layer_alpha_en && zpos == 1) { 1823 gpremulti_en = premulti_en; 1824 /* Cd = Cs + (1 - As) * Cd * Agd */ 1825 alpha_config.dst_premulti_en = false; 1826 alpha_config.src_pixel_alpha_en = pixel_alpha_en; 1827 alpha_config.src_glb_alpha_value = plane->state->alpha; 1828 alpha_config.dst_glb_alpha_value = dst_global_alpha; 1829 } else if (vop2_cluster_window(win)) { 1830 /* Mix output data only have pixel alpha */ 1831 alpha_config.dst_premulti_en = true; 1832 alpha_config.src_pixel_alpha_en = true; 1833 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1834 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1835 } else { 1836 /* Cd = Cs + (1 - As) * Cd */ 1837 alpha_config.dst_premulti_en = true; 1838 alpha_config.src_pixel_alpha_en = pixel_alpha_en; 1839 alpha_config.src_glb_alpha_value = plane->state->alpha; 1840 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1841 } 1842 1843 vop2_parse_alpha(&alpha_config, &alpha); 1844 1845 offset = (mixer_id + zpos - 1) * 0x10; 1846 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, 1847 alpha.src_color_ctrl.val); 1848 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, 1849 alpha.dst_color_ctrl.val); 1850 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, 1851 alpha.src_alpha_ctrl.val); 1852 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, 1853 alpha.dst_alpha_ctrl.val); 1854 } 1855 1856 if (vp->id == 0) { 1857 if (bottom_layer_alpha_en) { 1858 /* Transfer pixel alpha to hdr mix */ 1859 alpha_config.src_premulti_en = gpremulti_en; 1860 alpha_config.dst_premulti_en = true; 1861 alpha_config.src_pixel_alpha_en = true; 1862 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1863 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1864 vop2_parse_alpha(&alpha_config, &alpha); 1865 1866 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 1867 alpha.src_color_ctrl.val); 1868 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, 1869 alpha.dst_color_ctrl.val); 1870 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, 1871 alpha.src_alpha_ctrl.val); 1872 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, 1873 alpha.dst_alpha_ctrl.val); 1874 } else { 1875 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); 1876 } 1877 } 1878 } 1879 1880 static void vop2_setup_layer_mixer(struct vop2_video_port *vp) 1881 { 1882 struct vop2 *vop2 = vp->vop2; 1883 struct drm_plane *plane; 1884 u32 layer_sel = 0; 1885 u32 port_sel; 1886 unsigned int nlayer, ofs; 1887 struct drm_display_mode *adjusted_mode; 1888 u16 hsync_len; 1889 u16 hdisplay; 1890 u32 bg_dly; 1891 u32 pre_scan_dly; 1892 int i; 1893 struct vop2_video_port *vp0 = &vop2->vps[0]; 1894 struct vop2_video_port *vp1 = &vop2->vps[1]; 1895 struct vop2_video_port *vp2 = &vop2->vps[2]; 1896 1897 adjusted_mode = &vp->crtc.state->adjusted_mode; 1898 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1899 hdisplay = adjusted_mode->crtc_hdisplay; 1900 1901 bg_dly = vp->data->pre_scan_max_dly[3]; 1902 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), 1903 FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); 1904 1905 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; 1906 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); 1907 1908 vop2_writel(vop2, RK3568_OVL_CTRL, 0); 1909 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); 1910 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; 1911 1912 if (vp0->nlayers) 1913 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 1914 vp0->nlayers - 1); 1915 else 1916 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); 1917 1918 if (vp1->nlayers) 1919 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 1920 (vp0->nlayers + vp1->nlayers - 1)); 1921 else 1922 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); 1923 1924 if (vp2->nlayers) 1925 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 1926 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); 1927 else 1928 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); 1929 1930 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); 1931 1932 ofs = 0; 1933 for (i = 0; i < vp->id; i++) 1934 ofs += vop2->vps[i].nlayers; 1935 1936 nlayer = 0; 1937 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1938 struct vop2_win *win = to_vop2_win(plane); 1939 1940 switch (win->data->phys_id) { 1941 case ROCKCHIP_VOP2_CLUSTER0: 1942 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; 1943 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); 1944 break; 1945 case ROCKCHIP_VOP2_CLUSTER1: 1946 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; 1947 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); 1948 break; 1949 case ROCKCHIP_VOP2_ESMART0: 1950 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; 1951 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); 1952 break; 1953 case ROCKCHIP_VOP2_ESMART1: 1954 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; 1955 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); 1956 break; 1957 case ROCKCHIP_VOP2_SMART0: 1958 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; 1959 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); 1960 break; 1961 case ROCKCHIP_VOP2_SMART1: 1962 port_sel &= ~RK3568_OVL_PORT_SEL__SMART1; 1963 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); 1964 break; 1965 } 1966 1967 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, 1968 0x7); 1969 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, 1970 win->data->layer_sel_id); 1971 nlayer++; 1972 } 1973 1974 /* configure unused layers to 0x5 (reserved) */ 1975 for (; nlayer < vp->nlayers; nlayer++) { 1976 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); 1977 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); 1978 } 1979 1980 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); 1981 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); 1982 vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); 1983 } 1984 1985 static void vop2_setup_dly_for_windows(struct vop2 *vop2) 1986 { 1987 struct vop2_win *win; 1988 int i = 0; 1989 u32 cdly = 0, sdly = 0; 1990 1991 for (i = 0; i < vop2->data->win_size; i++) { 1992 u32 dly; 1993 1994 win = &vop2->win[i]; 1995 dly = win->delay; 1996 1997 switch (win->data->phys_id) { 1998 case ROCKCHIP_VOP2_CLUSTER0: 1999 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); 2000 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); 2001 break; 2002 case ROCKCHIP_VOP2_CLUSTER1: 2003 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); 2004 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); 2005 break; 2006 case ROCKCHIP_VOP2_ESMART0: 2007 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); 2008 break; 2009 case ROCKCHIP_VOP2_ESMART1: 2010 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); 2011 break; 2012 case ROCKCHIP_VOP2_SMART0: 2013 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); 2014 break; 2015 case ROCKCHIP_VOP2_SMART1: 2016 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); 2017 break; 2018 } 2019 } 2020 2021 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); 2022 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); 2023 } 2024 2025 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, 2026 struct drm_atomic_state *state) 2027 { 2028 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2029 struct vop2 *vop2 = vp->vop2; 2030 struct drm_plane *plane; 2031 2032 vp->win_mask = 0; 2033 2034 drm_atomic_crtc_for_each_plane(plane, crtc) { 2035 struct vop2_win *win = to_vop2_win(plane); 2036 2037 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT]; 2038 2039 vp->win_mask |= BIT(win->data->phys_id); 2040 2041 if (vop2_cluster_window(win)) 2042 vop2_setup_cluster_alpha(vop2, win); 2043 } 2044 2045 if (!vp->win_mask) 2046 return; 2047 2048 vop2_setup_layer_mixer(vp); 2049 vop2_setup_alpha(vp); 2050 vop2_setup_dly_for_windows(vop2); 2051 } 2052 2053 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, 2054 struct drm_atomic_state *state) 2055 { 2056 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2057 2058 vop2_post_config(crtc); 2059 2060 vop2_cfg_done(vp); 2061 2062 spin_lock_irq(&crtc->dev->event_lock); 2063 2064 if (crtc->state->event) { 2065 WARN_ON(drm_crtc_vblank_get(crtc)); 2066 vp->event = crtc->state->event; 2067 crtc->state->event = NULL; 2068 } 2069 2070 spin_unlock_irq(&crtc->dev->event_lock); 2071 } 2072 2073 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { 2074 .mode_fixup = vop2_crtc_mode_fixup, 2075 .atomic_check = vop2_crtc_atomic_check, 2076 .atomic_begin = vop2_crtc_atomic_begin, 2077 .atomic_flush = vop2_crtc_atomic_flush, 2078 .atomic_enable = vop2_crtc_atomic_enable, 2079 .atomic_disable = vop2_crtc_atomic_disable, 2080 }; 2081 2082 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) 2083 { 2084 struct rockchip_crtc_state *vcstate; 2085 2086 if (WARN_ON(!crtc->state)) 2087 return NULL; 2088 2089 vcstate = kmemdup(to_rockchip_crtc_state(crtc->state), 2090 sizeof(*vcstate), GFP_KERNEL); 2091 if (!vcstate) 2092 return NULL; 2093 2094 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); 2095 2096 return &vcstate->base; 2097 } 2098 2099 static void vop2_crtc_destroy_state(struct drm_crtc *crtc, 2100 struct drm_crtc_state *state) 2101 { 2102 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); 2103 2104 __drm_atomic_helper_crtc_destroy_state(&vcstate->base); 2105 kfree(vcstate); 2106 } 2107 2108 static void vop2_crtc_reset(struct drm_crtc *crtc) 2109 { 2110 struct rockchip_crtc_state *vcstate = 2111 kzalloc(sizeof(*vcstate), GFP_KERNEL); 2112 2113 if (crtc->state) 2114 vop2_crtc_destroy_state(crtc, crtc->state); 2115 2116 if (vcstate) 2117 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base); 2118 else 2119 __drm_atomic_helper_crtc_reset(crtc, NULL); 2120 } 2121 2122 static const struct drm_crtc_funcs vop2_crtc_funcs = { 2123 .set_config = drm_atomic_helper_set_config, 2124 .page_flip = drm_atomic_helper_page_flip, 2125 .destroy = drm_crtc_cleanup, 2126 .reset = vop2_crtc_reset, 2127 .atomic_duplicate_state = vop2_crtc_duplicate_state, 2128 .atomic_destroy_state = vop2_crtc_destroy_state, 2129 .enable_vblank = vop2_crtc_enable_vblank, 2130 .disable_vblank = vop2_crtc_disable_vblank, 2131 }; 2132 2133 static irqreturn_t vop2_isr(int irq, void *data) 2134 { 2135 struct vop2 *vop2 = data; 2136 const struct vop2_data *vop2_data = vop2->data; 2137 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; 2138 int ret = IRQ_NONE; 2139 int i; 2140 2141 /* 2142 * The irq is shared with the iommu. If the runtime-pm state of the 2143 * vop2-device is disabled the irq has to be targeted at the iommu. 2144 */ 2145 if (!pm_runtime_get_if_in_use(vop2->dev)) 2146 return IRQ_NONE; 2147 2148 for (i = 0; i < vop2_data->nr_vps; i++) { 2149 struct vop2_video_port *vp = &vop2->vps[i]; 2150 struct drm_crtc *crtc = &vp->crtc; 2151 u32 irqs; 2152 2153 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2154 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2155 2156 if (irqs & VP_INT_DSP_HOLD_VALID) { 2157 complete(&vp->dsp_hold_completion); 2158 ret = IRQ_HANDLED; 2159 } 2160 2161 if (irqs & VP_INT_FS_FIELD) { 2162 drm_crtc_handle_vblank(crtc); 2163 spin_lock(&crtc->dev->event_lock); 2164 if (vp->event) { 2165 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2166 2167 if (!(val & BIT(vp->id))) { 2168 drm_crtc_send_vblank_event(crtc, vp->event); 2169 vp->event = NULL; 2170 drm_crtc_vblank_put(crtc); 2171 } 2172 } 2173 spin_unlock(&crtc->dev->event_lock); 2174 2175 ret = IRQ_HANDLED; 2176 } 2177 2178 if (irqs & VP_INT_POST_BUF_EMPTY) { 2179 drm_err_ratelimited(vop2->drm, 2180 "POST_BUF_EMPTY irq err at vp%d\n", 2181 vp->id); 2182 ret = IRQ_HANDLED; 2183 } 2184 } 2185 2186 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); 2187 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); 2188 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); 2189 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); 2190 2191 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { 2192 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { 2193 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); 2194 ret = IRQ_HANDLED; 2195 } 2196 } 2197 2198 pm_runtime_put(vop2->dev); 2199 2200 return ret; 2201 } 2202 2203 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, 2204 unsigned long possible_crtcs) 2205 { 2206 const struct vop2_win_data *win_data = win->data; 2207 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2208 BIT(DRM_MODE_BLEND_PREMULTI) | 2209 BIT(DRM_MODE_BLEND_COVERAGE); 2210 int ret; 2211 2212 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, 2213 &vop2_plane_funcs, win_data->formats, 2214 win_data->nformats, 2215 win_data->format_modifiers, 2216 win->type, win_data->name); 2217 if (ret) { 2218 drm_err(vop2->drm, "failed to initialize plane %d\n", ret); 2219 return ret; 2220 } 2221 2222 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); 2223 2224 if (win->data->supported_rotations) 2225 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, 2226 DRM_MODE_ROTATE_0 | 2227 win->data->supported_rotations); 2228 drm_plane_create_alpha_property(&win->base); 2229 drm_plane_create_blend_mode_property(&win->base, blend_caps); 2230 drm_plane_create_zpos_property(&win->base, win->win_id, 0, 2231 vop2->registered_num_wins - 1); 2232 2233 return 0; 2234 } 2235 2236 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) 2237 { 2238 int i; 2239 2240 for (i = 0; i < vop2->data->nr_vps; i++) { 2241 struct vop2_video_port *vp = &vop2->vps[i]; 2242 2243 if (!vp->crtc.port) 2244 continue; 2245 if (vp->primary_plane) 2246 continue; 2247 2248 return vp; 2249 } 2250 2251 return NULL; 2252 } 2253 2254 #define NR_LAYERS 6 2255 2256 static int vop2_create_crtcs(struct vop2 *vop2) 2257 { 2258 const struct vop2_data *vop2_data = vop2->data; 2259 struct drm_device *drm = vop2->drm; 2260 struct device *dev = vop2->dev; 2261 struct drm_plane *plane; 2262 struct device_node *port; 2263 struct vop2_video_port *vp; 2264 int i, nvp, nvps = 0; 2265 int ret; 2266 2267 for (i = 0; i < vop2_data->nr_vps; i++) { 2268 const struct vop2_video_port_data *vp_data; 2269 struct device_node *np; 2270 char dclk_name[9]; 2271 2272 vp_data = &vop2_data->vp[i]; 2273 vp = &vop2->vps[i]; 2274 vp->vop2 = vop2; 2275 vp->id = vp_data->id; 2276 vp->regs = vp_data->regs; 2277 vp->data = vp_data; 2278 2279 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); 2280 vp->dclk = devm_clk_get(vop2->dev, dclk_name); 2281 if (IS_ERR(vp->dclk)) { 2282 drm_err(vop2->drm, "failed to get %s\n", dclk_name); 2283 return PTR_ERR(vp->dclk); 2284 } 2285 2286 np = of_graph_get_remote_node(dev->of_node, i, -1); 2287 if (!np) { 2288 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); 2289 continue; 2290 } 2291 of_node_put(np); 2292 2293 port = of_graph_get_port_by_id(dev->of_node, i); 2294 if (!port) { 2295 drm_err(vop2->drm, "no port node found for video_port%d\n", i); 2296 return -ENOENT; 2297 } 2298 2299 vp->crtc.port = port; 2300 nvps++; 2301 } 2302 2303 nvp = 0; 2304 for (i = 0; i < vop2->registered_num_wins; i++) { 2305 struct vop2_win *win = &vop2->win[i]; 2306 u32 possible_crtcs = 0; 2307 2308 if (vop2->data->soc_id == 3566) { 2309 /* 2310 * On RK3566 these windows don't have an independent 2311 * framebuffer. They share the framebuffer with smart0, 2312 * esmart0 and cluster0 respectively. 2313 */ 2314 switch (win->data->phys_id) { 2315 case ROCKCHIP_VOP2_SMART1: 2316 case ROCKCHIP_VOP2_ESMART1: 2317 case ROCKCHIP_VOP2_CLUSTER1: 2318 continue; 2319 } 2320 } 2321 2322 if (win->type == DRM_PLANE_TYPE_PRIMARY) { 2323 vp = find_vp_without_primary(vop2); 2324 if (vp) { 2325 possible_crtcs = BIT(nvp); 2326 vp->primary_plane = win; 2327 nvp++; 2328 } else { 2329 /* change the unused primary window to overlay window */ 2330 win->type = DRM_PLANE_TYPE_OVERLAY; 2331 } 2332 } 2333 2334 if (win->type == DRM_PLANE_TYPE_OVERLAY) 2335 possible_crtcs = (1 << nvps) - 1; 2336 2337 ret = vop2_plane_init(vop2, win, possible_crtcs); 2338 if (ret) { 2339 drm_err(vop2->drm, "failed to init plane %s: %d\n", 2340 win->data->name, ret); 2341 return ret; 2342 } 2343 } 2344 2345 for (i = 0; i < vop2_data->nr_vps; i++) { 2346 vp = &vop2->vps[i]; 2347 2348 if (!vp->crtc.port) 2349 continue; 2350 2351 plane = &vp->primary_plane->base; 2352 2353 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, 2354 &vop2_crtc_funcs, 2355 "video_port%d", vp->id); 2356 if (ret) { 2357 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); 2358 return ret; 2359 } 2360 2361 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); 2362 2363 init_completion(&vp->dsp_hold_completion); 2364 } 2365 2366 /* 2367 * On the VOP2 it's very hard to change the number of layers on a VP 2368 * during runtime, so we distribute the layers equally over the used 2369 * VPs 2370 */ 2371 for (i = 0; i < vop2->data->nr_vps; i++) { 2372 struct vop2_video_port *vp = &vop2->vps[i]; 2373 2374 if (vp->crtc.port) 2375 vp->nlayers = NR_LAYERS / nvps; 2376 } 2377 2378 return 0; 2379 } 2380 2381 static void vop2_destroy_crtcs(struct vop2 *vop2) 2382 { 2383 struct drm_device *drm = vop2->drm; 2384 struct list_head *crtc_list = &drm->mode_config.crtc_list; 2385 struct list_head *plane_list = &drm->mode_config.plane_list; 2386 struct drm_crtc *crtc, *tmpc; 2387 struct drm_plane *plane, *tmpp; 2388 2389 list_for_each_entry_safe(plane, tmpp, plane_list, head) 2390 drm_plane_cleanup(plane); 2391 2392 /* 2393 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() 2394 * references the CRTC. 2395 */ 2396 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) { 2397 of_node_put(crtc->port); 2398 drm_crtc_cleanup(crtc); 2399 } 2400 } 2401 2402 static int vop2_find_rgb_encoder(struct vop2 *vop2) 2403 { 2404 struct device_node *node = vop2->dev->of_node; 2405 struct device_node *endpoint; 2406 int i; 2407 2408 for (i = 0; i < vop2->data->nr_vps; i++) { 2409 endpoint = of_graph_get_endpoint_by_regs(node, i, 2410 ROCKCHIP_VOP2_EP_RGB0); 2411 if (!endpoint) 2412 continue; 2413 2414 of_node_put(endpoint); 2415 return i; 2416 } 2417 2418 return -ENOENT; 2419 } 2420 2421 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { 2422 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), 2423 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), 2424 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), 2425 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), 2426 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), 2427 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), 2428 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), 2429 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), 2430 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), 2431 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), 2432 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), 2433 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), 2434 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), 2435 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), 2436 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), 2437 2438 /* Scale */ 2439 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), 2440 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), 2441 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), 2442 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), 2443 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), 2444 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), 2445 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), 2446 2447 /* cluster regs */ 2448 [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), 2449 [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), 2450 [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), 2451 2452 /* afbc regs */ 2453 [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), 2454 [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), 2455 [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), 2456 [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), 2457 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), 2458 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), 2459 [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), 2460 [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), 2461 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), 2462 [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), 2463 [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), 2464 [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), 2465 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), 2466 [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), 2467 [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), 2468 [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), 2469 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), 2470 [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, 2471 [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, 2472 [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, 2473 [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, 2474 [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, 2475 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2476 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2477 [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, 2478 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2479 [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, 2480 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2481 [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, 2482 [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, 2483 }; 2484 2485 static int vop2_cluster_init(struct vop2_win *win) 2486 { 2487 struct vop2 *vop2 = win->vop2; 2488 struct reg_field *cluster_regs; 2489 int ret, i; 2490 2491 cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), 2492 GFP_KERNEL); 2493 if (!cluster_regs) 2494 return -ENOMEM; 2495 2496 for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) 2497 if (cluster_regs[i].reg != 0xffffffff) 2498 cluster_regs[i].reg += win->offset; 2499 2500 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, 2501 cluster_regs, 2502 ARRAY_SIZE(vop2_cluster_regs)); 2503 2504 kfree(cluster_regs); 2505 2506 return ret; 2507 }; 2508 2509 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { 2510 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), 2511 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), 2512 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), 2513 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), 2514 [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), 2515 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), 2516 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), 2517 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), 2518 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), 2519 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), 2520 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), 2521 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), 2522 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), 2523 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), 2524 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), 2525 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), 2526 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), 2527 [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), 2528 [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), 2529 2530 /* Scale */ 2531 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), 2532 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), 2533 [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), 2534 [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), 2535 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), 2536 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), 2537 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), 2538 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), 2539 [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), 2540 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), 2541 [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), 2542 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), 2543 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), 2544 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), 2545 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), 2546 [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), 2547 [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), 2548 [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, 2549 [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, 2550 [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, 2551 [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, 2552 [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, 2553 [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, 2554 [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, 2555 [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, 2556 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, 2557 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, 2558 [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, 2559 [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, 2560 [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, 2561 [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, 2562 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, 2563 [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, 2564 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, 2565 [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, 2566 [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, 2567 }; 2568 2569 static int vop2_esmart_init(struct vop2_win *win) 2570 { 2571 struct vop2 *vop2 = win->vop2; 2572 struct reg_field *esmart_regs; 2573 int ret, i; 2574 2575 esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), 2576 GFP_KERNEL); 2577 if (!esmart_regs) 2578 return -ENOMEM; 2579 2580 for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) 2581 if (esmart_regs[i].reg != 0xffffffff) 2582 esmart_regs[i].reg += win->offset; 2583 2584 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, 2585 esmart_regs, 2586 ARRAY_SIZE(vop2_esmart_regs)); 2587 2588 kfree(esmart_regs); 2589 2590 return ret; 2591 }; 2592 2593 static int vop2_win_init(struct vop2 *vop2) 2594 { 2595 const struct vop2_data *vop2_data = vop2->data; 2596 struct vop2_win *win; 2597 int i, ret; 2598 2599 for (i = 0; i < vop2_data->win_size; i++) { 2600 const struct vop2_win_data *win_data = &vop2_data->win[i]; 2601 2602 win = &vop2->win[i]; 2603 win->data = win_data; 2604 win->type = win_data->type; 2605 win->offset = win_data->base; 2606 win->win_id = i; 2607 win->vop2 = vop2; 2608 if (vop2_cluster_window(win)) 2609 ret = vop2_cluster_init(win); 2610 else 2611 ret = vop2_esmart_init(win); 2612 if (ret) 2613 return ret; 2614 } 2615 2616 vop2->registered_num_wins = vop2_data->win_size; 2617 2618 return 0; 2619 } 2620 2621 /* 2622 * The window registers are only updated when config done is written. 2623 * Until that they read back the old value. As we read-modify-write 2624 * these registers mark them as non-volatile. This makes sure we read 2625 * the new values from the regmap register cache. 2626 */ 2627 static const struct regmap_range vop2_nonvolatile_range[] = { 2628 regmap_reg_range(0x1000, 0x23ff), 2629 }; 2630 2631 static const struct regmap_access_table vop2_volatile_table = { 2632 .no_ranges = vop2_nonvolatile_range, 2633 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), 2634 }; 2635 2636 static const struct regmap_config vop2_regmap_config = { 2637 .reg_bits = 32, 2638 .val_bits = 32, 2639 .reg_stride = 4, 2640 .max_register = 0x3000, 2641 .name = "vop2", 2642 .volatile_table = &vop2_volatile_table, 2643 .cache_type = REGCACHE_MAPLE, 2644 }; 2645 2646 static int vop2_bind(struct device *dev, struct device *master, void *data) 2647 { 2648 struct platform_device *pdev = to_platform_device(dev); 2649 const struct vop2_data *vop2_data; 2650 struct drm_device *drm = data; 2651 struct vop2 *vop2; 2652 struct resource *res; 2653 size_t alloc_size; 2654 int ret; 2655 2656 vop2_data = of_device_get_match_data(dev); 2657 if (!vop2_data) 2658 return -ENODEV; 2659 2660 /* Allocate vop2 struct and its vop2_win array */ 2661 alloc_size = struct_size(vop2, win, vop2_data->win_size); 2662 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 2663 if (!vop2) 2664 return -ENOMEM; 2665 2666 vop2->dev = dev; 2667 vop2->data = vop2_data; 2668 vop2->drm = drm; 2669 2670 dev_set_drvdata(dev, vop2); 2671 2672 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop"); 2673 if (!res) { 2674 drm_err(vop2->drm, "failed to get vop2 register byname\n"); 2675 return -EINVAL; 2676 } 2677 2678 vop2->regs = devm_ioremap_resource(dev, res); 2679 if (IS_ERR(vop2->regs)) 2680 return PTR_ERR(vop2->regs); 2681 vop2->len = resource_size(res); 2682 2683 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); 2684 if (IS_ERR(vop2->map)) 2685 return PTR_ERR(vop2->map); 2686 2687 ret = vop2_win_init(vop2); 2688 if (ret) 2689 return ret; 2690 2691 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut"); 2692 if (res) { 2693 vop2->lut_regs = devm_ioremap_resource(dev, res); 2694 if (IS_ERR(vop2->lut_regs)) 2695 return PTR_ERR(vop2->lut_regs); 2696 } 2697 2698 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 2699 2700 vop2->hclk = devm_clk_get(vop2->dev, "hclk"); 2701 if (IS_ERR(vop2->hclk)) { 2702 drm_err(vop2->drm, "failed to get hclk source\n"); 2703 return PTR_ERR(vop2->hclk); 2704 } 2705 2706 vop2->aclk = devm_clk_get(vop2->dev, "aclk"); 2707 if (IS_ERR(vop2->aclk)) { 2708 drm_err(vop2->drm, "failed to get aclk source\n"); 2709 return PTR_ERR(vop2->aclk); 2710 } 2711 2712 vop2->irq = platform_get_irq(pdev, 0); 2713 if (vop2->irq < 0) { 2714 drm_err(vop2->drm, "cannot find irq for vop2\n"); 2715 return vop2->irq; 2716 } 2717 2718 mutex_init(&vop2->vop2_lock); 2719 2720 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); 2721 if (ret) 2722 return ret; 2723 2724 ret = vop2_create_crtcs(vop2); 2725 if (ret) 2726 return ret; 2727 2728 ret = vop2_find_rgb_encoder(vop2); 2729 if (ret >= 0) { 2730 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, 2731 vop2->drm, ret); 2732 if (IS_ERR(vop2->rgb)) { 2733 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { 2734 ret = PTR_ERR(vop2->rgb); 2735 goto err_crtcs; 2736 } 2737 vop2->rgb = NULL; 2738 } 2739 } 2740 2741 rockchip_drm_dma_init_device(vop2->drm, vop2->dev); 2742 2743 pm_runtime_enable(&pdev->dev); 2744 2745 return 0; 2746 2747 err_crtcs: 2748 vop2_destroy_crtcs(vop2); 2749 2750 return ret; 2751 } 2752 2753 static void vop2_unbind(struct device *dev, struct device *master, void *data) 2754 { 2755 struct vop2 *vop2 = dev_get_drvdata(dev); 2756 2757 pm_runtime_disable(dev); 2758 2759 if (vop2->rgb) 2760 rockchip_rgb_fini(vop2->rgb); 2761 2762 vop2_destroy_crtcs(vop2); 2763 } 2764 2765 const struct component_ops vop2_component_ops = { 2766 .bind = vop2_bind, 2767 .unbind = vop2_unbind, 2768 }; 2769 EXPORT_SYMBOL_GPL(vop2_component_ops); 2770