1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/swab.h> 21 22 #include <drm/drm.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_uapi.h> 25 #include <drm/drm_blend.h> 26 #include <drm/drm_crtc.h> 27 #include <linux/debugfs.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_flip_work.h> 30 #include <drm/drm_framebuffer.h> 31 #include <drm/drm_gem_framebuffer_helper.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <uapi/linux/videodev2.h> 36 37 #include "rockchip_drm_gem.h" 38 #include "rockchip_drm_vop2.h" 39 #include "rockchip_rgb.h" 40 41 /* 42 * VOP2 architecture 43 * 44 +----------+ +-------------+ +-----------+ 45 | Cluster | | Sel 1 from 6| | 1 from 3 | 46 | window0 | | Layer0 | | RGB | 47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+ 48 +----------+ +-------------+ |N from 6 layers| | | 49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ 50 | window1 | | Layer1 | | | | | | 1 from 3 | 51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS | 52 +----------+ +-------------+ +-----------+ 53 | Esmart | | Sel 1 from 6| 54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ 55 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | 56 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | 57 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ 58 | Window1 | | Layer3 | +---------------+ +-------------+ 59 +----------+ +-------------+ +-----------+ 60 +----------+ +-------------+ | 1 from 3 | 61 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | 62 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ 63 +----------+ +-------------+ | Overlay2 +--->| Video Port2 | 64 +----------+ +-------------+ | | | | +-----------+ 65 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | 66 | Window1 | | Layer5 | | eDP | 67 +----------+ +-------------+ +-----------+ 68 * 69 */ 70 71 enum vop2_data_format { 72 VOP2_FMT_ARGB8888 = 0, 73 VOP2_FMT_RGB888, 74 VOP2_FMT_RGB565, 75 VOP2_FMT_XRGB101010, 76 VOP2_FMT_YUV420SP, 77 VOP2_FMT_YUV422SP, 78 VOP2_FMT_YUV444SP, 79 VOP2_FMT_YUYV422 = 8, 80 VOP2_FMT_YUYV420, 81 VOP2_FMT_VYUY422, 82 VOP2_FMT_VYUY420, 83 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, 84 VOP2_FMT_YUV420SP_TILE_16x2, 85 VOP2_FMT_YUV422SP_TILE_8x4, 86 VOP2_FMT_YUV422SP_TILE_16x2, 87 VOP2_FMT_YUV420SP_10, 88 VOP2_FMT_YUV422SP_10, 89 VOP2_FMT_YUV444SP_10, 90 }; 91 92 enum vop2_afbc_format { 93 VOP2_AFBC_FMT_RGB565, 94 VOP2_AFBC_FMT_ARGB2101010 = 2, 95 VOP2_AFBC_FMT_YUV420_10BIT, 96 VOP2_AFBC_FMT_RGB888, 97 VOP2_AFBC_FMT_ARGB8888, 98 VOP2_AFBC_FMT_YUV420 = 9, 99 VOP2_AFBC_FMT_YUV422 = 0xb, 100 VOP2_AFBC_FMT_YUV422_10BIT = 0xe, 101 VOP2_AFBC_FMT_INVALID = -1, 102 }; 103 104 #define VOP2_MAX_DCLK_RATE 600000000 105 106 /* 107 * bus-format types. 108 */ 109 struct drm_bus_format_enum_list { 110 int type; 111 const char *name; 112 }; 113 114 static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = { 115 { DRM_MODE_CONNECTOR_Unknown, "Unknown" }, 116 { MEDIA_BUS_FMT_RGB565_1X16, "RGB565_1X16" }, 117 { MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" }, 118 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" }, 119 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" }, 120 { MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" }, 121 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" }, 122 { MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" }, 123 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" }, 124 { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" }, 125 { MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" }, 126 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" }, 127 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" }, 128 { MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" }, 129 { MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" }, 130 { MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" }, 131 { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" }, 132 { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" }, 133 }; 134 135 static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list) 136 137 static const struct regmap_config vop2_regmap_config; 138 139 static void vop2_lock(struct vop2 *vop2) 140 { 141 mutex_lock(&vop2->vop2_lock); 142 } 143 144 static void vop2_unlock(struct vop2 *vop2) 145 { 146 mutex_unlock(&vop2->vop2_lock); 147 } 148 149 static void vop2_win_disable(struct vop2_win *win) 150 { 151 vop2_win_write(win, VOP2_WIN_ENABLE, 0); 152 153 if (vop2_cluster_window(win)) 154 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); 155 } 156 157 static u32 vop2_get_bpp(const struct drm_format_info *format) 158 { 159 switch (format->format) { 160 case DRM_FORMAT_YUV420_8BIT: 161 return 12; 162 case DRM_FORMAT_YUV420_10BIT: 163 return 15; 164 case DRM_FORMAT_VUY101010: 165 return 30; 166 default: 167 return drm_format_info_bpp(format, 0); 168 } 169 } 170 171 static enum vop2_data_format vop2_convert_format(u32 format) 172 { 173 switch (format) { 174 case DRM_FORMAT_XRGB2101010: 175 case DRM_FORMAT_ARGB2101010: 176 case DRM_FORMAT_XBGR2101010: 177 case DRM_FORMAT_ABGR2101010: 178 return VOP2_FMT_XRGB101010; 179 case DRM_FORMAT_XRGB8888: 180 case DRM_FORMAT_ARGB8888: 181 case DRM_FORMAT_XBGR8888: 182 case DRM_FORMAT_ABGR8888: 183 return VOP2_FMT_ARGB8888; 184 case DRM_FORMAT_RGB888: 185 case DRM_FORMAT_BGR888: 186 return VOP2_FMT_RGB888; 187 case DRM_FORMAT_RGB565: 188 case DRM_FORMAT_BGR565: 189 return VOP2_FMT_RGB565; 190 case DRM_FORMAT_NV12: 191 case DRM_FORMAT_NV21: 192 case DRM_FORMAT_YUV420_8BIT: 193 return VOP2_FMT_YUV420SP; 194 case DRM_FORMAT_NV15: 195 case DRM_FORMAT_YUV420_10BIT: 196 return VOP2_FMT_YUV420SP_10; 197 case DRM_FORMAT_NV16: 198 case DRM_FORMAT_NV61: 199 return VOP2_FMT_YUV422SP; 200 case DRM_FORMAT_NV20: 201 case DRM_FORMAT_Y210: 202 return VOP2_FMT_YUV422SP_10; 203 case DRM_FORMAT_NV24: 204 case DRM_FORMAT_NV42: 205 return VOP2_FMT_YUV444SP; 206 case DRM_FORMAT_NV30: 207 return VOP2_FMT_YUV444SP_10; 208 case DRM_FORMAT_YUYV: 209 case DRM_FORMAT_YVYU: 210 return VOP2_FMT_VYUY422; 211 case DRM_FORMAT_VYUY: 212 case DRM_FORMAT_UYVY: 213 return VOP2_FMT_YUYV422; 214 default: 215 DRM_ERROR("unsupported format[%08x]\n", format); 216 return -EINVAL; 217 } 218 } 219 220 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) 221 { 222 switch (format) { 223 case DRM_FORMAT_XRGB2101010: 224 case DRM_FORMAT_ARGB2101010: 225 case DRM_FORMAT_XBGR2101010: 226 case DRM_FORMAT_ABGR2101010: 227 return VOP2_AFBC_FMT_ARGB2101010; 228 case DRM_FORMAT_XRGB8888: 229 case DRM_FORMAT_ARGB8888: 230 case DRM_FORMAT_XBGR8888: 231 case DRM_FORMAT_ABGR8888: 232 return VOP2_AFBC_FMT_ARGB8888; 233 case DRM_FORMAT_RGB888: 234 case DRM_FORMAT_BGR888: 235 return VOP2_AFBC_FMT_RGB888; 236 case DRM_FORMAT_RGB565: 237 case DRM_FORMAT_BGR565: 238 return VOP2_AFBC_FMT_RGB565; 239 case DRM_FORMAT_YUV420_8BIT: 240 return VOP2_AFBC_FMT_YUV420; 241 case DRM_FORMAT_YUV420_10BIT: 242 return VOP2_AFBC_FMT_YUV420_10BIT; 243 case DRM_FORMAT_YVYU: 244 case DRM_FORMAT_YUYV: 245 case DRM_FORMAT_VYUY: 246 case DRM_FORMAT_UYVY: 247 return VOP2_AFBC_FMT_YUV422; 248 case DRM_FORMAT_Y210: 249 return VOP2_AFBC_FMT_YUV422_10BIT; 250 default: 251 return VOP2_AFBC_FMT_INVALID; 252 } 253 254 return VOP2_AFBC_FMT_INVALID; 255 } 256 257 static bool vop2_win_rb_swap(u32 format) 258 { 259 switch (format) { 260 case DRM_FORMAT_XBGR2101010: 261 case DRM_FORMAT_ABGR2101010: 262 case DRM_FORMAT_XBGR8888: 263 case DRM_FORMAT_ABGR8888: 264 case DRM_FORMAT_BGR888: 265 case DRM_FORMAT_BGR565: 266 return true; 267 default: 268 return false; 269 } 270 } 271 272 static bool vop2_afbc_uv_swap(u32 format) 273 { 274 switch (format) { 275 case DRM_FORMAT_YUYV: 276 case DRM_FORMAT_Y210: 277 case DRM_FORMAT_YUV420_8BIT: 278 case DRM_FORMAT_YUV420_10BIT: 279 return true; 280 default: 281 return false; 282 } 283 } 284 285 static bool vop2_win_uv_swap(u32 format) 286 { 287 switch (format) { 288 case DRM_FORMAT_NV12: 289 case DRM_FORMAT_NV16: 290 case DRM_FORMAT_NV24: 291 case DRM_FORMAT_NV15: 292 case DRM_FORMAT_NV20: 293 case DRM_FORMAT_NV30: 294 case DRM_FORMAT_YUYV: 295 case DRM_FORMAT_UYVY: 296 return true; 297 default: 298 return false; 299 } 300 } 301 302 static bool vop2_win_dither_up(u32 format) 303 { 304 switch (format) { 305 case DRM_FORMAT_BGR565: 306 case DRM_FORMAT_RGB565: 307 return true; 308 default: 309 return false; 310 } 311 } 312 313 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) 314 { 315 /* 316 * FIXME: 317 * 318 * There is no media type for YUV444 output, 319 * so when out_mode is AAAA or P888, assume output is YUV444 on 320 * yuv format. 321 * 322 * From H/W testing, YUV444 mode need a rb swap. 323 */ 324 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 325 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 326 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 327 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 328 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 329 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 330 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 331 output_mode == ROCKCHIP_OUT_MODE_P888))) 332 return true; 333 else 334 return false; 335 } 336 337 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format) 338 { 339 if (vop2->version == VOP_VERSION_RK3588) { 340 if (bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 341 bus_format == MEDIA_BUS_FMT_YUV10_1X30) 342 return true; 343 } 344 345 return false; 346 } 347 348 static bool is_yuv_output(u32 bus_format) 349 { 350 switch (bus_format) { 351 case MEDIA_BUS_FMT_YUV8_1X24: 352 case MEDIA_BUS_FMT_YUV10_1X30: 353 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 354 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 355 case MEDIA_BUS_FMT_YUYV8_2X8: 356 case MEDIA_BUS_FMT_YVYU8_2X8: 357 case MEDIA_BUS_FMT_UYVY8_2X8: 358 case MEDIA_BUS_FMT_VYUY8_2X8: 359 case MEDIA_BUS_FMT_YUYV8_1X16: 360 case MEDIA_BUS_FMT_YVYU8_1X16: 361 case MEDIA_BUS_FMT_UYVY8_1X16: 362 case MEDIA_BUS_FMT_VYUY8_1X16: 363 return true; 364 default: 365 return false; 366 } 367 } 368 369 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) 370 { 371 int i; 372 373 if (modifier == DRM_FORMAT_MOD_LINEAR) 374 return false; 375 376 for (i = 0 ; i < plane->modifier_count; i++) 377 if (plane->modifiers[i] == modifier) 378 return true; 379 380 return false; 381 } 382 383 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, 384 u64 modifier) 385 { 386 struct vop2_win *win = to_vop2_win(plane); 387 struct vop2 *vop2 = win->vop2; 388 389 if (modifier == DRM_FORMAT_MOD_INVALID) 390 return false; 391 392 if (vop2->version == VOP_VERSION_RK3568) { 393 if (vop2_cluster_window(win)) { 394 if (modifier == DRM_FORMAT_MOD_LINEAR) { 395 drm_dbg_kms(vop2->drm, 396 "Cluster window only supports format with afbc\n"); 397 return false; 398 } 399 } 400 } 401 402 if (format == DRM_FORMAT_XRGB2101010 || format == DRM_FORMAT_XBGR2101010) { 403 if (vop2->version == VOP_VERSION_RK3588) { 404 if (!rockchip_afbc(plane, modifier)) { 405 drm_dbg_kms(vop2->drm, "Only support 32 bpp format with afbc\n"); 406 return false; 407 } 408 } 409 } 410 411 if (modifier == DRM_FORMAT_MOD_LINEAR) 412 return true; 413 414 if (!rockchip_afbc(plane, modifier)) { 415 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n", 416 modifier); 417 418 return false; 419 } 420 421 return vop2_convert_afbc_format(format) >= 0; 422 } 423 424 /* 425 * 0: Full mode, 16 lines for one tail 426 * 1: half block mode, 8 lines one tail 427 */ 428 static bool vop2_half_block_enable(struct drm_plane_state *pstate) 429 { 430 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) 431 return false; 432 else 433 return true; 434 } 435 436 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, 437 bool afbc_half_block_en) 438 { 439 struct drm_rect *src = &pstate->src; 440 struct drm_framebuffer *fb = pstate->fb; 441 u32 bpp = vop2_get_bpp(fb->format); 442 u32 vir_width = (fb->pitches[0] << 3) / bpp; 443 u32 width = drm_rect_width(src) >> 16; 444 u32 height = drm_rect_height(src) >> 16; 445 u32 act_xoffset = src->x1 >> 16; 446 u32 act_yoffset = src->y1 >> 16; 447 u32 align16_crop = 0; 448 u32 align64_crop = 0; 449 u32 height_tmp; 450 u8 tx, ty; 451 u8 bottom_crop_line_num = 0; 452 453 /* 16 pixel align */ 454 if (height & 0xf) 455 align16_crop = 16 - (height & 0xf); 456 457 height_tmp = height + align16_crop; 458 459 /* 64 pixel align */ 460 if (height_tmp & 0x3f) 461 align64_crop = 64 - (height_tmp & 0x3f); 462 463 bottom_crop_line_num = align16_crop + align64_crop; 464 465 switch (pstate->rotation & 466 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | 467 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { 468 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: 469 tx = 16 - ((act_xoffset + width) & 0xf); 470 ty = bottom_crop_line_num - act_yoffset; 471 break; 472 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: 473 tx = bottom_crop_line_num - act_yoffset; 474 ty = vir_width - width - act_xoffset; 475 break; 476 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: 477 tx = act_yoffset; 478 ty = act_xoffset; 479 break; 480 case DRM_MODE_REFLECT_X: 481 tx = 16 - ((act_xoffset + width) & 0xf); 482 ty = act_yoffset; 483 break; 484 case DRM_MODE_REFLECT_Y: 485 tx = act_xoffset; 486 ty = bottom_crop_line_num - act_yoffset; 487 break; 488 case DRM_MODE_ROTATE_90: 489 tx = bottom_crop_line_num - act_yoffset; 490 ty = act_xoffset; 491 break; 492 case DRM_MODE_ROTATE_270: 493 tx = act_yoffset; 494 ty = vir_width - width - act_xoffset; 495 break; 496 case 0: 497 tx = act_xoffset; 498 ty = act_yoffset; 499 break; 500 } 501 502 if (afbc_half_block_en) 503 ty &= 0x7f; 504 505 #define TRANSFORM_XOFFSET GENMASK(7, 0) 506 #define TRANSFORM_YOFFSET GENMASK(23, 16) 507 return FIELD_PREP(TRANSFORM_XOFFSET, tx) | 508 FIELD_PREP(TRANSFORM_YOFFSET, ty); 509 } 510 511 /* 512 * A Cluster window has 2048 x 16 line buffer, which can 513 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. 514 * for Cluster_lb_mode register: 515 * 0: half mode, for plane input width range 2048 ~ 4096 516 * 1: half mode, for cluster work at 2 * 2048 plane mode 517 * 2: half mode, for rotate_90/270 mode 518 * 519 */ 520 static int vop2_get_cluster_lb_mode(struct vop2_win *win, 521 struct drm_plane_state *pstate) 522 { 523 if ((pstate->rotation & DRM_MODE_ROTATE_270) || 524 (pstate->rotation & DRM_MODE_ROTATE_90)) 525 return 2; 526 else 527 return 0; 528 } 529 530 static u16 vop2_scale_factor(u32 src, u32 dst) 531 { 532 u32 fac; 533 int shift; 534 535 if (src == dst) 536 return 0; 537 538 if (dst < 2) 539 return U16_MAX; 540 541 if (src < 2) 542 return 0; 543 544 if (src > dst) 545 shift = 12; 546 else 547 shift = 16; 548 549 src--; 550 dst--; 551 552 fac = DIV_ROUND_UP(src << shift, dst) - 1; 553 554 if (fac > U16_MAX) 555 return U16_MAX; 556 557 return fac; 558 } 559 560 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, 561 u32 src_w, u32 src_h, u32 dst_w, 562 u32 dst_h, u32 pixel_format) 563 { 564 const struct drm_format_info *info; 565 u16 hor_scl_mode, ver_scl_mode; 566 u16 hscl_filter_mode, vscl_filter_mode; 567 uint16_t cbcr_src_w = src_w; 568 uint16_t cbcr_src_h = src_h; 569 u8 gt2 = 0; 570 u8 gt4 = 0; 571 u32 val; 572 573 info = drm_format_info(pixel_format); 574 575 if (src_h >= (4 * dst_h)) { 576 gt4 = 1; 577 src_h >>= 2; 578 } else if (src_h >= (2 * dst_h)) { 579 gt2 = 1; 580 src_h >>= 1; 581 } 582 583 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 584 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 585 586 if (hor_scl_mode == SCALE_UP) 587 hscl_filter_mode = VOP2_SCALE_UP_BIC; 588 else 589 hscl_filter_mode = VOP2_SCALE_DOWN_BIL; 590 591 if (ver_scl_mode == SCALE_UP) 592 vscl_filter_mode = VOP2_SCALE_UP_BIL; 593 else 594 vscl_filter_mode = VOP2_SCALE_DOWN_BIL; 595 596 /* 597 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 598 * at scale down mode 599 */ 600 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 601 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 602 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", 603 win->data->name, dst_w); 604 dst_w++; 605 } 606 } 607 608 val = vop2_scale_factor(src_w, dst_w); 609 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); 610 val = vop2_scale_factor(src_h, dst_h); 611 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); 612 613 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); 614 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); 615 616 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); 617 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); 618 619 if (vop2_cluster_window(win)) 620 return; 621 622 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); 623 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); 624 625 if (info->is_yuv) { 626 cbcr_src_w /= info->hsub; 627 cbcr_src_h /= info->vsub; 628 629 gt4 = 0; 630 gt2 = 0; 631 632 if (cbcr_src_h >= (4 * dst_h)) { 633 gt4 = 1; 634 cbcr_src_h >>= 2; 635 } else if (cbcr_src_h >= (2 * dst_h)) { 636 gt2 = 1; 637 cbcr_src_h >>= 1; 638 } 639 640 hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 641 ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 642 643 val = vop2_scale_factor(cbcr_src_w, dst_w); 644 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); 645 646 val = vop2_scale_factor(cbcr_src_h, dst_h); 647 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); 648 649 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); 650 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); 651 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); 652 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); 653 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); 654 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); 655 } 656 } 657 658 static int vop2_convert_csc_mode(int csc_mode) 659 { 660 switch (csc_mode) { 661 case V4L2_COLORSPACE_SMPTE170M: 662 case V4L2_COLORSPACE_470_SYSTEM_M: 663 case V4L2_COLORSPACE_470_SYSTEM_BG: 664 return CSC_BT601L; 665 case V4L2_COLORSPACE_REC709: 666 case V4L2_COLORSPACE_SMPTE240M: 667 case V4L2_COLORSPACE_DEFAULT: 668 return CSC_BT709L; 669 case V4L2_COLORSPACE_JPEG: 670 return CSC_BT601F; 671 case V4L2_COLORSPACE_BT2020: 672 return CSC_BT2020; 673 default: 674 return CSC_BT709L; 675 } 676 } 677 678 /* 679 * colorspace path: 680 * Input Win csc Output 681 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) 682 * RGB --> R2Y __/ 683 * 684 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) 685 * RGB --> 709To2020->R2Y __/ 686 * 687 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) 688 * RGB --> R2Y __/ 689 * 690 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) 691 * RGB --> 709To2020->R2Y __/ 692 * 693 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) 694 * RGB --> R2Y __/ 695 * 696 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) 697 * RGB --> R2Y(601) __/ 698 * 699 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) 700 * RGB --> bypass __/ 701 * 702 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) 703 * 704 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) 705 * 706 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) 707 * 708 * 11. RGB --> bypass --> RGB_OUTPUT(709) 709 */ 710 711 static void vop2_setup_csc_mode(struct vop2_video_port *vp, 712 struct vop2_win *win, 713 struct drm_plane_state *pstate) 714 { 715 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); 716 int is_input_yuv = pstate->fb->format->is_yuv; 717 int is_output_yuv = is_yuv_output(vcstate->bus_format); 718 int input_csc = V4L2_COLORSPACE_DEFAULT; 719 int output_csc = vcstate->color_space; 720 bool r2y_en, y2r_en; 721 int csc_mode; 722 723 if (is_input_yuv && !is_output_yuv) { 724 y2r_en = true; 725 r2y_en = false; 726 csc_mode = vop2_convert_csc_mode(input_csc); 727 } else if (!is_input_yuv && is_output_yuv) { 728 y2r_en = false; 729 r2y_en = true; 730 csc_mode = vop2_convert_csc_mode(output_csc); 731 } else { 732 y2r_en = false; 733 r2y_en = false; 734 csc_mode = false; 735 } 736 737 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); 738 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); 739 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); 740 } 741 742 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) 743 { 744 struct vop2 *vop2 = vp->vop2; 745 746 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); 747 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); 748 } 749 750 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) 751 { 752 struct vop2 *vop2 = vp->vop2; 753 754 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); 755 } 756 757 static int vop2_core_clks_prepare_enable(struct vop2 *vop2) 758 { 759 int ret; 760 761 ret = clk_prepare_enable(vop2->hclk); 762 if (ret < 0) { 763 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); 764 return ret; 765 } 766 767 ret = clk_prepare_enable(vop2->aclk); 768 if (ret < 0) { 769 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); 770 goto err; 771 } 772 773 ret = clk_prepare_enable(vop2->pclk); 774 if (ret < 0) { 775 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret); 776 goto err1; 777 } 778 779 return 0; 780 err1: 781 clk_disable_unprepare(vop2->aclk); 782 err: 783 clk_disable_unprepare(vop2->hclk); 784 785 return ret; 786 } 787 788 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) 789 { 790 u32 pd; 791 792 pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL); 793 pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 | 794 VOP2_PD_CLUSTER3 | VOP2_PD_ESMART); 795 796 vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); 797 } 798 799 static void vop2_enable(struct vop2 *vop2) 800 { 801 int ret; 802 u32 version; 803 804 ret = pm_runtime_resume_and_get(vop2->dev); 805 if (ret < 0) { 806 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); 807 return; 808 } 809 810 ret = vop2_core_clks_prepare_enable(vop2); 811 if (ret) { 812 pm_runtime_put_sync(vop2->dev); 813 return; 814 } 815 816 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); 817 if (ret) { 818 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); 819 return; 820 } 821 822 version = vop2_readl(vop2, RK3568_VERSION_INFO); 823 if (version != vop2->version) { 824 drm_err(vop2->drm, "Hardware version(0x%08x) mismatch\n", version); 825 return; 826 } 827 828 /* 829 * rk3566 share the same vop version with rk3568, so 830 * we need to use soc_id for identification here. 831 */ 832 if (vop2->data->soc_id == 3566) 833 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); 834 835 if (vop2->version == VOP_VERSION_RK3588) 836 rk3588_vop2_power_domain_enable_all(vop2); 837 838 if (vop2->version <= VOP_VERSION_RK3588) { 839 vop2->old_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); 840 vop2->old_port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); 841 } 842 843 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 844 845 /* 846 * Disable auto gating, this is a workaround to 847 * avoid display image shift when a window enabled. 848 */ 849 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, 850 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); 851 852 vop2_writel(vop2, RK3568_SYS0_INT_CLR, 853 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 854 vop2_writel(vop2, RK3568_SYS0_INT_EN, 855 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 856 vop2_writel(vop2, RK3568_SYS1_INT_CLR, 857 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 858 vop2_writel(vop2, RK3568_SYS1_INT_EN, 859 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 860 } 861 862 static void vop2_disable(struct vop2 *vop2) 863 { 864 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); 865 866 pm_runtime_put_sync(vop2->dev); 867 868 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); 869 870 clk_disable_unprepare(vop2->pclk); 871 clk_disable_unprepare(vop2->aclk); 872 clk_disable_unprepare(vop2->hclk); 873 } 874 875 static bool vop2_vp_dsp_lut_is_enabled(struct vop2_video_port *vp) 876 { 877 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 878 879 return dsp_ctrl & RK3568_VP_DSP_CTRL__DSP_LUT_EN; 880 } 881 882 static void vop2_vp_dsp_lut_disable(struct vop2_video_port *vp) 883 { 884 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 885 886 dsp_ctrl &= ~RK3568_VP_DSP_CTRL__DSP_LUT_EN; 887 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 888 } 889 890 static bool vop2_vp_dsp_lut_poll_disabled(struct vop2_video_port *vp) 891 { 892 u32 dsp_ctrl; 893 int ret = readx_poll_timeout(vop2_vp_dsp_lut_is_enabled, vp, dsp_ctrl, 894 !dsp_ctrl, 5, 30 * 1000); 895 if (ret) { 896 drm_err(vp->vop2->drm, "display LUT RAM enable timeout!\n"); 897 return false; 898 } 899 900 return true; 901 } 902 903 static void vop2_vp_dsp_lut_enable(struct vop2_video_port *vp) 904 { 905 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 906 907 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_LUT_EN; 908 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 909 } 910 911 static void vop2_vp_dsp_lut_update_enable(struct vop2_video_port *vp) 912 { 913 u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL); 914 915 dsp_ctrl |= RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN; 916 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 917 } 918 919 static inline bool vop2_supports_seamless_gamma_lut_update(struct vop2 *vop2) 920 { 921 return vop2->version != VOP_VERSION_RK3568; 922 } 923 924 static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp) 925 { 926 const int nr_vps = vop2->data->nr_vps; 927 int gamma_en_vp_id; 928 929 for (gamma_en_vp_id = 0; gamma_en_vp_id < nr_vps; gamma_en_vp_id++) 930 if (vop2_vp_dsp_lut_is_enabled(&vop2->vps[gamma_en_vp_id])) 931 break; 932 933 return gamma_en_vp_id != nr_vps && gamma_en_vp_id != vp->id; 934 } 935 936 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, 937 struct drm_atomic_state *state) 938 { 939 struct vop2_video_port *vp = to_vop2_video_port(crtc); 940 struct vop2 *vop2 = vp->vop2; 941 struct drm_crtc_state *old_crtc_state; 942 int ret; 943 944 vop2_lock(vop2); 945 946 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 947 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 948 949 drm_crtc_vblank_off(crtc); 950 951 /* 952 * Vop standby will take effect at end of current frame, 953 * if dsp hold valid irq happen, it means standby complete. 954 * 955 * we must wait standby complete when we want to disable aclk, 956 * if not, memory bus maybe dead. 957 */ 958 reinit_completion(&vp->dsp_hold_completion); 959 960 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); 961 962 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); 963 964 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, 965 msecs_to_jiffies(50)); 966 if (!ret) 967 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); 968 969 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); 970 971 if (vp->dclk_src) 972 clk_set_parent(vp->dclk, vp->dclk_src); 973 974 clk_disable_unprepare(vp->dclk); 975 976 vop2->enable_count--; 977 978 if (!vop2->enable_count) 979 vop2_disable(vop2); 980 981 vop2_unlock(vop2); 982 983 if (crtc->state->event && !crtc->state->active) { 984 spin_lock_irq(&crtc->dev->event_lock); 985 drm_crtc_send_vblank_event(crtc, crtc->state->event); 986 spin_unlock_irq(&crtc->dev->event_lock); 987 988 crtc->state->event = NULL; 989 } 990 } 991 992 static int vop2_plane_atomic_check(struct drm_plane *plane, 993 struct drm_atomic_state *astate) 994 { 995 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); 996 struct drm_framebuffer *fb = pstate->fb; 997 struct drm_crtc *crtc = pstate->crtc; 998 struct drm_crtc_state *cstate; 999 struct vop2_video_port *vp; 1000 struct vop2 *vop2; 1001 const struct vop2_data *vop2_data; 1002 struct drm_rect *dest = &pstate->dst; 1003 struct drm_rect *src = &pstate->src; 1004 int min_scale = FRAC_16_16(1, 8); 1005 int max_scale = FRAC_16_16(8, 1); 1006 int format; 1007 int ret; 1008 1009 if (!crtc) 1010 return 0; 1011 1012 vp = to_vop2_video_port(crtc); 1013 vop2 = vp->vop2; 1014 vop2_data = vop2->data; 1015 1016 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); 1017 if (WARN_ON(!cstate)) 1018 return -EINVAL; 1019 1020 ret = drm_atomic_helper_check_plane_state(pstate, cstate, 1021 min_scale, max_scale, 1022 true, true); 1023 if (ret) 1024 return ret; 1025 1026 if (!pstate->visible) 1027 return 0; 1028 1029 format = vop2_convert_format(fb->format->format); 1030 if (format < 0) 1031 return format; 1032 1033 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || 1034 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { 1035 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", 1036 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, 1037 drm_rect_width(dest), drm_rect_height(dest)); 1038 pstate->visible = false; 1039 return 0; 1040 } 1041 1042 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || 1043 drm_rect_height(src) >> 16 > vop2_data->max_input.height) { 1044 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", 1045 drm_rect_width(src) >> 16, 1046 drm_rect_height(src) >> 16, 1047 vop2_data->max_input.width, 1048 vop2_data->max_input.height); 1049 return -EINVAL; 1050 } 1051 1052 /* 1053 * Src.x1 can be odd when do clip, but yuv plane start point 1054 * need align with 2 pixel. 1055 */ 1056 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { 1057 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); 1058 return -EINVAL; 1059 } 1060 1061 return 0; 1062 } 1063 1064 static void vop2_plane_atomic_disable(struct drm_plane *plane, 1065 struct drm_atomic_state *state) 1066 { 1067 struct drm_plane_state *old_pstate = NULL; 1068 struct vop2_win *win = to_vop2_win(plane); 1069 struct vop2 *vop2 = win->vop2; 1070 1071 drm_dbg(vop2->drm, "%s disable\n", win->data->name); 1072 1073 if (state) 1074 old_pstate = drm_atomic_get_old_plane_state(state, plane); 1075 if (old_pstate && !old_pstate->crtc) 1076 return; 1077 1078 vop2_win_disable(win); 1079 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); 1080 } 1081 1082 /* 1083 * The color key is 10 bit, so all format should 1084 * convert to 10 bit here. 1085 */ 1086 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) 1087 { 1088 struct drm_plane_state *pstate = plane->state; 1089 struct drm_framebuffer *fb = pstate->fb; 1090 struct vop2_win *win = to_vop2_win(plane); 1091 u32 color_key_en = 0; 1092 u32 r = 0; 1093 u32 g = 0; 1094 u32 b = 0; 1095 1096 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { 1097 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); 1098 return; 1099 } 1100 1101 switch (fb->format->format) { 1102 case DRM_FORMAT_RGB565: 1103 case DRM_FORMAT_BGR565: 1104 r = (color_key & 0xf800) >> 11; 1105 g = (color_key & 0x7e0) >> 5; 1106 b = (color_key & 0x1f); 1107 r <<= 5; 1108 g <<= 4; 1109 b <<= 5; 1110 color_key_en = 1; 1111 break; 1112 case DRM_FORMAT_XRGB8888: 1113 case DRM_FORMAT_ARGB8888: 1114 case DRM_FORMAT_XBGR8888: 1115 case DRM_FORMAT_ABGR8888: 1116 case DRM_FORMAT_RGB888: 1117 case DRM_FORMAT_BGR888: 1118 r = (color_key & 0xff0000) >> 16; 1119 g = (color_key & 0xff00) >> 8; 1120 b = (color_key & 0xff); 1121 r <<= 2; 1122 g <<= 2; 1123 b <<= 2; 1124 color_key_en = 1; 1125 break; 1126 } 1127 1128 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); 1129 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); 1130 } 1131 1132 static void vop2_plane_atomic_update(struct drm_plane *plane, 1133 struct drm_atomic_state *state) 1134 { 1135 struct drm_plane_state *pstate = plane->state; 1136 struct drm_crtc *crtc = pstate->crtc; 1137 struct vop2_win *win = to_vop2_win(plane); 1138 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1139 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1140 struct vop2 *vop2 = win->vop2; 1141 struct drm_framebuffer *fb = pstate->fb; 1142 u32 bpp = vop2_get_bpp(fb->format); 1143 u32 actual_w, actual_h, dsp_w, dsp_h; 1144 u32 act_info, dsp_info; 1145 u32 format; 1146 u32 afbc_format; 1147 u32 rb_swap; 1148 u32 uv_swap; 1149 struct drm_rect *src = &pstate->src; 1150 struct drm_rect *dest = &pstate->dst; 1151 u32 afbc_tile_num; 1152 u32 transform_offset; 1153 bool dither_up; 1154 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1155 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1156 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1157 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1158 struct rockchip_gem_object *rk_obj; 1159 unsigned long offset; 1160 bool half_block_en; 1161 bool afbc_en; 1162 dma_addr_t yrgb_mst; 1163 dma_addr_t uv_mst; 1164 1165 /* 1166 * can't update plane when vop2 is disabled. 1167 */ 1168 if (WARN_ON(!crtc)) 1169 return; 1170 1171 if (!pstate->visible) { 1172 vop2_plane_atomic_disable(plane, state); 1173 return; 1174 } 1175 1176 afbc_en = rockchip_afbc(plane, fb->modifier); 1177 1178 offset = (src->x1 >> 16) * fb->format->cpp[0]; 1179 1180 /* 1181 * AFBC HDR_PTR must set to the zero offset of the framebuffer. 1182 */ 1183 if (afbc_en) 1184 offset = 0; 1185 else if (pstate->rotation & DRM_MODE_REFLECT_Y) 1186 offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; 1187 else 1188 offset += (src->y1 >> 16) * fb->pitches[0]; 1189 1190 rk_obj = to_rockchip_obj(fb->obj[0]); 1191 1192 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 1193 if (fb->format->is_yuv) { 1194 int hsub = fb->format->hsub; 1195 int vsub = fb->format->vsub; 1196 1197 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; 1198 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 1199 1200 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) 1201 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; 1202 1203 rk_obj = to_rockchip_obj(fb->obj[0]); 1204 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; 1205 } 1206 1207 actual_w = drm_rect_width(src) >> 16; 1208 actual_h = drm_rect_height(src) >> 16; 1209 dsp_w = drm_rect_width(dest); 1210 1211 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { 1212 drm_dbg_kms(vop2->drm, 1213 "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", 1214 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); 1215 dsp_w = adjusted_mode->hdisplay - dest->x1; 1216 if (dsp_w < 4) 1217 dsp_w = 4; 1218 actual_w = dsp_w * actual_w / drm_rect_width(dest); 1219 } 1220 1221 dsp_h = drm_rect_height(dest); 1222 1223 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { 1224 drm_dbg_kms(vop2->drm, 1225 "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", 1226 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); 1227 dsp_h = adjusted_mode->vdisplay - dest->y1; 1228 if (dsp_h < 4) 1229 dsp_h = 4; 1230 actual_h = dsp_h * actual_h / drm_rect_height(dest); 1231 } 1232 1233 /* 1234 * This is workaround solution for IC design: 1235 * esmart can't support scale down when actual_w % 16 == 1. 1236 */ 1237 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 1238 if (actual_w > dsp_w && (actual_w & 0xf) == 1) { 1239 drm_dbg_kms(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", 1240 vp->id, win->data->name, actual_w); 1241 actual_w -= 1; 1242 } 1243 } 1244 1245 if (afbc_en && actual_w % 4) { 1246 drm_dbg_kms(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", 1247 vp->id, win->data->name, actual_w); 1248 actual_w = ALIGN_DOWN(actual_w, 4); 1249 } 1250 1251 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 1252 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); 1253 1254 format = vop2_convert_format(fb->format->format); 1255 half_block_en = vop2_half_block_enable(pstate); 1256 1257 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", 1258 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, 1259 dest->x1, dest->y1, 1260 &fb->format->format, 1261 afbc_en ? "AFBC" : "", &yrgb_mst); 1262 1263 if (vop2->version > VOP_VERSION_RK3568) { 1264 vop2_win_write(win, VOP2_WIN_AXI_BUS_ID, win->data->axi_bus_id); 1265 vop2_win_write(win, VOP2_WIN_AXI_YRGB_R_ID, win->data->axi_yrgb_r_id); 1266 vop2_win_write(win, VOP2_WIN_AXI_UV_R_ID, win->data->axi_uv_r_id); 1267 } 1268 1269 if (vop2->version >= VOP_VERSION_RK3576) 1270 vop2_win_write(win, VOP2_WIN_VP_SEL, vp->id); 1271 1272 if (vop2_cluster_window(win)) 1273 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en); 1274 1275 if (afbc_en) { 1276 u32 stride, block_w; 1277 1278 /* the afbc superblock is 16 x 16 or 32 x 8 */ 1279 block_w = fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 ? 32 : 16; 1280 1281 afbc_format = vop2_convert_afbc_format(fb->format->format); 1282 1283 /* Enable color transform for YTR */ 1284 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 1285 afbc_format |= (1 << 4); 1286 1287 afbc_tile_num = ALIGN(actual_w, block_w) / block_w; 1288 1289 /* 1290 * AFBC pic_vir_width is count by pixel, this is different 1291 * with WIN_VIR_STRIDE. 1292 */ 1293 stride = (fb->pitches[0] << 3) / bpp; 1294 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) 1295 drm_dbg_kms(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", 1296 vp->id, win->data->name, stride); 1297 1298 /* It's for head stride, each head size is 16 byte */ 1299 stride = ALIGN(stride, block_w) / block_w * 16; 1300 1301 uv_swap = vop2_afbc_uv_swap(fb->format->format); 1302 /* 1303 * This is a workaround for crazy IC design, Cluster 1304 * and Esmart/Smart use different format configuration map: 1305 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. 1306 * 1307 * This is one thing we can make the convert simple: 1308 * AFBCD decode all the YUV data to YUV444. So we just 1309 * set all the yuv 10 bit to YUV444_10. 1310 */ 1311 if (fb->format->is_yuv && bpp == 10) 1312 format = VOP2_CLUSTER_YUV444_10; 1313 1314 if (vop2_cluster_window(win)) 1315 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); 1316 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); 1317 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); 1318 /* 1319 * On rk3566/8, this bit is auto gating enable, 1320 * but this function is not work well so we need 1321 * to disable it for these two platform. 1322 * On rk3588, and the following new soc(rk3528/rk3576), 1323 * this bit is gating disable, we should write 1 to 1324 * disable gating when enable afbc. 1325 */ 1326 if (vop2->version == VOP_VERSION_RK3568) 1327 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); 1328 else 1329 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1); 1330 1331 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT) 1332 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 1); 1333 else 1334 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); 1335 1336 if (vop2->version >= VOP_VERSION_RK3576) { 1337 vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET_EN, 1); 1338 vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET, yrgb_mst); 1339 } 1340 1341 transform_offset = vop2_afbc_transform_offset(pstate, half_block_en); 1342 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); 1343 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); 1344 vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, transform_offset); 1345 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); 1346 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); 1347 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); 1348 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); 1349 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); 1350 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); 1351 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); 1352 } else { 1353 if (vop2_cluster_window(win)) { 1354 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0); 1355 vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, 0); 1356 } 1357 1358 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); 1359 } 1360 1361 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); 1362 1363 if (rotate_90 || rotate_270) { 1364 act_info = swahw32(act_info); 1365 actual_w = drm_rect_height(src) >> 16; 1366 actual_h = drm_rect_width(src) >> 16; 1367 } 1368 1369 vop2_win_write(win, VOP2_WIN_FORMAT, format); 1370 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); 1371 1372 rb_swap = vop2_win_rb_swap(fb->format->format); 1373 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); 1374 uv_swap = vop2_win_uv_swap(fb->format->format); 1375 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); 1376 1377 if (fb->format->is_yuv) { 1378 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); 1379 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); 1380 } 1381 1382 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); 1383 if (!vop2_cluster_window(win)) 1384 vop2_plane_setup_color_key(plane, 0); 1385 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); 1386 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); 1387 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); 1388 1389 vop2_setup_csc_mode(vp, win, pstate); 1390 1391 dither_up = vop2_win_dither_up(fb->format->format); 1392 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); 1393 1394 vop2_win_write(win, VOP2_WIN_ENABLE, 1); 1395 1396 if (vop2_cluster_window(win)) { 1397 int lb_mode = vop2_get_cluster_lb_mode(win, pstate); 1398 1399 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); 1400 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); 1401 } 1402 } 1403 1404 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { 1405 .atomic_check = vop2_plane_atomic_check, 1406 .atomic_update = vop2_plane_atomic_update, 1407 .atomic_disable = vop2_plane_atomic_disable, 1408 }; 1409 1410 static const struct drm_plane_funcs vop2_plane_funcs = { 1411 .update_plane = drm_atomic_helper_update_plane, 1412 .disable_plane = drm_atomic_helper_disable_plane, 1413 .destroy = drm_plane_cleanup, 1414 .reset = drm_atomic_helper_plane_reset, 1415 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1416 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1417 .format_mod_supported = rockchip_vop2_mod_supported, 1418 }; 1419 1420 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) 1421 { 1422 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1423 1424 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); 1425 1426 return 0; 1427 } 1428 1429 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) 1430 { 1431 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1432 1433 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); 1434 } 1435 1436 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, 1437 const struct drm_display_mode *mode, 1438 struct drm_display_mode *adj_mode) 1439 { 1440 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | 1441 CRTC_STEREO_DOUBLE); 1442 1443 return true; 1444 } 1445 1446 static void vop2_crtc_write_gamma_lut(struct vop2 *vop2, struct drm_crtc *crtc) 1447 { 1448 const struct vop2_video_port *vp = to_vop2_video_port(crtc); 1449 const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id]; 1450 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1451 unsigned int i, bpc = ilog2(vp_data->gamma_lut_len); 1452 u32 word; 1453 1454 for (i = 0; i < crtc->gamma_size; i++) { 1455 word = (drm_color_lut_extract(lut[i].blue, bpc) << (2 * bpc)) | 1456 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1457 drm_color_lut_extract(lut[i].red, bpc); 1458 1459 writel(word, vop2->lut_regs + i * 4); 1460 } 1461 } 1462 1463 static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2, 1464 struct vop2_video_port *vp, 1465 struct drm_crtc *crtc) 1466 { 1467 vop2_writel(vop2, RK3568_LUT_PORT_SEL, 1468 FIELD_PREP(RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, vp->id)); 1469 vop2_vp_dsp_lut_enable(vp); 1470 vop2_crtc_write_gamma_lut(vop2, crtc); 1471 vop2_vp_dsp_lut_update_enable(vp); 1472 } 1473 1474 static void vop2_crtc_atomic_set_gamma_rk356x(struct vop2 *vop2, 1475 struct vop2_video_port *vp, 1476 struct drm_crtc *crtc) 1477 { 1478 vop2_vp_dsp_lut_disable(vp); 1479 vop2_cfg_done(vp); 1480 if (!vop2_vp_dsp_lut_poll_disabled(vp)) 1481 return; 1482 1483 vop2_writel(vop2, RK3568_LUT_PORT_SEL, vp->id); 1484 vop2_crtc_write_gamma_lut(vop2, crtc); 1485 vop2_vp_dsp_lut_enable(vp); 1486 } 1487 1488 static void vop2_crtc_atomic_try_set_gamma(struct vop2 *vop2, 1489 struct vop2_video_port *vp, 1490 struct drm_crtc *crtc, 1491 struct drm_crtc_state *crtc_state) 1492 { 1493 if (!vop2->lut_regs) 1494 return; 1495 1496 if (!crtc_state->gamma_lut) { 1497 vop2_vp_dsp_lut_disable(vp); 1498 return; 1499 } 1500 1501 if (vop2_supports_seamless_gamma_lut_update(vop2)) 1502 vop2_crtc_atomic_set_gamma_seamless(vop2, vp, crtc); 1503 else 1504 vop2_crtc_atomic_set_gamma_rk356x(vop2, vp, crtc); 1505 } 1506 1507 static inline void vop2_crtc_atomic_try_set_gamma_locked(struct vop2 *vop2, 1508 struct vop2_video_port *vp, 1509 struct drm_crtc *crtc, 1510 struct drm_crtc_state *crtc_state) 1511 { 1512 vop2_lock(vop2); 1513 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); 1514 vop2_unlock(vop2); 1515 } 1516 1517 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) 1518 { 1519 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1520 1521 switch (vcstate->bus_format) { 1522 case MEDIA_BUS_FMT_RGB565_1X16: 1523 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1524 break; 1525 case MEDIA_BUS_FMT_RGB666_1X18: 1526 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1527 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1528 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1529 *dsp_ctrl |= RGB888_TO_RGB666; 1530 break; 1531 case MEDIA_BUS_FMT_YUV8_1X24: 1532 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1533 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) 1540 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1541 1542 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, 1543 DITHER_DOWN_ALLEGRO); 1544 } 1545 1546 static void vop2_post_config(struct drm_crtc *crtc) 1547 { 1548 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1549 struct vop2 *vop2 = vp->vop2; 1550 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1551 u16 vtotal = mode->crtc_vtotal; 1552 u16 hdisplay = mode->crtc_hdisplay; 1553 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1554 u16 vdisplay = mode->crtc_vdisplay; 1555 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1556 u32 left_margin = 100, right_margin = 100; 1557 u32 top_margin = 100, bottom_margin = 100; 1558 u16 hsize = hdisplay * (left_margin + right_margin) / 200; 1559 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; 1560 u16 hact_end, vact_end; 1561 u32 val; 1562 1563 vop2->ops->setup_bg_dly(vp); 1564 1565 vsize = rounddown(vsize, 2); 1566 hsize = rounddown(hsize, 2); 1567 hact_st += hdisplay * (100 - left_margin) / 200; 1568 hact_end = hact_st + hsize; 1569 val = hact_st << 16; 1570 val |= hact_end; 1571 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); 1572 vact_st += vdisplay * (100 - top_margin) / 200; 1573 vact_end = vact_st + vsize; 1574 val = vact_st << 16; 1575 val |= vact_end; 1576 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); 1577 val = scl_cal_scale2(vdisplay, vsize) << 16; 1578 val |= scl_cal_scale2(hdisplay, hsize); 1579 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); 1580 1581 val = 0; 1582 if (hdisplay != hsize) 1583 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; 1584 if (vdisplay != vsize) 1585 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; 1586 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); 1587 1588 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1589 u16 vact_st_f1 = vtotal + vact_st + 1; 1590 u16 vact_end_f1 = vact_st_f1 + vsize; 1591 1592 val = vact_st_f1 << 16 | vact_end_f1; 1593 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); 1594 } 1595 1596 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); 1597 } 1598 1599 static int us_to_vertical_line(struct drm_display_mode *mode, int us) 1600 { 1601 return us * mode->clock / mode->htotal / 1000; 1602 } 1603 1604 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 1605 struct drm_atomic_state *state) 1606 { 1607 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1608 struct vop2 *vop2 = vp->vop2; 1609 const struct vop2_data *vop2_data = vop2->data; 1610 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 1611 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1612 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1613 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1614 unsigned long clock = mode->crtc_clock * 1000; 1615 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1616 u16 hdisplay = mode->crtc_hdisplay; 1617 u16 htotal = mode->crtc_htotal; 1618 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1619 u16 hact_end = hact_st + hdisplay; 1620 u16 vdisplay = mode->crtc_vdisplay; 1621 u16 vtotal = mode->crtc_vtotal; 1622 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1623 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1624 u16 vact_end = vact_st + vdisplay; 1625 u8 out_mode; 1626 u32 dsp_ctrl = 0; 1627 int act_end; 1628 u32 val, polflags; 1629 int ret; 1630 struct drm_encoder *encoder; 1631 1632 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", 1633 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1634 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); 1635 1636 vop2_lock(vop2); 1637 1638 ret = clk_prepare_enable(vp->dclk); 1639 if (ret < 0) { 1640 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", 1641 vp->id, ret); 1642 vop2_unlock(vop2); 1643 return; 1644 } 1645 1646 if (!vop2->enable_count) 1647 vop2_enable(vop2); 1648 1649 vop2->enable_count++; 1650 1651 vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format); 1652 1653 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); 1654 1655 polflags = 0; 1656 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 1657 polflags |= POLFLAG_DCLK_INV; 1658 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1659 polflags |= BIT(HSYNC_POSITIVE); 1660 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1661 polflags |= BIT(VSYNC_POSITIVE); 1662 1663 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1664 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1665 1666 /* 1667 * for drive a high resolution(4KP120, 8K), vop on rk3588/rk3576 need 1668 * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the 1669 * system cru may be the 1/2 or 1/4 of mode->clock. 1670 */ 1671 clock = vop2->ops->setup_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); 1672 } 1673 1674 if (!clock) { 1675 vop2_unlock(vop2); 1676 return; 1677 } 1678 1679 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1680 !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT)) 1681 out_mode = ROCKCHIP_OUT_MODE_P888; 1682 else 1683 out_mode = vcstate->output_mode; 1684 1685 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); 1686 1687 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) 1688 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; 1689 if (vop2_output_rg_swap(vop2, vcstate->bus_format)) 1690 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP; 1691 1692 if (vcstate->yuv_overlay) 1693 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; 1694 1695 vop2_dither_setup(crtc, &dsp_ctrl); 1696 1697 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); 1698 val = hact_st << 16; 1699 val |= hact_end; 1700 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); 1701 1702 val = vact_st << 16; 1703 val |= vact_end; 1704 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); 1705 1706 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1707 u16 vact_st_f1 = vtotal + vact_st + 1; 1708 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1709 1710 val = vact_st_f1 << 16 | vact_end_f1; 1711 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); 1712 1713 val = vtotal << 16 | (vtotal + vsync_len); 1714 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); 1715 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; 1716 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; 1717 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; 1718 vtotal += vtotal + 1; 1719 act_end = vact_end_f1; 1720 } else { 1721 act_end = vact_end; 1722 } 1723 1724 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), 1725 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); 1726 1727 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); 1728 1729 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1730 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; 1731 clock *= 2; 1732 } 1733 1734 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); 1735 1736 /* 1737 * Switch to HDMI PHY PLL as DCLK source for display modes up 1738 * to 4K@60Hz, if available, otherwise keep using the system CRU. 1739 */ 1740 if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { 1741 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1742 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1743 1744 if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { 1745 if (!vop2->pll_hdmiphy0) 1746 break; 1747 1748 if (!vp->dclk_src) 1749 vp->dclk_src = clk_get_parent(vp->dclk); 1750 1751 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); 1752 if (ret < 0) 1753 drm_warn(vop2->drm, 1754 "Could not switch to HDMI0 PHY PLL: %d\n", ret); 1755 break; 1756 } 1757 1758 if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { 1759 if (!vop2->pll_hdmiphy1) 1760 break; 1761 1762 if (!vp->dclk_src) 1763 vp->dclk_src = clk_get_parent(vp->dclk); 1764 1765 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); 1766 if (ret < 0) 1767 drm_warn(vop2->drm, 1768 "Could not switch to HDMI1 PHY PLL: %d\n", ret); 1769 break; 1770 } 1771 } 1772 } 1773 1774 clk_set_rate(vp->dclk, clock); 1775 1776 vop2_post_config(crtc); 1777 1778 vop2_cfg_done(vp); 1779 1780 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 1781 1782 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); 1783 1784 drm_crtc_vblank_on(crtc); 1785 1786 vop2_unlock(vop2); 1787 } 1788 1789 static int vop2_crtc_atomic_check_gamma(struct vop2_video_port *vp, 1790 struct drm_crtc *crtc, 1791 struct drm_atomic_state *state, 1792 struct drm_crtc_state *crtc_state) 1793 { 1794 struct vop2 *vop2 = vp->vop2; 1795 unsigned int len; 1796 1797 if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed || 1798 !crtc_state->gamma_lut) 1799 return 0; 1800 1801 len = drm_color_lut_size(crtc_state->gamma_lut); 1802 if (len != crtc->gamma_size) { 1803 drm_dbg(vop2->drm, "Invalid LUT size; got %d, expected %d\n", 1804 len, crtc->gamma_size); 1805 return -EINVAL; 1806 } 1807 1808 if (!vop2_supports_seamless_gamma_lut_update(vop2) && vop2_gamma_lut_in_use(vop2, vp)) { 1809 drm_info(vop2->drm, "Gamma LUT can be enabled for only one CRTC at a time\n"); 1810 return -EINVAL; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int vop2_crtc_atomic_check(struct drm_crtc *crtc, 1817 struct drm_atomic_state *state) 1818 { 1819 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1820 struct drm_plane *plane; 1821 int nplanes = 0; 1822 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1823 int ret; 1824 1825 ret = vop2_crtc_atomic_check_gamma(vp, crtc, state, crtc_state); 1826 if (ret) 1827 return ret; 1828 1829 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) 1830 nplanes++; 1831 1832 if (nplanes > vp->nlayers) 1833 return -EINVAL; 1834 1835 return 0; 1836 } 1837 1838 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, 1839 struct drm_atomic_state *state) 1840 { 1841 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1842 struct vop2 *vop2 = vp->vop2; 1843 1844 vop2->ops->setup_overlay(vp); 1845 } 1846 1847 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, 1848 struct drm_atomic_state *state) 1849 { 1850 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1851 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1852 struct vop2 *vop2 = vp->vop2; 1853 1854 /* In case of modeset, gamma lut update already happened in atomic enable */ 1855 if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_changed) 1856 vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); 1857 1858 vop2_post_config(crtc); 1859 1860 vop2_cfg_done(vp); 1861 1862 spin_lock_irq(&crtc->dev->event_lock); 1863 1864 if (crtc->state->event) { 1865 WARN_ON(drm_crtc_vblank_get(crtc)); 1866 vp->event = crtc->state->event; 1867 crtc->state->event = NULL; 1868 } 1869 1870 spin_unlock_irq(&crtc->dev->event_lock); 1871 } 1872 1873 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { 1874 .mode_fixup = vop2_crtc_mode_fixup, 1875 .atomic_check = vop2_crtc_atomic_check, 1876 .atomic_begin = vop2_crtc_atomic_begin, 1877 .atomic_flush = vop2_crtc_atomic_flush, 1878 .atomic_enable = vop2_crtc_atomic_enable, 1879 .atomic_disable = vop2_crtc_atomic_disable, 1880 }; 1881 1882 static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *s) 1883 { 1884 struct drm_connector_list_iter conn_iter; 1885 struct drm_connector *connector; 1886 1887 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 1888 drm_for_each_connector_iter(connector, &conn_iter) { 1889 if (crtc->state->connector_mask & drm_connector_mask(connector)) 1890 seq_printf(s, " Connector: %s\n", connector->name); 1891 } 1892 drm_connector_list_iter_end(&conn_iter); 1893 } 1894 1895 static int vop2_plane_state_dump(struct seq_file *s, struct drm_plane *plane) 1896 { 1897 struct vop2_win *win = to_vop2_win(plane); 1898 struct drm_plane_state *pstate = plane->state; 1899 struct drm_rect *src, *dst; 1900 struct drm_framebuffer *fb; 1901 struct drm_gem_object *obj; 1902 struct rockchip_gem_object *rk_obj; 1903 bool xmirror; 1904 bool ymirror; 1905 bool rotate_270; 1906 bool rotate_90; 1907 dma_addr_t fb_addr; 1908 int i; 1909 1910 seq_printf(s, " %s: %s\n", win->data->name, !pstate ? 1911 "DISABLED" : pstate->crtc ? "ACTIVE" : "DISABLED"); 1912 1913 if (!pstate || !pstate->fb) 1914 return 0; 1915 1916 fb = pstate->fb; 1917 src = &pstate->src; 1918 dst = &pstate->dst; 1919 xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1920 ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1921 rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1922 rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1923 1924 seq_printf(s, "\twin_id: %d\n", win->win_id); 1925 1926 seq_printf(s, "\tformat: %p4cc%s glb_alpha[0x%x]\n", 1927 &fb->format->format, 1928 drm_is_afbc(fb->modifier) ? "[AFBC]" : "", 1929 pstate->alpha >> 8); 1930 seq_printf(s, "\trotate: xmirror: %d ymirror: %d rotate_90: %d rotate_270: %d\n", 1931 xmirror, ymirror, rotate_90, rotate_270); 1932 seq_printf(s, "\tzpos: %d\n", pstate->normalized_zpos); 1933 seq_printf(s, "\tsrc: pos[%d, %d] rect[%d x %d]\n", src->x1 >> 16, 1934 src->y1 >> 16, drm_rect_width(src) >> 16, 1935 drm_rect_height(src) >> 16); 1936 seq_printf(s, "\tdst: pos[%d, %d] rect[%d x %d]\n", dst->x1, dst->y1, 1937 drm_rect_width(dst), drm_rect_height(dst)); 1938 1939 for (i = 0; i < fb->format->num_planes; i++) { 1940 obj = fb->obj[i]; 1941 rk_obj = to_rockchip_obj(obj); 1942 fb_addr = rk_obj->dma_addr + fb->offsets[i]; 1943 1944 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n", 1945 i, &fb_addr, fb->pitches[i], fb->offsets[i]); 1946 } 1947 1948 return 0; 1949 } 1950 1951 static int vop2_crtc_state_dump(struct drm_crtc *crtc, struct seq_file *s) 1952 { 1953 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1954 struct drm_crtc_state *cstate = crtc->state; 1955 struct rockchip_crtc_state *vcstate; 1956 struct drm_display_mode *mode; 1957 struct drm_plane *plane; 1958 bool interlaced; 1959 1960 seq_printf(s, "Video Port%d: %s\n", vp->id, !cstate ? 1961 "DISABLED" : cstate->active ? "ACTIVE" : "DISABLED"); 1962 1963 if (!cstate || !cstate->active) 1964 return 0; 1965 1966 mode = &crtc->state->adjusted_mode; 1967 vcstate = to_rockchip_crtc_state(cstate); 1968 interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1969 1970 vop2_dump_connector_on_crtc(crtc, s); 1971 seq_printf(s, "\tbus_format[%x]: %s\n", vcstate->bus_format, 1972 drm_get_bus_format_name(vcstate->bus_format)); 1973 seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode); 1974 seq_printf(s, " color_space[%d]\n", vcstate->color_space); 1975 seq_printf(s, " Display mode: %dx%d%s%d\n", 1976 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p", 1977 drm_mode_vrefresh(mode)); 1978 seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n", 1979 mode->clock, mode->crtc_clock, mode->type, mode->flags); 1980 seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start, 1981 mode->hsync_end, mode->htotal); 1982 seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start, 1983 mode->vsync_end, mode->vtotal); 1984 1985 drm_atomic_crtc_for_each_plane(plane, crtc) { 1986 vop2_plane_state_dump(s, plane); 1987 } 1988 1989 return 0; 1990 } 1991 1992 static int vop2_summary_show(struct seq_file *s, void *data) 1993 { 1994 struct drm_info_node *node = s->private; 1995 struct drm_minor *minor = node->minor; 1996 struct drm_device *drm_dev = minor->dev; 1997 struct drm_crtc *crtc; 1998 1999 drm_modeset_lock_all(drm_dev); 2000 drm_for_each_crtc(crtc, drm_dev) { 2001 vop2_crtc_state_dump(crtc, s); 2002 } 2003 drm_modeset_unlock_all(drm_dev); 2004 2005 return 0; 2006 } 2007 2008 static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s, 2009 const struct vop2_regs_dump *dump, bool active_only) 2010 { 2011 resource_size_t start; 2012 u32 val; 2013 int i; 2014 2015 if (dump->en_mask && active_only) { 2016 val = vop2_readl(vop2, dump->base + dump->en_reg); 2017 if ((val & dump->en_mask) != dump->en_val) 2018 return; 2019 } 2020 2021 seq_printf(s, "\n%s:\n", dump->name); 2022 2023 start = vop2->res->start + dump->base; 2024 for (i = 0; i < dump->size >> 2; i += 4) { 2025 seq_printf(s, "%08x: %08x %08x %08x %08x\n", (u32)start + i * 4, 2026 vop2_readl(vop2, dump->base + (4 * i)), 2027 vop2_readl(vop2, dump->base + (4 * (i + 1))), 2028 vop2_readl(vop2, dump->base + (4 * (i + 2))), 2029 vop2_readl(vop2, dump->base + (4 * (i + 3)))); 2030 } 2031 } 2032 2033 static void __vop2_regs_dump(struct seq_file *s, bool active_only) 2034 { 2035 struct drm_info_node *node = s->private; 2036 struct vop2 *vop2 = node->info_ent->data; 2037 struct drm_minor *minor = node->minor; 2038 struct drm_device *drm_dev = minor->dev; 2039 const struct vop2_regs_dump *dump; 2040 unsigned int i; 2041 2042 drm_modeset_lock_all(drm_dev); 2043 2044 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); 2045 2046 if (vop2->enable_count) { 2047 for (i = 0; i < vop2->data->regs_dump_size; i++) { 2048 dump = &vop2->data->regs_dump[i]; 2049 vop2_regs_print(vop2, s, dump, active_only); 2050 } 2051 } else { 2052 seq_puts(s, "VOP disabled\n"); 2053 } 2054 drm_modeset_unlock_all(drm_dev); 2055 } 2056 2057 static int vop2_regs_show(struct seq_file *s, void *arg) 2058 { 2059 __vop2_regs_dump(s, false); 2060 2061 return 0; 2062 } 2063 2064 static int vop2_active_regs_show(struct seq_file *s, void *data) 2065 { 2066 __vop2_regs_dump(s, true); 2067 2068 return 0; 2069 } 2070 2071 static struct drm_info_list vop2_debugfs_list[] = { 2072 { "summary", vop2_summary_show, 0, NULL }, 2073 { "active_regs", vop2_active_regs_show, 0, NULL }, 2074 { "regs", vop2_regs_show, 0, NULL }, 2075 }; 2076 2077 static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor) 2078 { 2079 struct dentry *root; 2080 unsigned int i; 2081 2082 root = debugfs_create_dir("vop2", minor->debugfs_root); 2083 if (!IS_ERR(root)) { 2084 for (i = 0; i < ARRAY_SIZE(vop2_debugfs_list); i++) 2085 vop2_debugfs_list[i].data = vop2; 2086 2087 drm_debugfs_create_files(vop2_debugfs_list, 2088 ARRAY_SIZE(vop2_debugfs_list), 2089 root, minor); 2090 } 2091 } 2092 2093 static int vop2_crtc_late_register(struct drm_crtc *crtc) 2094 { 2095 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2096 struct vop2 *vop2 = vp->vop2; 2097 2098 if (drm_crtc_index(crtc) == 0) 2099 vop2_debugfs_init(vop2, crtc->dev->primary); 2100 2101 return 0; 2102 } 2103 2104 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) 2105 { 2106 struct rockchip_crtc_state *vcstate; 2107 2108 if (WARN_ON(!crtc->state)) 2109 return NULL; 2110 2111 vcstate = kmemdup(to_rockchip_crtc_state(crtc->state), 2112 sizeof(*vcstate), GFP_KERNEL); 2113 if (!vcstate) 2114 return NULL; 2115 2116 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); 2117 2118 return &vcstate->base; 2119 } 2120 2121 static void vop2_crtc_destroy_state(struct drm_crtc *crtc, 2122 struct drm_crtc_state *state) 2123 { 2124 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); 2125 2126 __drm_atomic_helper_crtc_destroy_state(&vcstate->base); 2127 kfree(vcstate); 2128 } 2129 2130 static void vop2_crtc_reset(struct drm_crtc *crtc) 2131 { 2132 struct rockchip_crtc_state *vcstate = 2133 kzalloc(sizeof(*vcstate), GFP_KERNEL); 2134 2135 if (crtc->state) 2136 vop2_crtc_destroy_state(crtc, crtc->state); 2137 2138 if (vcstate) 2139 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base); 2140 else 2141 __drm_atomic_helper_crtc_reset(crtc, NULL); 2142 } 2143 2144 static const struct drm_crtc_funcs vop2_crtc_funcs = { 2145 .set_config = drm_atomic_helper_set_config, 2146 .page_flip = drm_atomic_helper_page_flip, 2147 .destroy = drm_crtc_cleanup, 2148 .reset = vop2_crtc_reset, 2149 .atomic_duplicate_state = vop2_crtc_duplicate_state, 2150 .atomic_destroy_state = vop2_crtc_destroy_state, 2151 .enable_vblank = vop2_crtc_enable_vblank, 2152 .disable_vblank = vop2_crtc_disable_vblank, 2153 .late_register = vop2_crtc_late_register, 2154 }; 2155 2156 static irqreturn_t rk3576_vp_isr(int irq, void *data) 2157 { 2158 struct vop2_video_port *vp = data; 2159 struct vop2 *vop2 = vp->vop2; 2160 struct drm_crtc *crtc = &vp->crtc; 2161 uint32_t irqs; 2162 int ret = IRQ_NONE; 2163 2164 if (!pm_runtime_get_if_in_use(vop2->dev)) 2165 return IRQ_NONE; 2166 2167 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2168 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2169 2170 if (irqs & VP_INT_DSP_HOLD_VALID) { 2171 complete(&vp->dsp_hold_completion); 2172 ret = IRQ_HANDLED; 2173 } 2174 2175 if (irqs & VP_INT_FS_FIELD) { 2176 drm_crtc_handle_vblank(crtc); 2177 spin_lock(&crtc->dev->event_lock); 2178 if (vp->event) { 2179 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2180 2181 if (!(val & BIT(vp->id))) { 2182 drm_crtc_send_vblank_event(crtc, vp->event); 2183 vp->event = NULL; 2184 drm_crtc_vblank_put(crtc); 2185 } 2186 } 2187 spin_unlock(&crtc->dev->event_lock); 2188 2189 ret = IRQ_HANDLED; 2190 } 2191 2192 if (irqs & VP_INT_POST_BUF_EMPTY) { 2193 drm_err_ratelimited(vop2->drm, "POST_BUF_EMPTY irq err at vp%d\n", vp->id); 2194 ret = IRQ_HANDLED; 2195 } 2196 2197 pm_runtime_put(vop2->dev); 2198 2199 return ret; 2200 } 2201 2202 static irqreturn_t vop2_isr(int irq, void *data) 2203 { 2204 struct vop2 *vop2 = data; 2205 const struct vop2_data *vop2_data = vop2->data; 2206 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; 2207 int ret = IRQ_NONE; 2208 int i; 2209 2210 /* 2211 * The irq is shared with the iommu. If the runtime-pm state of the 2212 * vop2-device is disabled the irq has to be targeted at the iommu. 2213 */ 2214 if (!pm_runtime_get_if_in_use(vop2->dev)) 2215 return IRQ_NONE; 2216 2217 if (vop2->version < VOP_VERSION_RK3576) { 2218 for (i = 0; i < vop2_data->nr_vps; i++) { 2219 struct vop2_video_port *vp = &vop2->vps[i]; 2220 struct drm_crtc *crtc = &vp->crtc; 2221 u32 irqs; 2222 2223 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2224 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2225 2226 if (irqs & VP_INT_DSP_HOLD_VALID) { 2227 complete(&vp->dsp_hold_completion); 2228 ret = IRQ_HANDLED; 2229 } 2230 2231 if (irqs & VP_INT_FS_FIELD) { 2232 drm_crtc_handle_vblank(crtc); 2233 spin_lock(&crtc->dev->event_lock); 2234 if (vp->event) { 2235 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2236 2237 if (!(val & BIT(vp->id))) { 2238 drm_crtc_send_vblank_event(crtc, vp->event); 2239 vp->event = NULL; 2240 drm_crtc_vblank_put(crtc); 2241 } 2242 } 2243 spin_unlock(&crtc->dev->event_lock); 2244 2245 ret = IRQ_HANDLED; 2246 } 2247 2248 if (irqs & VP_INT_POST_BUF_EMPTY) { 2249 drm_err_ratelimited(vop2->drm, 2250 "POST_BUF_EMPTY irq err at vp%d\n", 2251 vp->id); 2252 ret = IRQ_HANDLED; 2253 } 2254 } 2255 } 2256 2257 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); 2258 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); 2259 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); 2260 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); 2261 2262 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { 2263 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { 2264 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); 2265 ret = IRQ_HANDLED; 2266 } 2267 } 2268 2269 pm_runtime_put(vop2->dev); 2270 2271 return ret; 2272 } 2273 2274 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, 2275 unsigned long possible_crtcs) 2276 { 2277 const struct vop2_win_data *win_data = win->data; 2278 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2279 BIT(DRM_MODE_BLEND_PREMULTI) | 2280 BIT(DRM_MODE_BLEND_COVERAGE); 2281 int ret; 2282 2283 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, 2284 &vop2_plane_funcs, win_data->formats, 2285 win_data->nformats, 2286 win_data->format_modifiers, 2287 win->type, win_data->name); 2288 if (ret) { 2289 drm_err(vop2->drm, "failed to initialize plane %d\n", ret); 2290 return ret; 2291 } 2292 2293 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); 2294 2295 if (win->data->supported_rotations) 2296 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, 2297 DRM_MODE_ROTATE_0 | 2298 win->data->supported_rotations); 2299 drm_plane_create_alpha_property(&win->base); 2300 drm_plane_create_blend_mode_property(&win->base, blend_caps); 2301 drm_plane_create_zpos_property(&win->base, win->win_id, 0, 2302 vop2->registered_num_wins - 1); 2303 2304 return 0; 2305 } 2306 2307 /* 2308 * On RK3566 these windows don't have an independent 2309 * framebuffer. They can only share/mirror the framebuffer 2310 * with smart0, esmart0 and cluster0 respectively. 2311 * And RK3566 share the same vop version with Rk3568, so we 2312 * need to use soc_id for identification here. 2313 */ 2314 static bool vop2_is_mirror_win(struct vop2_win *win) 2315 { 2316 struct vop2 *vop2 = win->vop2; 2317 2318 if (vop2->data->soc_id == 3566) { 2319 switch (win->data->phys_id) { 2320 case ROCKCHIP_VOP2_SMART1: 2321 case ROCKCHIP_VOP2_ESMART1: 2322 case ROCKCHIP_VOP2_CLUSTER1: 2323 return true; 2324 default: 2325 return false; 2326 } 2327 } else { 2328 return false; 2329 } 2330 } 2331 2332 static int vop2_create_crtcs(struct vop2 *vop2) 2333 { 2334 const struct vop2_data *vop2_data = vop2->data; 2335 struct drm_device *drm = vop2->drm; 2336 struct device *dev = vop2->dev; 2337 struct drm_plane *plane; 2338 struct device_node *port; 2339 struct vop2_video_port *vp; 2340 struct vop2_win *win; 2341 u32 possible_crtcs; 2342 int i, j, nvp, nvps = 0; 2343 int ret; 2344 2345 for (i = 0; i < vop2_data->nr_vps; i++) { 2346 const struct vop2_video_port_data *vp_data; 2347 struct device_node *np; 2348 char dclk_name[9]; 2349 2350 vp_data = &vop2_data->vp[i]; 2351 vp = &vop2->vps[i]; 2352 vp->vop2 = vop2; 2353 vp->id = vp_data->id; 2354 vp->data = vp_data; 2355 2356 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); 2357 vp->dclk = devm_clk_get(vop2->dev, dclk_name); 2358 if (IS_ERR(vp->dclk)) 2359 return dev_err_probe(drm->dev, PTR_ERR(vp->dclk), 2360 "failed to get %s\n", dclk_name); 2361 2362 np = of_graph_get_remote_node(dev->of_node, i, -1); 2363 if (!np) { 2364 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); 2365 continue; 2366 } 2367 of_node_put(np); 2368 2369 port = of_graph_get_port_by_id(dev->of_node, i); 2370 if (!port) 2371 return dev_err_probe(drm->dev, -ENOENT, 2372 "no port node found for video_port%d\n", i); 2373 vp->crtc.port = port; 2374 nvps++; 2375 } 2376 2377 nvp = 0; 2378 /* Register a primary plane for every crtc */ 2379 for (i = 0; i < vop2_data->nr_vps; i++) { 2380 vp = &vop2->vps[i]; 2381 2382 if (!vp->crtc.port) 2383 continue; 2384 2385 for (j = 0; j < vop2->registered_num_wins; j++) { 2386 win = &vop2->win[j]; 2387 2388 /* Aready registered as primary plane */ 2389 if (win->base.type == DRM_PLANE_TYPE_PRIMARY) 2390 continue; 2391 2392 /* If this win can not attached to this VP */ 2393 if (!(win->data->possible_vp_mask & BIT(vp->id))) 2394 continue; 2395 2396 if (vop2_is_mirror_win(win)) 2397 continue; 2398 2399 if (win->type == DRM_PLANE_TYPE_PRIMARY) { 2400 possible_crtcs = BIT(nvp); 2401 vp->primary_plane = win; 2402 ret = vop2_plane_init(vop2, win, possible_crtcs); 2403 if (ret) 2404 return dev_err_probe(drm->dev, ret, 2405 "failed to init primary plane %s\n", 2406 win->data->name); 2407 nvp++; 2408 break; 2409 } 2410 } 2411 2412 if (!vp->primary_plane) 2413 return dev_err_probe(drm->dev, -ENOENT, 2414 "no primary plane for vp %d\n", i); 2415 } 2416 2417 /* Register all unused window as overlay plane */ 2418 for (i = 0; i < vop2->registered_num_wins; i++) { 2419 win = &vop2->win[i]; 2420 2421 /* Aready registered as primary plane */ 2422 if (win->base.type == DRM_PLANE_TYPE_PRIMARY) 2423 continue; 2424 2425 if (vop2_is_mirror_win(win)) 2426 continue; 2427 2428 win->type = DRM_PLANE_TYPE_OVERLAY; 2429 2430 possible_crtcs = 0; 2431 nvp = 0; 2432 for (j = 0; j < vop2_data->nr_vps; j++) { 2433 vp = &vop2->vps[j]; 2434 2435 if (!vp->crtc.port) 2436 continue; 2437 2438 if (win->data->possible_vp_mask & BIT(vp->id)) 2439 possible_crtcs |= BIT(nvp); 2440 nvp++; 2441 } 2442 2443 ret = vop2_plane_init(vop2, win, possible_crtcs); 2444 if (ret) 2445 return dev_err_probe(drm->dev, ret, "failed to init overlay plane %s\n", 2446 win->data->name); 2447 } 2448 2449 for (i = 0; i < vop2_data->nr_vps; i++) { 2450 vp = &vop2->vps[i]; 2451 2452 if (!vp->crtc.port) 2453 continue; 2454 2455 plane = &vp->primary_plane->base; 2456 2457 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, 2458 &vop2_crtc_funcs, 2459 "video_port%d", vp->id); 2460 if (ret) 2461 return dev_err_probe(drm->dev, ret, 2462 "crtc init for video_port%d failed\n", i); 2463 2464 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); 2465 if (vop2->lut_regs) { 2466 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 2467 2468 drm_mode_crtc_set_gamma_size(&vp->crtc, vp_data->gamma_lut_len); 2469 drm_crtc_enable_color_mgmt(&vp->crtc, 0, false, vp_data->gamma_lut_len); 2470 } 2471 init_completion(&vp->dsp_hold_completion); 2472 } 2473 2474 /* 2475 * On the VOP2 it's very hard to change the number of layers on a VP 2476 * during runtime, so we distribute the layers equally over the used 2477 * VPs 2478 */ 2479 for (i = 0; i < vop2->data->nr_vps; i++) { 2480 struct vop2_video_port *vp = &vop2->vps[i]; 2481 2482 if (vp->crtc.port) 2483 vp->nlayers = vop2_data->win_size / nvps; 2484 } 2485 2486 return 0; 2487 } 2488 2489 static void vop2_destroy_crtcs(struct vop2 *vop2) 2490 { 2491 struct drm_device *drm = vop2->drm; 2492 struct list_head *crtc_list = &drm->mode_config.crtc_list; 2493 struct list_head *plane_list = &drm->mode_config.plane_list; 2494 struct drm_crtc *crtc, *tmpc; 2495 struct drm_plane *plane, *tmpp; 2496 2497 list_for_each_entry_safe(plane, tmpp, plane_list, head) 2498 drm_plane_cleanup(plane); 2499 2500 /* 2501 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() 2502 * references the CRTC. 2503 */ 2504 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) { 2505 of_node_put(crtc->port); 2506 drm_crtc_cleanup(crtc); 2507 } 2508 } 2509 2510 static int vop2_find_rgb_encoder(struct vop2 *vop2) 2511 { 2512 struct device_node *node = vop2->dev->of_node; 2513 struct device_node *endpoint; 2514 int i; 2515 2516 for (i = 0; i < vop2->data->nr_vps; i++) { 2517 endpoint = of_graph_get_endpoint_by_regs(node, i, 2518 ROCKCHIP_VOP2_EP_RGB0); 2519 if (!endpoint) 2520 continue; 2521 2522 of_node_put(endpoint); 2523 return i; 2524 } 2525 2526 return -ENOENT; 2527 } 2528 2529 static int vop2_regmap_init(struct vop2_win *win, const struct reg_field *regs, 2530 int nr_regs) 2531 { 2532 struct vop2 *vop2 = win->vop2; 2533 int i; 2534 2535 for (i = 0; i < nr_regs; i++) { 2536 const struct reg_field field = { 2537 .reg = (regs[i].reg != 0xffffffff) ? 2538 regs[i].reg + win->offset : regs[i].reg, 2539 .lsb = regs[i].lsb, 2540 .msb = regs[i].msb 2541 }; 2542 2543 win->reg[i] = devm_regmap_field_alloc(vop2->dev, vop2->map, field); 2544 if (IS_ERR(win->reg[i])) 2545 return PTR_ERR(win->reg[i]); 2546 } 2547 2548 return 0; 2549 }; 2550 2551 static int vop2_win_init(struct vop2 *vop2) 2552 { 2553 const struct vop2_data *vop2_data = vop2->data; 2554 struct vop2_win *win; 2555 int i, ret; 2556 2557 for (i = 0; i < vop2_data->win_size; i++) { 2558 const struct vop2_win_data *win_data = &vop2_data->win[i]; 2559 2560 win = &vop2->win[i]; 2561 win->data = win_data; 2562 win->type = win_data->type; 2563 win->offset = win_data->base; 2564 win->win_id = i; 2565 win->vop2 = vop2; 2566 if (vop2_cluster_window(win)) 2567 ret = vop2_regmap_init(win, vop2->data->cluster_reg, 2568 vop2->data->nr_cluster_regs); 2569 else 2570 ret = vop2_regmap_init(win, vop2->data->smart_reg, 2571 vop2->data->nr_smart_regs); 2572 if (ret) 2573 return ret; 2574 } 2575 2576 vop2->registered_num_wins = vop2_data->win_size; 2577 2578 return 0; 2579 } 2580 2581 /* 2582 * The window registers are only updated when config done is written. 2583 * Until that they read back the old value. As we read-modify-write 2584 * these registers mark them as non-volatile. This makes sure we read 2585 * the new values from the regmap register cache. 2586 */ 2587 static const struct regmap_range vop2_nonvolatile_range[] = { 2588 regmap_reg_range(0x1000, 0x23ff), 2589 }; 2590 2591 static const struct regmap_access_table vop2_volatile_table = { 2592 .no_ranges = vop2_nonvolatile_range, 2593 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), 2594 }; 2595 2596 static const struct regmap_config vop2_regmap_config = { 2597 .reg_bits = 32, 2598 .val_bits = 32, 2599 .reg_stride = 4, 2600 .max_register = 0x3000, 2601 .name = "vop2", 2602 .volatile_table = &vop2_volatile_table, 2603 .cache_type = REGCACHE_MAPLE, 2604 }; 2605 2606 static int vop2_bind(struct device *dev, struct device *master, void *data) 2607 { 2608 struct platform_device *pdev = to_platform_device(dev); 2609 const struct vop2_data *vop2_data; 2610 struct drm_device *drm = data; 2611 struct vop2 *vop2; 2612 struct resource *res; 2613 size_t alloc_size; 2614 int ret; 2615 2616 vop2_data = of_device_get_match_data(dev); 2617 if (!vop2_data) 2618 return -ENODEV; 2619 2620 /* Allocate vop2 struct and its vop2_win array */ 2621 alloc_size = struct_size(vop2, win, vop2_data->win_size); 2622 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 2623 if (!vop2) 2624 return -ENOMEM; 2625 2626 vop2->dev = dev; 2627 vop2->data = vop2_data; 2628 vop2->ops = vop2_data->ops; 2629 vop2->version = vop2_data->version; 2630 vop2->drm = drm; 2631 2632 dev_set_drvdata(dev, vop2); 2633 2634 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop"); 2635 if (!res) 2636 return dev_err_probe(drm->dev, -EINVAL, 2637 "failed to get vop2 register byname\n"); 2638 2639 vop2->res = res; 2640 vop2->regs = devm_ioremap_resource(dev, res); 2641 if (IS_ERR(vop2->regs)) 2642 return PTR_ERR(vop2->regs); 2643 vop2->len = resource_size(res); 2644 2645 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); 2646 if (IS_ERR(vop2->map)) 2647 return PTR_ERR(vop2->map); 2648 2649 ret = vop2_win_init(vop2); 2650 if (ret) 2651 return ret; 2652 2653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut"); 2654 if (res) { 2655 vop2->lut_regs = devm_ioremap_resource(dev, res); 2656 if (IS_ERR(vop2->lut_regs)) 2657 return PTR_ERR(vop2->lut_regs); 2658 } 2659 if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_GRF) { 2660 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 2661 if (IS_ERR(vop2->sys_grf)) 2662 return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_grf), 2663 "cannot get sys_grf\n"); 2664 } 2665 2666 if (vop2_data->feature & VOP2_FEATURE_HAS_VOP_GRF) { 2667 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); 2668 if (IS_ERR(vop2->vop_grf)) 2669 return dev_err_probe(drm->dev, PTR_ERR(vop2->vop_grf), 2670 "cannot get vop_grf\n"); 2671 } 2672 2673 if (vop2_data->feature & VOP2_FEATURE_HAS_VO1_GRF) { 2674 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); 2675 if (IS_ERR(vop2->vo1_grf)) 2676 return dev_err_probe(drm->dev, PTR_ERR(vop2->vo1_grf), 2677 "cannot get vo1_grf\n"); 2678 } 2679 2680 if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_PMU) { 2681 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); 2682 if (IS_ERR(vop2->sys_pmu)) 2683 return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_pmu), 2684 "cannot get sys_pmu\n"); 2685 } 2686 2687 vop2->hclk = devm_clk_get(vop2->dev, "hclk"); 2688 if (IS_ERR(vop2->hclk)) 2689 return dev_err_probe(drm->dev, PTR_ERR(vop2->hclk), 2690 "failed to get hclk source\n"); 2691 2692 vop2->aclk = devm_clk_get(vop2->dev, "aclk"); 2693 if (IS_ERR(vop2->aclk)) 2694 return dev_err_probe(drm->dev, PTR_ERR(vop2->aclk), 2695 "failed to get aclk source\n"); 2696 2697 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); 2698 if (IS_ERR(vop2->pclk)) 2699 return dev_err_probe(drm->dev, PTR_ERR(vop2->pclk), 2700 "failed to get pclk source\n"); 2701 2702 vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0"); 2703 if (IS_ERR(vop2->pll_hdmiphy0)) 2704 return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy0), 2705 "failed to get pll_hdmiphy0\n"); 2706 2707 vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); 2708 if (IS_ERR(vop2->pll_hdmiphy1)) 2709 return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy1), 2710 "failed to get pll_hdmiphy1\n"); 2711 2712 vop2->irq = platform_get_irq(pdev, 0); 2713 if (vop2->irq < 0) 2714 return dev_err_probe(drm->dev, vop2->irq, "cannot find irq for vop2\n"); 2715 2716 mutex_init(&vop2->vop2_lock); 2717 mutex_init(&vop2->ovl_lock); 2718 2719 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); 2720 if (ret) 2721 return ret; 2722 2723 ret = vop2_create_crtcs(vop2); 2724 if (ret) 2725 return ret; 2726 2727 if (vop2->version >= VOP_VERSION_RK3576) { 2728 struct drm_crtc *crtc; 2729 2730 drm_for_each_crtc(crtc, drm) { 2731 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2732 int vp_irq; 2733 const char *irq_name = devm_kasprintf(dev, GFP_KERNEL, "vp%d", vp->id); 2734 2735 if (!irq_name) 2736 return -ENOMEM; 2737 2738 vp_irq = platform_get_irq_byname(pdev, irq_name); 2739 if (vp_irq < 0) 2740 return dev_err_probe(drm->dev, vp_irq, 2741 "cannot find irq for vop2 vp%d\n", vp->id); 2742 2743 ret = devm_request_irq(dev, vp_irq, rk3576_vp_isr, IRQF_SHARED, irq_name, 2744 vp); 2745 if (ret) 2746 dev_err_probe(drm->dev, ret, 2747 "request irq for vop2 vp%d failed\n", vp->id); 2748 } 2749 } 2750 2751 ret = vop2_find_rgb_encoder(vop2); 2752 if (ret >= 0) { 2753 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, 2754 vop2->drm, ret); 2755 if (IS_ERR(vop2->rgb)) { 2756 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { 2757 ret = PTR_ERR(vop2->rgb); 2758 goto err_crtcs; 2759 } 2760 vop2->rgb = NULL; 2761 } 2762 } 2763 2764 rockchip_drm_dma_init_device(vop2->drm, vop2->dev); 2765 2766 pm_runtime_enable(&pdev->dev); 2767 2768 return 0; 2769 2770 err_crtcs: 2771 vop2_destroy_crtcs(vop2); 2772 2773 return ret; 2774 } 2775 2776 static void vop2_unbind(struct device *dev, struct device *master, void *data) 2777 { 2778 struct vop2 *vop2 = dev_get_drvdata(dev); 2779 2780 pm_runtime_disable(dev); 2781 2782 if (vop2->rgb) 2783 rockchip_rgb_fini(vop2->rgb); 2784 2785 vop2_destroy_crtcs(vop2); 2786 } 2787 2788 const struct component_ops vop2_component_ops = { 2789 .bind = vop2_bind, 2790 .unbind = vop2_unbind, 2791 }; 2792 EXPORT_SYMBOL_GPL(vop2_component_ops); 2793