1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/swab.h> 22 23 #include <drm/drm.h> 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_uapi.h> 26 #include <drm/drm_blend.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_debugfs.h> 30 #include <drm/drm_flip_work.h> 31 #include <drm/drm_framebuffer.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <uapi/linux/videodev2.h> 36 #include <dt-bindings/soc/rockchip,vop2.h> 37 38 #include "rockchip_drm_drv.h" 39 #include "rockchip_drm_gem.h" 40 #include "rockchip_drm_fb.h" 41 #include "rockchip_drm_vop2.h" 42 43 /* 44 * VOP2 architecture 45 * 46 +----------+ +-------------+ +-----------+ 47 | Cluster | | Sel 1 from 6| | 1 from 3 | 48 | window0 | | Layer0 | | RGB | 49 +----------+ +-------------+ +---------------+ +-------------+ +-----------+ 50 +----------+ +-------------+ |N from 6 layers| | | 51 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ 52 | window1 | | Layer1 | | | | | | 1 from 3 | 53 +----------+ +-------------+ +---------------+ +-------------+ | LVDS | 54 +----------+ +-------------+ +-----------+ 55 | Esmart | | Sel 1 from 6| 56 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ 57 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | 58 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | 59 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ 60 | Window1 | | Layer3 | +---------------+ +-------------+ 61 +----------+ +-------------+ +-----------+ 62 +----------+ +-------------+ | 1 from 3 | 63 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | 64 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ 65 +----------+ +-------------+ | Overlay2 +--->| Video Port2 | 66 +----------+ +-------------+ | | | | +-----------+ 67 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | 68 | Window1 | | Layer5 | | eDP | 69 +----------+ +-------------+ +-----------+ 70 * 71 */ 72 73 enum vop2_data_format { 74 VOP2_FMT_ARGB8888 = 0, 75 VOP2_FMT_RGB888, 76 VOP2_FMT_RGB565, 77 VOP2_FMT_XRGB101010, 78 VOP2_FMT_YUV420SP, 79 VOP2_FMT_YUV422SP, 80 VOP2_FMT_YUV444SP, 81 VOP2_FMT_YUYV422 = 8, 82 VOP2_FMT_YUYV420, 83 VOP2_FMT_VYUY422, 84 VOP2_FMT_VYUY420, 85 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, 86 VOP2_FMT_YUV420SP_TILE_16x2, 87 VOP2_FMT_YUV422SP_TILE_8x4, 88 VOP2_FMT_YUV422SP_TILE_16x2, 89 VOP2_FMT_YUV420SP_10, 90 VOP2_FMT_YUV422SP_10, 91 VOP2_FMT_YUV444SP_10, 92 }; 93 94 enum vop2_afbc_format { 95 VOP2_AFBC_FMT_RGB565, 96 VOP2_AFBC_FMT_ARGB2101010 = 2, 97 VOP2_AFBC_FMT_YUV420_10BIT, 98 VOP2_AFBC_FMT_RGB888, 99 VOP2_AFBC_FMT_ARGB8888, 100 VOP2_AFBC_FMT_YUV420 = 9, 101 VOP2_AFBC_FMT_YUV422 = 0xb, 102 VOP2_AFBC_FMT_YUV422_10BIT = 0xe, 103 VOP2_AFBC_FMT_INVALID = -1, 104 }; 105 106 union vop2_alpha_ctrl { 107 u32 val; 108 struct { 109 /* [0:1] */ 110 u32 color_mode:1; 111 u32 alpha_mode:1; 112 /* [2:3] */ 113 u32 blend_mode:2; 114 u32 alpha_cal_mode:1; 115 /* [5:7] */ 116 u32 factor_mode:3; 117 /* [8:9] */ 118 u32 alpha_en:1; 119 u32 src_dst_swap:1; 120 u32 reserved:6; 121 /* [16:23] */ 122 u32 glb_alpha:8; 123 } bits; 124 }; 125 126 struct vop2_alpha { 127 union vop2_alpha_ctrl src_color_ctrl; 128 union vop2_alpha_ctrl dst_color_ctrl; 129 union vop2_alpha_ctrl src_alpha_ctrl; 130 union vop2_alpha_ctrl dst_alpha_ctrl; 131 }; 132 133 struct vop2_alpha_config { 134 bool src_premulti_en; 135 bool dst_premulti_en; 136 bool src_pixel_alpha_en; 137 bool dst_pixel_alpha_en; 138 u16 src_glb_alpha_value; 139 u16 dst_glb_alpha_value; 140 }; 141 142 struct vop2_win { 143 struct vop2 *vop2; 144 struct drm_plane base; 145 const struct vop2_win_data *data; 146 struct regmap_field *reg[VOP2_WIN_MAX_REG]; 147 148 /** 149 * @win_id: graphic window id, a cluster may be split into two 150 * graphics windows. 151 */ 152 u8 win_id; 153 u8 delay; 154 u32 offset; 155 156 enum drm_plane_type type; 157 }; 158 159 struct vop2_video_port { 160 struct drm_crtc crtc; 161 struct vop2 *vop2; 162 struct clk *dclk; 163 unsigned int id; 164 const struct vop2_video_port_regs *regs; 165 const struct vop2_video_port_data *data; 166 167 struct completion dsp_hold_completion; 168 169 /** 170 * @win_mask: Bitmask of windows attached to the video port; 171 */ 172 u32 win_mask; 173 174 struct vop2_win *primary_plane; 175 struct drm_pending_vblank_event *event; 176 177 unsigned int nlayers; 178 }; 179 180 struct vop2 { 181 struct device *dev; 182 struct drm_device *drm; 183 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; 184 185 const struct vop2_data *data; 186 /* 187 * Number of windows that are registered as plane, may be less than the 188 * total number of hardware windows. 189 */ 190 u32 registered_num_wins; 191 192 void __iomem *regs; 193 struct regmap *map; 194 195 struct regmap *grf; 196 197 /* physical map length of vop2 register */ 198 u32 len; 199 200 void __iomem *lut_regs; 201 202 /* protects crtc enable/disable */ 203 struct mutex vop2_lock; 204 205 int irq; 206 207 /* 208 * Some global resources are shared between all video ports(crtcs), so 209 * we need a ref counter here. 210 */ 211 unsigned int enable_count; 212 struct clk *hclk; 213 struct clk *aclk; 214 215 /* must be put at the end of the struct */ 216 struct vop2_win win[]; 217 }; 218 219 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) 220 { 221 return container_of(crtc, struct vop2_video_port, crtc); 222 } 223 224 static struct vop2_win *to_vop2_win(struct drm_plane *p) 225 { 226 return container_of(p, struct vop2_win, base); 227 } 228 229 static void vop2_lock(struct vop2 *vop2) 230 { 231 mutex_lock(&vop2->vop2_lock); 232 } 233 234 static void vop2_unlock(struct vop2 *vop2) 235 { 236 mutex_unlock(&vop2->vop2_lock); 237 } 238 239 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 240 { 241 regmap_write(vop2->map, offset, v); 242 } 243 244 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) 245 { 246 regmap_write(vp->vop2->map, vp->data->offset + offset, v); 247 } 248 249 static u32 vop2_readl(struct vop2 *vop2, u32 offset) 250 { 251 u32 val; 252 253 regmap_read(vop2->map, offset, &val); 254 255 return val; 256 } 257 258 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) 259 { 260 regmap_field_write(win->reg[reg], v); 261 } 262 263 static bool vop2_cluster_window(const struct vop2_win *win) 264 { 265 return win->data->feature & WIN_FEATURE_CLUSTER; 266 } 267 268 static void vop2_cfg_done(struct vop2_video_port *vp) 269 { 270 struct vop2 *vop2 = vp->vop2; 271 272 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, 273 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 274 } 275 276 static void vop2_win_disable(struct vop2_win *win) 277 { 278 vop2_win_write(win, VOP2_WIN_ENABLE, 0); 279 280 if (vop2_cluster_window(win)) 281 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); 282 } 283 284 static enum vop2_data_format vop2_convert_format(u32 format) 285 { 286 switch (format) { 287 case DRM_FORMAT_XRGB8888: 288 case DRM_FORMAT_ARGB8888: 289 case DRM_FORMAT_XBGR8888: 290 case DRM_FORMAT_ABGR8888: 291 return VOP2_FMT_ARGB8888; 292 case DRM_FORMAT_RGB888: 293 case DRM_FORMAT_BGR888: 294 return VOP2_FMT_RGB888; 295 case DRM_FORMAT_RGB565: 296 case DRM_FORMAT_BGR565: 297 return VOP2_FMT_RGB565; 298 case DRM_FORMAT_NV12: 299 return VOP2_FMT_YUV420SP; 300 case DRM_FORMAT_NV16: 301 return VOP2_FMT_YUV422SP; 302 case DRM_FORMAT_NV24: 303 return VOP2_FMT_YUV444SP; 304 case DRM_FORMAT_YUYV: 305 case DRM_FORMAT_YVYU: 306 return VOP2_FMT_VYUY422; 307 case DRM_FORMAT_VYUY: 308 case DRM_FORMAT_UYVY: 309 return VOP2_FMT_YUYV422; 310 default: 311 DRM_ERROR("unsupported format[%08x]\n", format); 312 return -EINVAL; 313 } 314 } 315 316 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) 317 { 318 switch (format) { 319 case DRM_FORMAT_XRGB8888: 320 case DRM_FORMAT_ARGB8888: 321 case DRM_FORMAT_XBGR8888: 322 case DRM_FORMAT_ABGR8888: 323 return VOP2_AFBC_FMT_ARGB8888; 324 case DRM_FORMAT_RGB888: 325 case DRM_FORMAT_BGR888: 326 return VOP2_AFBC_FMT_RGB888; 327 case DRM_FORMAT_RGB565: 328 case DRM_FORMAT_BGR565: 329 return VOP2_AFBC_FMT_RGB565; 330 case DRM_FORMAT_NV12: 331 return VOP2_AFBC_FMT_YUV420; 332 case DRM_FORMAT_NV16: 333 return VOP2_AFBC_FMT_YUV422; 334 default: 335 return VOP2_AFBC_FMT_INVALID; 336 } 337 338 return VOP2_AFBC_FMT_INVALID; 339 } 340 341 static bool vop2_win_rb_swap(u32 format) 342 { 343 switch (format) { 344 case DRM_FORMAT_XBGR8888: 345 case DRM_FORMAT_ABGR8888: 346 case DRM_FORMAT_BGR888: 347 case DRM_FORMAT_BGR565: 348 return true; 349 default: 350 return false; 351 } 352 } 353 354 static bool vop2_afbc_rb_swap(u32 format) 355 { 356 switch (format) { 357 case DRM_FORMAT_NV24: 358 return true; 359 default: 360 return false; 361 } 362 } 363 364 static bool vop2_afbc_uv_swap(u32 format) 365 { 366 switch (format) { 367 case DRM_FORMAT_NV12: 368 case DRM_FORMAT_NV16: 369 return true; 370 default: 371 return false; 372 } 373 } 374 375 static bool vop2_win_uv_swap(u32 format) 376 { 377 switch (format) { 378 case DRM_FORMAT_NV12: 379 case DRM_FORMAT_NV16: 380 case DRM_FORMAT_NV24: 381 return true; 382 default: 383 return false; 384 } 385 } 386 387 static bool vop2_win_dither_up(u32 format) 388 { 389 switch (format) { 390 case DRM_FORMAT_BGR565: 391 case DRM_FORMAT_RGB565: 392 return true; 393 default: 394 return false; 395 } 396 } 397 398 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) 399 { 400 /* 401 * FIXME: 402 * 403 * There is no media type for YUV444 output, 404 * so when out_mode is AAAA or P888, assume output is YUV444 on 405 * yuv format. 406 * 407 * From H/W testing, YUV444 mode need a rb swap. 408 */ 409 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 410 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 411 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 412 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 413 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 414 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 415 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 416 output_mode == ROCKCHIP_OUT_MODE_P888))) 417 return true; 418 else 419 return false; 420 } 421 422 static bool is_yuv_output(u32 bus_format) 423 { 424 switch (bus_format) { 425 case MEDIA_BUS_FMT_YUV8_1X24: 426 case MEDIA_BUS_FMT_YUV10_1X30: 427 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 428 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 429 case MEDIA_BUS_FMT_YUYV8_2X8: 430 case MEDIA_BUS_FMT_YVYU8_2X8: 431 case MEDIA_BUS_FMT_UYVY8_2X8: 432 case MEDIA_BUS_FMT_VYUY8_2X8: 433 case MEDIA_BUS_FMT_YUYV8_1X16: 434 case MEDIA_BUS_FMT_YVYU8_1X16: 435 case MEDIA_BUS_FMT_UYVY8_1X16: 436 case MEDIA_BUS_FMT_VYUY8_1X16: 437 return true; 438 default: 439 return false; 440 } 441 } 442 443 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) 444 { 445 int i; 446 447 if (modifier == DRM_FORMAT_MOD_LINEAR) 448 return false; 449 450 for (i = 0 ; i < plane->modifier_count; i++) 451 if (plane->modifiers[i] == modifier) 452 return true; 453 454 return false; 455 } 456 457 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, 458 u64 modifier) 459 { 460 struct vop2_win *win = to_vop2_win(plane); 461 struct vop2 *vop2 = win->vop2; 462 463 if (modifier == DRM_FORMAT_MOD_INVALID) 464 return false; 465 466 if (modifier == DRM_FORMAT_MOD_LINEAR) 467 return true; 468 469 if (!rockchip_afbc(plane, modifier)) { 470 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", 471 modifier); 472 473 return false; 474 } 475 476 return vop2_convert_afbc_format(format) >= 0; 477 } 478 479 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, 480 bool afbc_half_block_en) 481 { 482 struct drm_rect *src = &pstate->src; 483 struct drm_framebuffer *fb = pstate->fb; 484 u32 bpp = fb->format->cpp[0] * 8; 485 u32 vir_width = (fb->pitches[0] << 3) / bpp; 486 u32 width = drm_rect_width(src) >> 16; 487 u32 height = drm_rect_height(src) >> 16; 488 u32 act_xoffset = src->x1 >> 16; 489 u32 act_yoffset = src->y1 >> 16; 490 u32 align16_crop = 0; 491 u32 align64_crop = 0; 492 u32 height_tmp; 493 u8 tx, ty; 494 u8 bottom_crop_line_num = 0; 495 496 /* 16 pixel align */ 497 if (height & 0xf) 498 align16_crop = 16 - (height & 0xf); 499 500 height_tmp = height + align16_crop; 501 502 /* 64 pixel align */ 503 if (height_tmp & 0x3f) 504 align64_crop = 64 - (height_tmp & 0x3f); 505 506 bottom_crop_line_num = align16_crop + align64_crop; 507 508 switch (pstate->rotation & 509 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | 510 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { 511 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: 512 tx = 16 - ((act_xoffset + width) & 0xf); 513 ty = bottom_crop_line_num - act_yoffset; 514 break; 515 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: 516 tx = bottom_crop_line_num - act_yoffset; 517 ty = vir_width - width - act_xoffset; 518 break; 519 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: 520 tx = act_yoffset; 521 ty = act_xoffset; 522 break; 523 case DRM_MODE_REFLECT_X: 524 tx = 16 - ((act_xoffset + width) & 0xf); 525 ty = act_yoffset; 526 break; 527 case DRM_MODE_REFLECT_Y: 528 tx = act_xoffset; 529 ty = bottom_crop_line_num - act_yoffset; 530 break; 531 case DRM_MODE_ROTATE_90: 532 tx = bottom_crop_line_num - act_yoffset; 533 ty = act_xoffset; 534 break; 535 case DRM_MODE_ROTATE_270: 536 tx = act_yoffset; 537 ty = vir_width - width - act_xoffset; 538 break; 539 case 0: 540 tx = act_xoffset; 541 ty = act_yoffset; 542 break; 543 } 544 545 if (afbc_half_block_en) 546 ty &= 0x7f; 547 548 #define TRANSFORM_XOFFSET GENMASK(7, 0) 549 #define TRANSFORM_YOFFSET GENMASK(23, 16) 550 return FIELD_PREP(TRANSFORM_XOFFSET, tx) | 551 FIELD_PREP(TRANSFORM_YOFFSET, ty); 552 } 553 554 /* 555 * A Cluster window has 2048 x 16 line buffer, which can 556 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. 557 * for Cluster_lb_mode register: 558 * 0: half mode, for plane input width range 2048 ~ 4096 559 * 1: half mode, for cluster work at 2 * 2048 plane mode 560 * 2: half mode, for rotate_90/270 mode 561 * 562 */ 563 static int vop2_get_cluster_lb_mode(struct vop2_win *win, 564 struct drm_plane_state *pstate) 565 { 566 if ((pstate->rotation & DRM_MODE_ROTATE_270) || 567 (pstate->rotation & DRM_MODE_ROTATE_90)) 568 return 2; 569 else 570 return 0; 571 } 572 573 static u16 vop2_scale_factor(u32 src, u32 dst) 574 { 575 u32 fac; 576 int shift; 577 578 if (src == dst) 579 return 0; 580 581 if (dst < 2) 582 return U16_MAX; 583 584 if (src < 2) 585 return 0; 586 587 if (src > dst) 588 shift = 12; 589 else 590 shift = 16; 591 592 src--; 593 dst--; 594 595 fac = DIV_ROUND_UP(src << shift, dst) - 1; 596 597 if (fac > U16_MAX) 598 return U16_MAX; 599 600 return fac; 601 } 602 603 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, 604 u32 src_w, u32 src_h, u32 dst_w, 605 u32 dst_h, u32 pixel_format) 606 { 607 const struct drm_format_info *info; 608 u16 hor_scl_mode, ver_scl_mode; 609 u16 hscl_filter_mode, vscl_filter_mode; 610 u8 gt2 = 0; 611 u8 gt4 = 0; 612 u32 val; 613 614 info = drm_format_info(pixel_format); 615 616 if (src_h >= (4 * dst_h)) { 617 gt4 = 1; 618 src_h >>= 2; 619 } else if (src_h >= (2 * dst_h)) { 620 gt2 = 1; 621 src_h >>= 1; 622 } 623 624 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 625 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 626 627 if (hor_scl_mode == SCALE_UP) 628 hscl_filter_mode = VOP2_SCALE_UP_BIC; 629 else 630 hscl_filter_mode = VOP2_SCALE_DOWN_BIL; 631 632 if (ver_scl_mode == SCALE_UP) 633 vscl_filter_mode = VOP2_SCALE_UP_BIL; 634 else 635 vscl_filter_mode = VOP2_SCALE_DOWN_BIL; 636 637 /* 638 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 639 * at scale down mode 640 */ 641 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 642 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 643 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", 644 win->data->name, dst_w); 645 dst_w++; 646 } 647 } 648 649 val = vop2_scale_factor(src_w, dst_w); 650 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); 651 val = vop2_scale_factor(src_h, dst_h); 652 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); 653 654 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); 655 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); 656 657 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); 658 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); 659 660 if (vop2_cluster_window(win)) 661 return; 662 663 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); 664 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); 665 666 if (info->is_yuv) { 667 src_w /= info->hsub; 668 src_h /= info->vsub; 669 670 gt4 = 0; 671 gt2 = 0; 672 673 if (src_h >= (4 * dst_h)) { 674 gt4 = 1; 675 src_h >>= 2; 676 } else if (src_h >= (2 * dst_h)) { 677 gt2 = 1; 678 src_h >>= 1; 679 } 680 681 hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 682 ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 683 684 val = vop2_scale_factor(src_w, dst_w); 685 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); 686 687 val = vop2_scale_factor(src_h, dst_h); 688 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); 689 690 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); 691 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); 692 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); 693 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); 694 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); 695 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); 696 } 697 } 698 699 static int vop2_convert_csc_mode(int csc_mode) 700 { 701 switch (csc_mode) { 702 case V4L2_COLORSPACE_SMPTE170M: 703 case V4L2_COLORSPACE_470_SYSTEM_M: 704 case V4L2_COLORSPACE_470_SYSTEM_BG: 705 return CSC_BT601L; 706 case V4L2_COLORSPACE_REC709: 707 case V4L2_COLORSPACE_SMPTE240M: 708 case V4L2_COLORSPACE_DEFAULT: 709 return CSC_BT709L; 710 case V4L2_COLORSPACE_JPEG: 711 return CSC_BT601F; 712 case V4L2_COLORSPACE_BT2020: 713 return CSC_BT2020; 714 default: 715 return CSC_BT709L; 716 } 717 } 718 719 /* 720 * colorspace path: 721 * Input Win csc Output 722 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) 723 * RGB --> R2Y __/ 724 * 725 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) 726 * RGB --> 709To2020->R2Y __/ 727 * 728 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) 729 * RGB --> R2Y __/ 730 * 731 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) 732 * RGB --> 709To2020->R2Y __/ 733 * 734 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) 735 * RGB --> R2Y __/ 736 * 737 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) 738 * RGB --> R2Y(601) __/ 739 * 740 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) 741 * RGB --> bypass __/ 742 * 743 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) 744 * 745 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) 746 * 747 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) 748 * 749 * 11. RGB --> bypass --> RGB_OUTPUT(709) 750 */ 751 752 static void vop2_setup_csc_mode(struct vop2_video_port *vp, 753 struct vop2_win *win, 754 struct drm_plane_state *pstate) 755 { 756 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); 757 int is_input_yuv = pstate->fb->format->is_yuv; 758 int is_output_yuv = is_yuv_output(vcstate->bus_format); 759 int input_csc = V4L2_COLORSPACE_DEFAULT; 760 int output_csc = vcstate->color_space; 761 bool r2y_en, y2r_en; 762 int csc_mode; 763 764 if (is_input_yuv && !is_output_yuv) { 765 y2r_en = true; 766 r2y_en = false; 767 csc_mode = vop2_convert_csc_mode(input_csc); 768 } else if (!is_input_yuv && is_output_yuv) { 769 y2r_en = false; 770 r2y_en = true; 771 csc_mode = vop2_convert_csc_mode(output_csc); 772 } else { 773 y2r_en = false; 774 r2y_en = false; 775 csc_mode = false; 776 } 777 778 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); 779 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); 780 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); 781 } 782 783 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) 784 { 785 struct vop2 *vop2 = vp->vop2; 786 787 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); 788 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); 789 } 790 791 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) 792 { 793 struct vop2 *vop2 = vp->vop2; 794 795 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); 796 } 797 798 static int vop2_core_clks_prepare_enable(struct vop2 *vop2) 799 { 800 int ret; 801 802 ret = clk_prepare_enable(vop2->hclk); 803 if (ret < 0) { 804 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); 805 return ret; 806 } 807 808 ret = clk_prepare_enable(vop2->aclk); 809 if (ret < 0) { 810 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); 811 goto err; 812 } 813 814 return 0; 815 err: 816 clk_disable_unprepare(vop2->hclk); 817 818 return ret; 819 } 820 821 static void vop2_enable(struct vop2 *vop2) 822 { 823 int ret; 824 825 ret = pm_runtime_resume_and_get(vop2->dev); 826 if (ret < 0) { 827 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); 828 return; 829 } 830 831 ret = vop2_core_clks_prepare_enable(vop2); 832 if (ret) { 833 pm_runtime_put_sync(vop2->dev); 834 return; 835 } 836 837 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); 838 if (ret) { 839 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); 840 return; 841 } 842 843 if (vop2->data->soc_id == 3566) 844 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); 845 846 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); 847 848 /* 849 * Disable auto gating, this is a workaround to 850 * avoid display image shift when a window enabled. 851 */ 852 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, 853 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); 854 855 vop2_writel(vop2, RK3568_SYS0_INT_CLR, 856 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 857 vop2_writel(vop2, RK3568_SYS0_INT_EN, 858 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 859 vop2_writel(vop2, RK3568_SYS1_INT_CLR, 860 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 861 vop2_writel(vop2, RK3568_SYS1_INT_EN, 862 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); 863 } 864 865 static void vop2_disable(struct vop2 *vop2) 866 { 867 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); 868 869 pm_runtime_put_sync(vop2->dev); 870 871 clk_disable_unprepare(vop2->aclk); 872 clk_disable_unprepare(vop2->hclk); 873 } 874 875 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, 876 struct drm_atomic_state *state) 877 { 878 struct vop2_video_port *vp = to_vop2_video_port(crtc); 879 struct vop2 *vop2 = vp->vop2; 880 struct drm_crtc_state *old_crtc_state; 881 int ret; 882 883 vop2_lock(vop2); 884 885 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 886 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); 887 888 drm_crtc_vblank_off(crtc); 889 890 /* 891 * Vop standby will take effect at end of current frame, 892 * if dsp hold valid irq happen, it means standby complete. 893 * 894 * we must wait standby complete when we want to disable aclk, 895 * if not, memory bus maybe dead. 896 */ 897 reinit_completion(&vp->dsp_hold_completion); 898 899 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); 900 901 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); 902 903 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, 904 msecs_to_jiffies(50)); 905 if (!ret) 906 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); 907 908 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); 909 910 clk_disable_unprepare(vp->dclk); 911 912 vop2->enable_count--; 913 914 if (!vop2->enable_count) 915 vop2_disable(vop2); 916 917 vop2_unlock(vop2); 918 919 if (crtc->state->event && !crtc->state->active) { 920 spin_lock_irq(&crtc->dev->event_lock); 921 drm_crtc_send_vblank_event(crtc, crtc->state->event); 922 spin_unlock_irq(&crtc->dev->event_lock); 923 924 crtc->state->event = NULL; 925 } 926 } 927 928 static int vop2_plane_atomic_check(struct drm_plane *plane, 929 struct drm_atomic_state *astate) 930 { 931 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); 932 struct drm_framebuffer *fb = pstate->fb; 933 struct drm_crtc *crtc = pstate->crtc; 934 struct drm_crtc_state *cstate; 935 struct vop2_video_port *vp; 936 struct vop2 *vop2; 937 const struct vop2_data *vop2_data; 938 struct drm_rect *dest = &pstate->dst; 939 struct drm_rect *src = &pstate->src; 940 int min_scale = FRAC_16_16(1, 8); 941 int max_scale = FRAC_16_16(8, 1); 942 int format; 943 int ret; 944 945 if (!crtc) 946 return 0; 947 948 vp = to_vop2_video_port(crtc); 949 vop2 = vp->vop2; 950 vop2_data = vop2->data; 951 952 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); 953 if (WARN_ON(!cstate)) 954 return -EINVAL; 955 956 ret = drm_atomic_helper_check_plane_state(pstate, cstate, 957 min_scale, max_scale, 958 true, true); 959 if (ret) 960 return ret; 961 962 if (!pstate->visible) 963 return 0; 964 965 format = vop2_convert_format(fb->format->format); 966 if (format < 0) 967 return format; 968 969 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || 970 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { 971 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", 972 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, 973 drm_rect_width(dest), drm_rect_height(dest)); 974 pstate->visible = false; 975 return 0; 976 } 977 978 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || 979 drm_rect_height(src) >> 16 > vop2_data->max_input.height) { 980 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", 981 drm_rect_width(src) >> 16, 982 drm_rect_height(src) >> 16, 983 vop2_data->max_input.width, 984 vop2_data->max_input.height); 985 return -EINVAL; 986 } 987 988 /* 989 * Src.x1 can be odd when do clip, but yuv plane start point 990 * need align with 2 pixel. 991 */ 992 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { 993 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); 994 return -EINVAL; 995 } 996 997 return 0; 998 } 999 1000 static void vop2_plane_atomic_disable(struct drm_plane *plane, 1001 struct drm_atomic_state *state) 1002 { 1003 struct drm_plane_state *old_pstate = NULL; 1004 struct vop2_win *win = to_vop2_win(plane); 1005 struct vop2 *vop2 = win->vop2; 1006 1007 drm_dbg(vop2->drm, "%s disable\n", win->data->name); 1008 1009 if (state) 1010 old_pstate = drm_atomic_get_old_plane_state(state, plane); 1011 if (old_pstate && !old_pstate->crtc) 1012 return; 1013 1014 vop2_win_disable(win); 1015 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); 1016 } 1017 1018 /* 1019 * The color key is 10 bit, so all format should 1020 * convert to 10 bit here. 1021 */ 1022 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) 1023 { 1024 struct drm_plane_state *pstate = plane->state; 1025 struct drm_framebuffer *fb = pstate->fb; 1026 struct vop2_win *win = to_vop2_win(plane); 1027 u32 color_key_en = 0; 1028 u32 r = 0; 1029 u32 g = 0; 1030 u32 b = 0; 1031 1032 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { 1033 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); 1034 return; 1035 } 1036 1037 switch (fb->format->format) { 1038 case DRM_FORMAT_RGB565: 1039 case DRM_FORMAT_BGR565: 1040 r = (color_key & 0xf800) >> 11; 1041 g = (color_key & 0x7e0) >> 5; 1042 b = (color_key & 0x1f); 1043 r <<= 5; 1044 g <<= 4; 1045 b <<= 5; 1046 color_key_en = 1; 1047 break; 1048 case DRM_FORMAT_XRGB8888: 1049 case DRM_FORMAT_ARGB8888: 1050 case DRM_FORMAT_XBGR8888: 1051 case DRM_FORMAT_ABGR8888: 1052 case DRM_FORMAT_RGB888: 1053 case DRM_FORMAT_BGR888: 1054 r = (color_key & 0xff0000) >> 16; 1055 g = (color_key & 0xff00) >> 8; 1056 b = (color_key & 0xff); 1057 r <<= 2; 1058 g <<= 2; 1059 b <<= 2; 1060 color_key_en = 1; 1061 break; 1062 } 1063 1064 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); 1065 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); 1066 } 1067 1068 static void vop2_plane_atomic_update(struct drm_plane *plane, 1069 struct drm_atomic_state *state) 1070 { 1071 struct drm_plane_state *pstate = plane->state; 1072 struct drm_crtc *crtc = pstate->crtc; 1073 struct vop2_win *win = to_vop2_win(plane); 1074 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1075 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1076 struct vop2 *vop2 = win->vop2; 1077 struct drm_framebuffer *fb = pstate->fb; 1078 u32 bpp = fb->format->cpp[0] * 8; 1079 u32 actual_w, actual_h, dsp_w, dsp_h; 1080 u32 act_info, dsp_info; 1081 u32 format; 1082 u32 afbc_format; 1083 u32 rb_swap; 1084 u32 uv_swap; 1085 struct drm_rect *src = &pstate->src; 1086 struct drm_rect *dest = &pstate->dst; 1087 u32 afbc_tile_num; 1088 u32 transform_offset; 1089 bool dither_up; 1090 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; 1091 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; 1092 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; 1093 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; 1094 struct rockchip_gem_object *rk_obj; 1095 unsigned long offset; 1096 bool afbc_en; 1097 dma_addr_t yrgb_mst; 1098 dma_addr_t uv_mst; 1099 1100 /* 1101 * can't update plane when vop2 is disabled. 1102 */ 1103 if (WARN_ON(!crtc)) 1104 return; 1105 1106 if (!pstate->visible) { 1107 vop2_plane_atomic_disable(plane, state); 1108 return; 1109 } 1110 1111 afbc_en = rockchip_afbc(plane, fb->modifier); 1112 1113 offset = (src->x1 >> 16) * fb->format->cpp[0]; 1114 1115 /* 1116 * AFBC HDR_PTR must set to the zero offset of the framebuffer. 1117 */ 1118 if (afbc_en) 1119 offset = 0; 1120 else if (pstate->rotation & DRM_MODE_REFLECT_Y) 1121 offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; 1122 else 1123 offset += (src->y1 >> 16) * fb->pitches[0]; 1124 1125 rk_obj = to_rockchip_obj(fb->obj[0]); 1126 1127 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 1128 if (fb->format->is_yuv) { 1129 int hsub = fb->format->hsub; 1130 int vsub = fb->format->vsub; 1131 1132 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; 1133 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 1134 1135 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) 1136 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; 1137 1138 rk_obj = to_rockchip_obj(fb->obj[0]); 1139 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; 1140 } 1141 1142 actual_w = drm_rect_width(src) >> 16; 1143 actual_h = drm_rect_height(src) >> 16; 1144 dsp_w = drm_rect_width(dest); 1145 1146 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { 1147 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", 1148 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); 1149 dsp_w = adjusted_mode->hdisplay - dest->x1; 1150 if (dsp_w < 4) 1151 dsp_w = 4; 1152 actual_w = dsp_w * actual_w / drm_rect_width(dest); 1153 } 1154 1155 dsp_h = drm_rect_height(dest); 1156 1157 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { 1158 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", 1159 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); 1160 dsp_h = adjusted_mode->vdisplay - dest->y1; 1161 if (dsp_h < 4) 1162 dsp_h = 4; 1163 actual_h = dsp_h * actual_h / drm_rect_height(dest); 1164 } 1165 1166 /* 1167 * This is workaround solution for IC design: 1168 * esmart can't support scale down when actual_w % 16 == 1. 1169 */ 1170 if (!(win->data->feature & WIN_FEATURE_AFBDC)) { 1171 if (actual_w > dsp_w && (actual_w & 0xf) == 1) { 1172 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", 1173 vp->id, win->data->name, actual_w); 1174 actual_w -= 1; 1175 } 1176 } 1177 1178 if (afbc_en && actual_w % 4) { 1179 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", 1180 vp->id, win->data->name, actual_w); 1181 actual_w = ALIGN_DOWN(actual_w, 4); 1182 } 1183 1184 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 1185 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); 1186 1187 format = vop2_convert_format(fb->format->format); 1188 1189 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", 1190 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, 1191 dest->x1, dest->y1, 1192 &fb->format->format, 1193 afbc_en ? "AFBC" : "", &yrgb_mst); 1194 1195 if (afbc_en) { 1196 u32 stride; 1197 1198 /* the afbc superblock is 16 x 16 */ 1199 afbc_format = vop2_convert_afbc_format(fb->format->format); 1200 1201 /* Enable color transform for YTR */ 1202 if (fb->modifier & AFBC_FORMAT_MOD_YTR) 1203 afbc_format |= (1 << 4); 1204 1205 afbc_tile_num = ALIGN(actual_w, 16) >> 4; 1206 1207 /* 1208 * AFBC pic_vir_width is count by pixel, this is different 1209 * with WIN_VIR_STRIDE. 1210 */ 1211 stride = (fb->pitches[0] << 3) / bpp; 1212 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) 1213 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", 1214 vp->id, win->data->name, stride); 1215 1216 rb_swap = vop2_afbc_rb_swap(fb->format->format); 1217 uv_swap = vop2_afbc_uv_swap(fb->format->format); 1218 /* 1219 * This is a workaround for crazy IC design, Cluster 1220 * and Esmart/Smart use different format configuration map: 1221 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. 1222 * 1223 * This is one thing we can make the convert simple: 1224 * AFBCD decode all the YUV data to YUV444. So we just 1225 * set all the yuv 10 bit to YUV444_10. 1226 */ 1227 if (fb->format->is_yuv && bpp == 10) 1228 format = VOP2_CLUSTER_YUV444_10; 1229 1230 if (vop2_cluster_window(win)) 1231 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); 1232 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); 1233 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); 1234 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); 1235 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); 1236 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); 1237 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { 1238 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); 1239 transform_offset = vop2_afbc_transform_offset(pstate, false); 1240 } else { 1241 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); 1242 transform_offset = vop2_afbc_transform_offset(pstate, true); 1243 } 1244 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); 1245 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); 1246 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); 1247 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); 1248 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); 1249 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); 1250 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); 1251 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); 1252 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); 1253 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); 1254 } else { 1255 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); 1256 } 1257 1258 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); 1259 1260 if (rotate_90 || rotate_270) { 1261 act_info = swahw32(act_info); 1262 actual_w = drm_rect_height(src) >> 16; 1263 actual_h = drm_rect_width(src) >> 16; 1264 } 1265 1266 vop2_win_write(win, VOP2_WIN_FORMAT, format); 1267 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); 1268 1269 rb_swap = vop2_win_rb_swap(fb->format->format); 1270 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); 1271 if (!vop2_cluster_window(win)) { 1272 uv_swap = vop2_win_uv_swap(fb->format->format); 1273 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); 1274 } 1275 1276 if (fb->format->is_yuv) { 1277 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); 1278 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); 1279 } 1280 1281 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); 1282 if (!vop2_cluster_window(win)) 1283 vop2_plane_setup_color_key(plane, 0); 1284 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); 1285 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); 1286 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); 1287 1288 vop2_setup_csc_mode(vp, win, pstate); 1289 1290 dither_up = vop2_win_dither_up(fb->format->format); 1291 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); 1292 1293 vop2_win_write(win, VOP2_WIN_ENABLE, 1); 1294 1295 if (vop2_cluster_window(win)) { 1296 int lb_mode = vop2_get_cluster_lb_mode(win, pstate); 1297 1298 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); 1299 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); 1300 } 1301 } 1302 1303 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { 1304 .atomic_check = vop2_plane_atomic_check, 1305 .atomic_update = vop2_plane_atomic_update, 1306 .atomic_disable = vop2_plane_atomic_disable, 1307 }; 1308 1309 static const struct drm_plane_funcs vop2_plane_funcs = { 1310 .update_plane = drm_atomic_helper_update_plane, 1311 .disable_plane = drm_atomic_helper_disable_plane, 1312 .destroy = drm_plane_cleanup, 1313 .reset = drm_atomic_helper_plane_reset, 1314 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1315 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1316 .format_mod_supported = rockchip_vop2_mod_supported, 1317 }; 1318 1319 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) 1320 { 1321 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1322 1323 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); 1324 1325 return 0; 1326 } 1327 1328 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) 1329 { 1330 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1331 1332 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); 1333 } 1334 1335 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, 1336 const struct drm_display_mode *mode, 1337 struct drm_display_mode *adj_mode) 1338 { 1339 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | 1340 CRTC_STEREO_DOUBLE); 1341 1342 return true; 1343 } 1344 1345 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) 1346 { 1347 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1348 1349 switch (vcstate->bus_format) { 1350 case MEDIA_BUS_FMT_RGB565_1X16: 1351 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1352 break; 1353 case MEDIA_BUS_FMT_RGB666_1X18: 1354 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1355 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1356 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; 1357 *dsp_ctrl |= RGB888_TO_RGB666; 1358 break; 1359 case MEDIA_BUS_FMT_YUV8_1X24: 1360 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1361 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1362 break; 1363 default: 1364 break; 1365 } 1366 1367 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) 1368 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; 1369 1370 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, 1371 DITHER_DOWN_ALLEGRO); 1372 } 1373 1374 static void vop2_post_config(struct drm_crtc *crtc) 1375 { 1376 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1377 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1378 u16 vtotal = mode->crtc_vtotal; 1379 u16 hdisplay = mode->crtc_hdisplay; 1380 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1381 u16 vdisplay = mode->crtc_vdisplay; 1382 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1383 u32 left_margin = 100, right_margin = 100; 1384 u32 top_margin = 100, bottom_margin = 100; 1385 u16 hsize = hdisplay * (left_margin + right_margin) / 200; 1386 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; 1387 u16 hact_end, vact_end; 1388 u32 val; 1389 1390 vsize = rounddown(vsize, 2); 1391 hsize = rounddown(hsize, 2); 1392 hact_st += hdisplay * (100 - left_margin) / 200; 1393 hact_end = hact_st + hsize; 1394 val = hact_st << 16; 1395 val |= hact_end; 1396 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); 1397 vact_st += vdisplay * (100 - top_margin) / 200; 1398 vact_end = vact_st + vsize; 1399 val = vact_st << 16; 1400 val |= vact_end; 1401 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); 1402 val = scl_cal_scale2(vdisplay, vsize) << 16; 1403 val |= scl_cal_scale2(hdisplay, hsize); 1404 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); 1405 1406 val = 0; 1407 if (hdisplay != hsize) 1408 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; 1409 if (vdisplay != vsize) 1410 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; 1411 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); 1412 1413 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1414 u16 vact_st_f1 = vtotal + vact_st + 1; 1415 u16 vact_end_f1 = vact_st_f1 + vsize; 1416 1417 val = vact_st_f1 << 16 | vact_end_f1; 1418 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); 1419 } 1420 1421 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); 1422 } 1423 1424 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, 1425 u32 polflags) 1426 { 1427 struct vop2 *vop2 = vp->vop2; 1428 u32 die, dip; 1429 1430 die = vop2_readl(vop2, RK3568_DSP_IF_EN); 1431 dip = vop2_readl(vop2, RK3568_DSP_IF_POL); 1432 1433 switch (id) { 1434 case ROCKCHIP_VOP2_EP_RGB0: 1435 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX; 1436 die |= RK3568_SYS_DSP_INFACE_EN_RGB | 1437 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); 1438 if (polflags & POLFLAG_DCLK_INV) 1439 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); 1440 else 1441 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); 1442 break; 1443 case ROCKCHIP_VOP2_EP_HDMI0: 1444 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; 1445 die |= RK3568_SYS_DSP_INFACE_EN_HDMI | 1446 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); 1447 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL; 1448 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags); 1449 break; 1450 case ROCKCHIP_VOP2_EP_EDP0: 1451 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; 1452 die |= RK3568_SYS_DSP_INFACE_EN_EDP | 1453 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); 1454 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL; 1455 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags); 1456 break; 1457 case ROCKCHIP_VOP2_EP_MIPI0: 1458 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; 1459 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 | 1460 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); 1461 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; 1462 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); 1463 break; 1464 case ROCKCHIP_VOP2_EP_MIPI1: 1465 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX; 1466 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 | 1467 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); 1468 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; 1469 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); 1470 break; 1471 case ROCKCHIP_VOP2_EP_LVDS0: 1472 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX; 1473 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 | 1474 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); 1475 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; 1476 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); 1477 break; 1478 case ROCKCHIP_VOP2_EP_LVDS1: 1479 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX; 1480 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 | 1481 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); 1482 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; 1483 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); 1484 break; 1485 default: 1486 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); 1487 return; 1488 } 1489 1490 dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; 1491 1492 vop2_writel(vop2, RK3568_DSP_IF_EN, die); 1493 vop2_writel(vop2, RK3568_DSP_IF_POL, dip); 1494 } 1495 1496 static int us_to_vertical_line(struct drm_display_mode *mode, int us) 1497 { 1498 return us * mode->clock / mode->htotal / 1000; 1499 } 1500 1501 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 1502 struct drm_atomic_state *state) 1503 { 1504 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1505 struct vop2 *vop2 = vp->vop2; 1506 const struct vop2_data *vop2_data = vop2->data; 1507 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; 1508 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1509 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 1510 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1511 unsigned long clock = mode->crtc_clock * 1000; 1512 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1513 u16 hdisplay = mode->crtc_hdisplay; 1514 u16 htotal = mode->crtc_htotal; 1515 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1516 u16 hact_end = hact_st + hdisplay; 1517 u16 vdisplay = mode->crtc_vdisplay; 1518 u16 vtotal = mode->crtc_vtotal; 1519 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1520 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1521 u16 vact_end = vact_st + vdisplay; 1522 u8 out_mode; 1523 u32 dsp_ctrl = 0; 1524 int act_end; 1525 u32 val, polflags; 1526 int ret; 1527 struct drm_encoder *encoder; 1528 1529 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", 1530 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1531 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); 1532 1533 vop2_lock(vop2); 1534 1535 ret = clk_prepare_enable(vp->dclk); 1536 if (ret < 0) { 1537 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", 1538 vp->id, ret); 1539 vop2_unlock(vop2); 1540 return; 1541 } 1542 1543 if (!vop2->enable_count) 1544 vop2_enable(vop2); 1545 1546 vop2->enable_count++; 1547 1548 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); 1549 1550 polflags = 0; 1551 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 1552 polflags |= POLFLAG_DCLK_INV; 1553 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1554 polflags |= BIT(HSYNC_POSITIVE); 1555 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1556 polflags |= BIT(VSYNC_POSITIVE); 1557 1558 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { 1559 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 1560 1561 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); 1562 } 1563 1564 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1565 !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 1566 out_mode = ROCKCHIP_OUT_MODE_P888; 1567 else 1568 out_mode = vcstate->output_mode; 1569 1570 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); 1571 1572 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) 1573 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; 1574 1575 if (is_yuv_output(vcstate->bus_format)) 1576 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; 1577 1578 vop2_dither_setup(crtc, &dsp_ctrl); 1579 1580 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); 1581 val = hact_st << 16; 1582 val |= hact_end; 1583 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); 1584 1585 val = vact_st << 16; 1586 val |= vact_end; 1587 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); 1588 1589 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1590 u16 vact_st_f1 = vtotal + vact_st + 1; 1591 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1592 1593 val = vact_st_f1 << 16 | vact_end_f1; 1594 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); 1595 1596 val = vtotal << 16 | (vtotal + vsync_len); 1597 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); 1598 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; 1599 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; 1600 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; 1601 vtotal += vtotal + 1; 1602 act_end = vact_end_f1; 1603 } else { 1604 act_end = vact_end; 1605 } 1606 1607 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), 1608 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); 1609 1610 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); 1611 1612 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1613 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; 1614 clock *= 2; 1615 } 1616 1617 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); 1618 1619 clk_set_rate(vp->dclk, clock); 1620 1621 vop2_post_config(crtc); 1622 1623 vop2_cfg_done(vp); 1624 1625 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); 1626 1627 drm_crtc_vblank_on(crtc); 1628 1629 vop2_unlock(vop2); 1630 } 1631 1632 static int vop2_crtc_atomic_check(struct drm_crtc *crtc, 1633 struct drm_atomic_state *state) 1634 { 1635 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1636 struct drm_plane *plane; 1637 int nplanes = 0; 1638 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1639 1640 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) 1641 nplanes++; 1642 1643 if (nplanes > vp->nlayers) 1644 return -EINVAL; 1645 1646 return 0; 1647 } 1648 1649 static bool is_opaque(u16 alpha) 1650 { 1651 return (alpha >> 8) == 0xff; 1652 } 1653 1654 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config, 1655 struct vop2_alpha *alpha) 1656 { 1657 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; 1658 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; 1659 int src_color_mode = alpha_config->src_premulti_en ? 1660 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; 1661 int dst_color_mode = alpha_config->dst_premulti_en ? 1662 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; 1663 1664 alpha->src_color_ctrl.val = 0; 1665 alpha->dst_color_ctrl.val = 0; 1666 alpha->src_alpha_ctrl.val = 0; 1667 alpha->dst_alpha_ctrl.val = 0; 1668 1669 if (!alpha_config->src_pixel_alpha_en) 1670 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; 1671 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en) 1672 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX; 1673 else 1674 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; 1675 1676 alpha->src_color_ctrl.bits.alpha_en = 1; 1677 1678 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) { 1679 alpha->src_color_ctrl.bits.color_mode = src_color_mode; 1680 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; 1681 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) { 1682 alpha->src_color_ctrl.bits.color_mode = src_color_mode; 1683 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE; 1684 } else { 1685 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL; 1686 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; 1687 } 1688 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8; 1689 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1690 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1691 1692 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1693 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1694 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; 1695 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8; 1696 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode; 1697 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; 1698 1699 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1700 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode; 1701 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; 1702 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE; 1703 1704 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; 1705 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en) 1706 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX; 1707 else 1708 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; 1709 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION; 1710 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; 1711 } 1712 1713 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) 1714 { 1715 struct vop2_video_port *vp; 1716 int used_layer = 0; 1717 int i; 1718 1719 for (i = 0; i < port_id; i++) { 1720 vp = &vop2->vps[i]; 1721 used_layer += hweight32(vp->win_mask); 1722 } 1723 1724 return used_layer; 1725 } 1726 1727 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) 1728 { 1729 u32 offset = (main_win->data->phys_id * 0x10); 1730 struct vop2_alpha_config alpha_config; 1731 struct vop2_alpha alpha; 1732 struct drm_plane_state *bottom_win_pstate; 1733 bool src_pixel_alpha_en = false; 1734 u16 src_glb_alpha_val, dst_glb_alpha_val; 1735 bool premulti_en = false; 1736 bool swap = false; 1737 1738 /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */ 1739 bottom_win_pstate = main_win->base.state; 1740 src_glb_alpha_val = 0; 1741 dst_glb_alpha_val = main_win->base.state->alpha; 1742 1743 if (!bottom_win_pstate->fb) 1744 return; 1745 1746 alpha_config.src_premulti_en = premulti_en; 1747 alpha_config.dst_premulti_en = false; 1748 alpha_config.src_pixel_alpha_en = src_pixel_alpha_en; 1749 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ 1750 alpha_config.src_glb_alpha_value = src_glb_alpha_val; 1751 alpha_config.dst_glb_alpha_value = dst_glb_alpha_val; 1752 vop2_parse_alpha(&alpha_config, &alpha); 1753 1754 alpha.src_color_ctrl.bits.src_dst_swap = swap; 1755 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, 1756 alpha.src_color_ctrl.val); 1757 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, 1758 alpha.dst_color_ctrl.val); 1759 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, 1760 alpha.src_alpha_ctrl.val); 1761 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, 1762 alpha.dst_alpha_ctrl.val); 1763 } 1764 1765 static void vop2_setup_alpha(struct vop2_video_port *vp) 1766 { 1767 struct vop2 *vop2 = vp->vop2; 1768 struct drm_framebuffer *fb; 1769 struct vop2_alpha_config alpha_config; 1770 struct vop2_alpha alpha; 1771 struct drm_plane *plane; 1772 int pixel_alpha_en; 1773 int premulti_en, gpremulti_en = 0; 1774 int mixer_id; 1775 u32 offset; 1776 bool bottom_layer_alpha_en = false; 1777 u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; 1778 1779 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); 1780 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ 1781 1782 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1783 struct vop2_win *win = to_vop2_win(plane); 1784 1785 if (plane->state->normalized_zpos == 0 && 1786 !is_opaque(plane->state->alpha) && 1787 !vop2_cluster_window(win)) { 1788 /* 1789 * If bottom layer have global alpha effect [except cluster layer, 1790 * because cluster have deal with bottom layer global alpha value 1791 * at cluster mix], bottom layer mix need deal with global alpha. 1792 */ 1793 bottom_layer_alpha_en = true; 1794 dst_global_alpha = plane->state->alpha; 1795 } 1796 } 1797 1798 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1799 struct vop2_win *win = to_vop2_win(plane); 1800 int zpos = plane->state->normalized_zpos; 1801 1802 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) 1803 premulti_en = 1; 1804 else 1805 premulti_en = 0; 1806 1807 plane = &win->base; 1808 fb = plane->state->fb; 1809 1810 pixel_alpha_en = fb->format->has_alpha; 1811 1812 alpha_config.src_premulti_en = premulti_en; 1813 1814 if (bottom_layer_alpha_en && zpos == 1) { 1815 gpremulti_en = premulti_en; 1816 /* Cd = Cs + (1 - As) * Cd * Agd */ 1817 alpha_config.dst_premulti_en = false; 1818 alpha_config.src_pixel_alpha_en = pixel_alpha_en; 1819 alpha_config.src_glb_alpha_value = plane->state->alpha; 1820 alpha_config.dst_glb_alpha_value = dst_global_alpha; 1821 } else if (vop2_cluster_window(win)) { 1822 /* Mix output data only have pixel alpha */ 1823 alpha_config.dst_premulti_en = true; 1824 alpha_config.src_pixel_alpha_en = true; 1825 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1826 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1827 } else { 1828 /* Cd = Cs + (1 - As) * Cd */ 1829 alpha_config.dst_premulti_en = true; 1830 alpha_config.src_pixel_alpha_en = pixel_alpha_en; 1831 alpha_config.src_glb_alpha_value = plane->state->alpha; 1832 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1833 } 1834 1835 vop2_parse_alpha(&alpha_config, &alpha); 1836 1837 offset = (mixer_id + zpos - 1) * 0x10; 1838 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, 1839 alpha.src_color_ctrl.val); 1840 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, 1841 alpha.dst_color_ctrl.val); 1842 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, 1843 alpha.src_alpha_ctrl.val); 1844 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, 1845 alpha.dst_alpha_ctrl.val); 1846 } 1847 1848 if (vp->id == 0) { 1849 if (bottom_layer_alpha_en) { 1850 /* Transfer pixel alpha to hdr mix */ 1851 alpha_config.src_premulti_en = gpremulti_en; 1852 alpha_config.dst_premulti_en = true; 1853 alpha_config.src_pixel_alpha_en = true; 1854 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1855 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; 1856 vop2_parse_alpha(&alpha_config, &alpha); 1857 1858 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 1859 alpha.src_color_ctrl.val); 1860 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, 1861 alpha.dst_color_ctrl.val); 1862 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, 1863 alpha.src_alpha_ctrl.val); 1864 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, 1865 alpha.dst_alpha_ctrl.val); 1866 } else { 1867 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); 1868 } 1869 } 1870 } 1871 1872 static void vop2_setup_layer_mixer(struct vop2_video_port *vp) 1873 { 1874 struct vop2 *vop2 = vp->vop2; 1875 struct drm_plane *plane; 1876 u32 layer_sel = 0; 1877 u32 port_sel; 1878 unsigned int nlayer, ofs; 1879 struct drm_display_mode *adjusted_mode; 1880 u16 hsync_len; 1881 u16 hdisplay; 1882 u32 bg_dly; 1883 u32 pre_scan_dly; 1884 int i; 1885 struct vop2_video_port *vp0 = &vop2->vps[0]; 1886 struct vop2_video_port *vp1 = &vop2->vps[1]; 1887 struct vop2_video_port *vp2 = &vop2->vps[2]; 1888 1889 adjusted_mode = &vp->crtc.state->adjusted_mode; 1890 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1891 hdisplay = adjusted_mode->crtc_hdisplay; 1892 1893 bg_dly = vp->data->pre_scan_max_dly[3]; 1894 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), 1895 FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); 1896 1897 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; 1898 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); 1899 1900 vop2_writel(vop2, RK3568_OVL_CTRL, 0); 1901 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); 1902 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; 1903 1904 if (vp0->nlayers) 1905 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 1906 vp0->nlayers - 1); 1907 else 1908 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); 1909 1910 if (vp1->nlayers) 1911 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 1912 (vp0->nlayers + vp1->nlayers - 1)); 1913 else 1914 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); 1915 1916 if (vp2->nlayers) 1917 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 1918 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); 1919 else 1920 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); 1921 1922 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); 1923 1924 ofs = 0; 1925 for (i = 0; i < vp->id; i++) 1926 ofs += vop2->vps[i].nlayers; 1927 1928 nlayer = 0; 1929 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { 1930 struct vop2_win *win = to_vop2_win(plane); 1931 1932 switch (win->data->phys_id) { 1933 case ROCKCHIP_VOP2_CLUSTER0: 1934 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; 1935 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); 1936 break; 1937 case ROCKCHIP_VOP2_CLUSTER1: 1938 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; 1939 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); 1940 break; 1941 case ROCKCHIP_VOP2_ESMART0: 1942 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; 1943 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); 1944 break; 1945 case ROCKCHIP_VOP2_ESMART1: 1946 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; 1947 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); 1948 break; 1949 case ROCKCHIP_VOP2_SMART0: 1950 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; 1951 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); 1952 break; 1953 case ROCKCHIP_VOP2_SMART1: 1954 port_sel &= ~RK3568_OVL_PORT_SEL__SMART1; 1955 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); 1956 break; 1957 } 1958 1959 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, 1960 0x7); 1961 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, 1962 win->data->layer_sel_id); 1963 nlayer++; 1964 } 1965 1966 /* configure unused layers to 0x5 (reserved) */ 1967 for (; nlayer < vp->nlayers; nlayer++) { 1968 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); 1969 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); 1970 } 1971 1972 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); 1973 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); 1974 vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); 1975 } 1976 1977 static void vop2_setup_dly_for_windows(struct vop2 *vop2) 1978 { 1979 struct vop2_win *win; 1980 int i = 0; 1981 u32 cdly = 0, sdly = 0; 1982 1983 for (i = 0; i < vop2->data->win_size; i++) { 1984 u32 dly; 1985 1986 win = &vop2->win[i]; 1987 dly = win->delay; 1988 1989 switch (win->data->phys_id) { 1990 case ROCKCHIP_VOP2_CLUSTER0: 1991 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); 1992 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); 1993 break; 1994 case ROCKCHIP_VOP2_CLUSTER1: 1995 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); 1996 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); 1997 break; 1998 case ROCKCHIP_VOP2_ESMART0: 1999 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); 2000 break; 2001 case ROCKCHIP_VOP2_ESMART1: 2002 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); 2003 break; 2004 case ROCKCHIP_VOP2_SMART0: 2005 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); 2006 break; 2007 case ROCKCHIP_VOP2_SMART1: 2008 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); 2009 break; 2010 } 2011 } 2012 2013 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); 2014 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); 2015 } 2016 2017 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, 2018 struct drm_atomic_state *state) 2019 { 2020 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2021 struct vop2 *vop2 = vp->vop2; 2022 struct drm_plane *plane; 2023 2024 vp->win_mask = 0; 2025 2026 drm_atomic_crtc_for_each_plane(plane, crtc) { 2027 struct vop2_win *win = to_vop2_win(plane); 2028 2029 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT]; 2030 2031 vp->win_mask |= BIT(win->data->phys_id); 2032 2033 if (vop2_cluster_window(win)) 2034 vop2_setup_cluster_alpha(vop2, win); 2035 } 2036 2037 if (!vp->win_mask) 2038 return; 2039 2040 vop2_setup_layer_mixer(vp); 2041 vop2_setup_alpha(vp); 2042 vop2_setup_dly_for_windows(vop2); 2043 } 2044 2045 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, 2046 struct drm_atomic_state *state) 2047 { 2048 struct vop2_video_port *vp = to_vop2_video_port(crtc); 2049 2050 vop2_post_config(crtc); 2051 2052 vop2_cfg_done(vp); 2053 2054 spin_lock_irq(&crtc->dev->event_lock); 2055 2056 if (crtc->state->event) { 2057 WARN_ON(drm_crtc_vblank_get(crtc)); 2058 vp->event = crtc->state->event; 2059 crtc->state->event = NULL; 2060 } 2061 2062 spin_unlock_irq(&crtc->dev->event_lock); 2063 } 2064 2065 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { 2066 .mode_fixup = vop2_crtc_mode_fixup, 2067 .atomic_check = vop2_crtc_atomic_check, 2068 .atomic_begin = vop2_crtc_atomic_begin, 2069 .atomic_flush = vop2_crtc_atomic_flush, 2070 .atomic_enable = vop2_crtc_atomic_enable, 2071 .atomic_disable = vop2_crtc_atomic_disable, 2072 }; 2073 2074 static void vop2_crtc_reset(struct drm_crtc *crtc) 2075 { 2076 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); 2077 2078 if (crtc->state) { 2079 __drm_atomic_helper_crtc_destroy_state(crtc->state); 2080 kfree(vcstate); 2081 } 2082 2083 vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL); 2084 if (!vcstate) 2085 return; 2086 2087 crtc->state = &vcstate->base; 2088 crtc->state->crtc = crtc; 2089 } 2090 2091 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) 2092 { 2093 struct rockchip_crtc_state *vcstate, *old_vcstate; 2094 2095 old_vcstate = to_rockchip_crtc_state(crtc->state); 2096 2097 vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL); 2098 if (!vcstate) 2099 return NULL; 2100 2101 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); 2102 2103 return &vcstate->base; 2104 } 2105 2106 static void vop2_crtc_destroy_state(struct drm_crtc *crtc, 2107 struct drm_crtc_state *state) 2108 { 2109 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); 2110 2111 __drm_atomic_helper_crtc_destroy_state(&vcstate->base); 2112 kfree(vcstate); 2113 } 2114 2115 static const struct drm_crtc_funcs vop2_crtc_funcs = { 2116 .set_config = drm_atomic_helper_set_config, 2117 .page_flip = drm_atomic_helper_page_flip, 2118 .destroy = drm_crtc_cleanup, 2119 .reset = vop2_crtc_reset, 2120 .atomic_duplicate_state = vop2_crtc_duplicate_state, 2121 .atomic_destroy_state = vop2_crtc_destroy_state, 2122 .enable_vblank = vop2_crtc_enable_vblank, 2123 .disable_vblank = vop2_crtc_disable_vblank, 2124 }; 2125 2126 static irqreturn_t vop2_isr(int irq, void *data) 2127 { 2128 struct vop2 *vop2 = data; 2129 const struct vop2_data *vop2_data = vop2->data; 2130 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; 2131 int ret = IRQ_NONE; 2132 int i; 2133 2134 /* 2135 * The irq is shared with the iommu. If the runtime-pm state of the 2136 * vop2-device is disabled the irq has to be targeted at the iommu. 2137 */ 2138 if (!pm_runtime_get_if_in_use(vop2->dev)) 2139 return IRQ_NONE; 2140 2141 for (i = 0; i < vop2_data->nr_vps; i++) { 2142 struct vop2_video_port *vp = &vop2->vps[i]; 2143 struct drm_crtc *crtc = &vp->crtc; 2144 u32 irqs; 2145 2146 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); 2147 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); 2148 2149 if (irqs & VP_INT_DSP_HOLD_VALID) { 2150 complete(&vp->dsp_hold_completion); 2151 ret = IRQ_HANDLED; 2152 } 2153 2154 if (irqs & VP_INT_FS_FIELD) { 2155 drm_crtc_handle_vblank(crtc); 2156 spin_lock(&crtc->dev->event_lock); 2157 if (vp->event) { 2158 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); 2159 2160 if (!(val & BIT(vp->id))) { 2161 drm_crtc_send_vblank_event(crtc, vp->event); 2162 vp->event = NULL; 2163 drm_crtc_vblank_put(crtc); 2164 } 2165 } 2166 spin_unlock(&crtc->dev->event_lock); 2167 2168 ret = IRQ_HANDLED; 2169 } 2170 2171 if (irqs & VP_INT_POST_BUF_EMPTY) { 2172 drm_err_ratelimited(vop2->drm, 2173 "POST_BUF_EMPTY irq err at vp%d\n", 2174 vp->id); 2175 ret = IRQ_HANDLED; 2176 } 2177 } 2178 2179 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); 2180 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); 2181 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); 2182 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); 2183 2184 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { 2185 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { 2186 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); 2187 ret = IRQ_HANDLED; 2188 } 2189 } 2190 2191 pm_runtime_put(vop2->dev); 2192 2193 return ret; 2194 } 2195 2196 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, 2197 unsigned long possible_crtcs) 2198 { 2199 const struct vop2_win_data *win_data = win->data; 2200 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2201 BIT(DRM_MODE_BLEND_PREMULTI) | 2202 BIT(DRM_MODE_BLEND_COVERAGE); 2203 int ret; 2204 2205 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, 2206 &vop2_plane_funcs, win_data->formats, 2207 win_data->nformats, 2208 win_data->format_modifiers, 2209 win->type, win_data->name); 2210 if (ret) { 2211 drm_err(vop2->drm, "failed to initialize plane %d\n", ret); 2212 return ret; 2213 } 2214 2215 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); 2216 2217 if (win->data->supported_rotations) 2218 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, 2219 DRM_MODE_ROTATE_0 | 2220 win->data->supported_rotations); 2221 drm_plane_create_alpha_property(&win->base); 2222 drm_plane_create_blend_mode_property(&win->base, blend_caps); 2223 drm_plane_create_zpos_property(&win->base, win->win_id, 0, 2224 vop2->registered_num_wins - 1); 2225 2226 return 0; 2227 } 2228 2229 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) 2230 { 2231 int i; 2232 2233 for (i = 0; i < vop2->data->nr_vps; i++) { 2234 struct vop2_video_port *vp = &vop2->vps[i]; 2235 2236 if (!vp->crtc.port) 2237 continue; 2238 if (vp->primary_plane) 2239 continue; 2240 2241 return vp; 2242 } 2243 2244 return NULL; 2245 } 2246 2247 #define NR_LAYERS 6 2248 2249 static int vop2_create_crtc(struct vop2 *vop2) 2250 { 2251 const struct vop2_data *vop2_data = vop2->data; 2252 struct drm_device *drm = vop2->drm; 2253 struct device *dev = vop2->dev; 2254 struct drm_plane *plane; 2255 struct device_node *port; 2256 struct vop2_video_port *vp; 2257 int i, nvp, nvps = 0; 2258 int ret; 2259 2260 for (i = 0; i < vop2_data->nr_vps; i++) { 2261 const struct vop2_video_port_data *vp_data; 2262 struct device_node *np; 2263 char dclk_name[9]; 2264 2265 vp_data = &vop2_data->vp[i]; 2266 vp = &vop2->vps[i]; 2267 vp->vop2 = vop2; 2268 vp->id = vp_data->id; 2269 vp->regs = vp_data->regs; 2270 vp->data = vp_data; 2271 2272 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); 2273 vp->dclk = devm_clk_get(vop2->dev, dclk_name); 2274 if (IS_ERR(vp->dclk)) { 2275 drm_err(vop2->drm, "failed to get %s\n", dclk_name); 2276 return PTR_ERR(vp->dclk); 2277 } 2278 2279 np = of_graph_get_remote_node(dev->of_node, i, -1); 2280 if (!np) { 2281 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); 2282 continue; 2283 } 2284 of_node_put(np); 2285 2286 port = of_graph_get_port_by_id(dev->of_node, i); 2287 if (!port) { 2288 drm_err(vop2->drm, "no port node found for video_port%d\n", i); 2289 return -ENOENT; 2290 } 2291 2292 vp->crtc.port = port; 2293 nvps++; 2294 } 2295 2296 nvp = 0; 2297 for (i = 0; i < vop2->registered_num_wins; i++) { 2298 struct vop2_win *win = &vop2->win[i]; 2299 u32 possible_crtcs; 2300 2301 if (vop2->data->soc_id == 3566) { 2302 /* 2303 * On RK3566 these windows don't have an independent 2304 * framebuffer. They share the framebuffer with smart0, 2305 * esmart0 and cluster0 respectively. 2306 */ 2307 switch (win->data->phys_id) { 2308 case ROCKCHIP_VOP2_SMART1: 2309 case ROCKCHIP_VOP2_ESMART1: 2310 case ROCKCHIP_VOP2_CLUSTER1: 2311 continue; 2312 } 2313 } 2314 2315 if (win->type == DRM_PLANE_TYPE_PRIMARY) { 2316 vp = find_vp_without_primary(vop2); 2317 if (vp) { 2318 possible_crtcs = BIT(nvp); 2319 vp->primary_plane = win; 2320 nvp++; 2321 } else { 2322 /* change the unused primary window to overlay window */ 2323 win->type = DRM_PLANE_TYPE_OVERLAY; 2324 } 2325 } 2326 2327 if (win->type == DRM_PLANE_TYPE_OVERLAY) 2328 possible_crtcs = (1 << nvps) - 1; 2329 2330 ret = vop2_plane_init(vop2, win, possible_crtcs); 2331 if (ret) { 2332 drm_err(vop2->drm, "failed to init plane %s: %d\n", 2333 win->data->name, ret); 2334 return ret; 2335 } 2336 } 2337 2338 for (i = 0; i < vop2_data->nr_vps; i++) { 2339 vp = &vop2->vps[i]; 2340 2341 if (!vp->crtc.port) 2342 continue; 2343 2344 plane = &vp->primary_plane->base; 2345 2346 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, 2347 &vop2_crtc_funcs, 2348 "video_port%d", vp->id); 2349 if (ret) { 2350 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); 2351 return ret; 2352 } 2353 2354 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); 2355 2356 init_completion(&vp->dsp_hold_completion); 2357 } 2358 2359 /* 2360 * On the VOP2 it's very hard to change the number of layers on a VP 2361 * during runtime, so we distribute the layers equally over the used 2362 * VPs 2363 */ 2364 for (i = 0; i < vop2->data->nr_vps; i++) { 2365 struct vop2_video_port *vp = &vop2->vps[i]; 2366 2367 if (vp->crtc.port) 2368 vp->nlayers = NR_LAYERS / nvps; 2369 } 2370 2371 return 0; 2372 } 2373 2374 static void vop2_destroy_crtc(struct drm_crtc *crtc) 2375 { 2376 of_node_put(crtc->port); 2377 2378 /* 2379 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() 2380 * references the CRTC. 2381 */ 2382 drm_crtc_cleanup(crtc); 2383 } 2384 2385 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { 2386 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), 2387 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), 2388 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), 2389 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), 2390 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), 2391 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), 2392 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), 2393 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), 2394 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), 2395 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), 2396 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), 2397 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), 2398 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), 2399 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), 2400 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), 2401 2402 /* Scale */ 2403 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), 2404 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), 2405 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), 2406 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), 2407 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), 2408 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), 2409 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), 2410 2411 /* cluster regs */ 2412 [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), 2413 [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), 2414 [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), 2415 2416 /* afbc regs */ 2417 [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), 2418 [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), 2419 [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), 2420 [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), 2421 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), 2422 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), 2423 [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), 2424 [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), 2425 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), 2426 [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), 2427 [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), 2428 [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), 2429 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), 2430 [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), 2431 [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), 2432 [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), 2433 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), 2434 [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, 2435 [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, 2436 [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, 2437 [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, 2438 [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, 2439 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2440 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2441 [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, 2442 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2443 [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, 2444 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, 2445 [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, 2446 [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, 2447 }; 2448 2449 static int vop2_cluster_init(struct vop2_win *win) 2450 { 2451 struct vop2 *vop2 = win->vop2; 2452 struct reg_field *cluster_regs; 2453 int ret, i; 2454 2455 cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), 2456 GFP_KERNEL); 2457 if (!cluster_regs) 2458 return -ENOMEM; 2459 2460 for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) 2461 if (cluster_regs[i].reg != 0xffffffff) 2462 cluster_regs[i].reg += win->offset; 2463 2464 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, 2465 cluster_regs, 2466 ARRAY_SIZE(vop2_cluster_regs)); 2467 2468 kfree(cluster_regs); 2469 2470 return ret; 2471 }; 2472 2473 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { 2474 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), 2475 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), 2476 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), 2477 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), 2478 [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), 2479 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), 2480 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), 2481 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), 2482 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), 2483 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), 2484 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), 2485 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), 2486 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), 2487 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), 2488 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), 2489 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), 2490 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), 2491 [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), 2492 [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), 2493 2494 /* Scale */ 2495 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), 2496 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), 2497 [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), 2498 [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), 2499 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), 2500 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), 2501 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), 2502 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), 2503 [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), 2504 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), 2505 [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), 2506 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), 2507 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), 2508 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), 2509 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), 2510 [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), 2511 [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), 2512 [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, 2513 [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, 2514 [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, 2515 [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, 2516 [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, 2517 [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, 2518 [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, 2519 [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, 2520 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, 2521 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, 2522 [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, 2523 [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, 2524 [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, 2525 [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, 2526 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, 2527 [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, 2528 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, 2529 [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, 2530 [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, 2531 }; 2532 2533 static int vop2_esmart_init(struct vop2_win *win) 2534 { 2535 struct vop2 *vop2 = win->vop2; 2536 struct reg_field *esmart_regs; 2537 int ret, i; 2538 2539 esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), 2540 GFP_KERNEL); 2541 if (!esmart_regs) 2542 return -ENOMEM; 2543 2544 for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) 2545 if (esmart_regs[i].reg != 0xffffffff) 2546 esmart_regs[i].reg += win->offset; 2547 2548 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, 2549 esmart_regs, 2550 ARRAY_SIZE(vop2_esmart_regs)); 2551 2552 kfree(esmart_regs); 2553 2554 return ret; 2555 }; 2556 2557 static int vop2_win_init(struct vop2 *vop2) 2558 { 2559 const struct vop2_data *vop2_data = vop2->data; 2560 struct vop2_win *win; 2561 int i, ret; 2562 2563 for (i = 0; i < vop2_data->win_size; i++) { 2564 const struct vop2_win_data *win_data = &vop2_data->win[i]; 2565 2566 win = &vop2->win[i]; 2567 win->data = win_data; 2568 win->type = win_data->type; 2569 win->offset = win_data->base; 2570 win->win_id = i; 2571 win->vop2 = vop2; 2572 if (vop2_cluster_window(win)) 2573 ret = vop2_cluster_init(win); 2574 else 2575 ret = vop2_esmart_init(win); 2576 if (ret) 2577 return ret; 2578 } 2579 2580 vop2->registered_num_wins = vop2_data->win_size; 2581 2582 return 0; 2583 } 2584 2585 /* 2586 * The window registers are only updated when config done is written. 2587 * Until that they read back the old value. As we read-modify-write 2588 * these registers mark them as non-volatile. This makes sure we read 2589 * the new values from the regmap register cache. 2590 */ 2591 static const struct regmap_range vop2_nonvolatile_range[] = { 2592 regmap_reg_range(0x1000, 0x23ff), 2593 }; 2594 2595 static const struct regmap_access_table vop2_volatile_table = { 2596 .no_ranges = vop2_nonvolatile_range, 2597 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), 2598 }; 2599 2600 static const struct regmap_config vop2_regmap_config = { 2601 .reg_bits = 32, 2602 .val_bits = 32, 2603 .reg_stride = 4, 2604 .max_register = 0x3000, 2605 .name = "vop2", 2606 .volatile_table = &vop2_volatile_table, 2607 .cache_type = REGCACHE_RBTREE, 2608 }; 2609 2610 static int vop2_bind(struct device *dev, struct device *master, void *data) 2611 { 2612 struct platform_device *pdev = to_platform_device(dev); 2613 const struct vop2_data *vop2_data; 2614 struct drm_device *drm = data; 2615 struct vop2 *vop2; 2616 struct resource *res; 2617 size_t alloc_size; 2618 int ret; 2619 2620 vop2_data = of_device_get_match_data(dev); 2621 if (!vop2_data) 2622 return -ENODEV; 2623 2624 /* Allocate vop2 struct and its vop2_win array */ 2625 alloc_size = sizeof(*vop2) + sizeof(*vop2->win) * vop2_data->win_size; 2626 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 2627 if (!vop2) 2628 return -ENOMEM; 2629 2630 vop2->dev = dev; 2631 vop2->data = vop2_data; 2632 vop2->drm = drm; 2633 2634 dev_set_drvdata(dev, vop2); 2635 2636 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop"); 2637 if (!res) { 2638 drm_err(vop2->drm, "failed to get vop2 register byname\n"); 2639 return -EINVAL; 2640 } 2641 2642 vop2->regs = devm_ioremap_resource(dev, res); 2643 if (IS_ERR(vop2->regs)) 2644 return PTR_ERR(vop2->regs); 2645 vop2->len = resource_size(res); 2646 2647 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); 2648 2649 ret = vop2_win_init(vop2); 2650 if (ret) 2651 return ret; 2652 2653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut"); 2654 if (res) { 2655 vop2->lut_regs = devm_ioremap_resource(dev, res); 2656 if (IS_ERR(vop2->lut_regs)) 2657 return PTR_ERR(vop2->lut_regs); 2658 } 2659 2660 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 2661 2662 vop2->hclk = devm_clk_get(vop2->dev, "hclk"); 2663 if (IS_ERR(vop2->hclk)) { 2664 drm_err(vop2->drm, "failed to get hclk source\n"); 2665 return PTR_ERR(vop2->hclk); 2666 } 2667 2668 vop2->aclk = devm_clk_get(vop2->dev, "aclk"); 2669 if (IS_ERR(vop2->aclk)) { 2670 drm_err(vop2->drm, "failed to get aclk source\n"); 2671 return PTR_ERR(vop2->aclk); 2672 } 2673 2674 vop2->irq = platform_get_irq(pdev, 0); 2675 if (vop2->irq < 0) { 2676 drm_err(vop2->drm, "cannot find irq for vop2\n"); 2677 return vop2->irq; 2678 } 2679 2680 mutex_init(&vop2->vop2_lock); 2681 2682 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); 2683 if (ret) 2684 return ret; 2685 2686 ret = vop2_create_crtc(vop2); 2687 if (ret) 2688 return ret; 2689 2690 rockchip_drm_dma_init_device(vop2->drm, vop2->dev); 2691 2692 pm_runtime_enable(&pdev->dev); 2693 2694 return 0; 2695 } 2696 2697 static void vop2_unbind(struct device *dev, struct device *master, void *data) 2698 { 2699 struct vop2 *vop2 = dev_get_drvdata(dev); 2700 struct drm_device *drm = vop2->drm; 2701 struct list_head *plane_list = &drm->mode_config.plane_list; 2702 struct list_head *crtc_list = &drm->mode_config.crtc_list; 2703 struct drm_crtc *crtc, *tmpc; 2704 struct drm_plane *plane, *tmpp; 2705 2706 pm_runtime_disable(dev); 2707 2708 list_for_each_entry_safe(plane, tmpp, plane_list, head) 2709 drm_plane_cleanup(plane); 2710 2711 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) 2712 vop2_destroy_crtc(crtc); 2713 } 2714 2715 const struct component_ops vop2_component_ops = { 2716 .bind = vop2_bind, 2717 .unbind = vop2_unbind, 2718 }; 2719 EXPORT_SYMBOL_GPL(vop2_component_ops); 2720