1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef _ROCKCHIP_DRM_VOP_H 16 #define _ROCKCHIP_DRM_VOP_H 17 18 enum vop_data_format { 19 VOP_FMT_ARGB8888 = 0, 20 VOP_FMT_RGB888, 21 VOP_FMT_RGB565, 22 VOP_FMT_YUV420SP = 4, 23 VOP_FMT_YUV422SP, 24 VOP_FMT_YUV444SP, 25 }; 26 27 struct vop_reg_data { 28 uint32_t offset; 29 uint32_t value; 30 }; 31 32 struct vop_reg { 33 uint32_t offset; 34 uint32_t shift; 35 uint32_t mask; 36 bool write_mask; 37 }; 38 39 struct vop_ctrl { 40 struct vop_reg standby; 41 struct vop_reg data_blank; 42 struct vop_reg gate_en; 43 struct vop_reg mmu_en; 44 struct vop_reg rgb_en; 45 struct vop_reg edp_en; 46 struct vop_reg hdmi_en; 47 struct vop_reg mipi_en; 48 struct vop_reg dp_en; 49 struct vop_reg out_mode; 50 struct vop_reg dither_down; 51 struct vop_reg dither_up; 52 struct vop_reg pin_pol; 53 struct vop_reg rgb_pin_pol; 54 struct vop_reg hdmi_pin_pol; 55 struct vop_reg edp_pin_pol; 56 struct vop_reg mipi_pin_pol; 57 struct vop_reg dp_pin_pol; 58 59 struct vop_reg htotal_pw; 60 struct vop_reg hact_st_end; 61 struct vop_reg vtotal_pw; 62 struct vop_reg vact_st_end; 63 struct vop_reg hpost_st_end; 64 struct vop_reg vpost_st_end; 65 66 struct vop_reg line_flag_num[2]; 67 68 struct vop_reg cfg_done; 69 }; 70 71 struct vop_intr { 72 const int *intrs; 73 uint32_t nintrs; 74 struct vop_reg enable; 75 struct vop_reg clear; 76 struct vop_reg status; 77 }; 78 79 struct vop_scl_extension { 80 struct vop_reg cbcr_vsd_mode; 81 struct vop_reg cbcr_vsu_mode; 82 struct vop_reg cbcr_hsd_mode; 83 struct vop_reg cbcr_ver_scl_mode; 84 struct vop_reg cbcr_hor_scl_mode; 85 struct vop_reg yrgb_vsd_mode; 86 struct vop_reg yrgb_vsu_mode; 87 struct vop_reg yrgb_hsd_mode; 88 struct vop_reg yrgb_ver_scl_mode; 89 struct vop_reg yrgb_hor_scl_mode; 90 struct vop_reg line_load_mode; 91 struct vop_reg cbcr_axi_gather_num; 92 struct vop_reg yrgb_axi_gather_num; 93 struct vop_reg vsd_cbcr_gt2; 94 struct vop_reg vsd_cbcr_gt4; 95 struct vop_reg vsd_yrgb_gt2; 96 struct vop_reg vsd_yrgb_gt4; 97 struct vop_reg bic_coe_sel; 98 struct vop_reg cbcr_axi_gather_en; 99 struct vop_reg yrgb_axi_gather_en; 100 struct vop_reg lb_mode; 101 }; 102 103 struct vop_scl_regs { 104 const struct vop_scl_extension *ext; 105 106 struct vop_reg scale_yrgb_x; 107 struct vop_reg scale_yrgb_y; 108 struct vop_reg scale_cbcr_x; 109 struct vop_reg scale_cbcr_y; 110 }; 111 112 struct vop_win_phy { 113 const struct vop_scl_regs *scl; 114 const uint32_t *data_formats; 115 uint32_t nformats; 116 117 struct vop_reg enable; 118 struct vop_reg format; 119 struct vop_reg rb_swap; 120 struct vop_reg act_info; 121 struct vop_reg dsp_info; 122 struct vop_reg dsp_st; 123 struct vop_reg yrgb_mst; 124 struct vop_reg uv_mst; 125 struct vop_reg yrgb_vir; 126 struct vop_reg uv_vir; 127 128 struct vop_reg dst_alpha_ctl; 129 struct vop_reg src_alpha_ctl; 130 }; 131 132 struct vop_win_data { 133 uint32_t base; 134 const struct vop_win_phy *phy; 135 enum drm_plane_type type; 136 }; 137 138 struct vop_data { 139 const struct vop_reg_data *init_table; 140 unsigned int table_size; 141 const struct vop_ctrl *ctrl; 142 const struct vop_intr *intr; 143 const struct vop_win_data *win; 144 unsigned int win_size; 145 }; 146 147 /* interrupt define */ 148 #define DSP_HOLD_VALID_INTR (1 << 0) 149 #define FS_INTR (1 << 1) 150 #define LINE_FLAG_INTR (1 << 2) 151 #define BUS_ERROR_INTR (1 << 3) 152 153 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 154 LINE_FLAG_INTR | BUS_ERROR_INTR) 155 156 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 157 #define FS_INTR_EN(x) ((x) << 5) 158 #define LINE_FLAG_INTR_EN(x) ((x) << 6) 159 #define BUS_ERROR_INTR_EN(x) ((x) << 7) 160 #define DSP_HOLD_VALID_INTR_MASK (1 << 4) 161 #define FS_INTR_MASK (1 << 5) 162 #define LINE_FLAG_INTR_MASK (1 << 6) 163 #define BUS_ERROR_INTR_MASK (1 << 7) 164 165 #define INTR_CLR_SHIFT 8 166 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 167 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 168 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 169 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 170 171 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 172 #define DSP_LINE_NUM_MASK (0x1fff << 12) 173 174 /* src alpha ctrl define */ 175 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 176 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 177 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 178 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 179 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 180 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 181 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 182 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 183 /* dst alpha ctrl define */ 184 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 185 186 /* 187 * display output interface supported by rockchip lcdc 188 */ 189 #define ROCKCHIP_OUT_MODE_P888 0 190 #define ROCKCHIP_OUT_MODE_P666 1 191 #define ROCKCHIP_OUT_MODE_P565 2 192 /* for use special outface */ 193 #define ROCKCHIP_OUT_MODE_AAAA 15 194 195 enum alpha_mode { 196 ALPHA_STRAIGHT, 197 ALPHA_INVERSE, 198 }; 199 200 enum global_blend_mode { 201 ALPHA_GLOBAL, 202 ALPHA_PER_PIX, 203 ALPHA_PER_PIX_GLOBAL, 204 }; 205 206 enum alpha_cal_mode { 207 ALPHA_SATURATION, 208 ALPHA_NO_SATURATION, 209 }; 210 211 enum color_mode { 212 ALPHA_SRC_PRE_MUL, 213 ALPHA_SRC_NO_PRE_MUL, 214 }; 215 216 enum factor_mode { 217 ALPHA_ZERO, 218 ALPHA_ONE, 219 ALPHA_SRC, 220 ALPHA_SRC_INVERSE, 221 ALPHA_SRC_GLOBAL, 222 }; 223 224 enum scale_mode { 225 SCALE_NONE = 0x0, 226 SCALE_UP = 0x1, 227 SCALE_DOWN = 0x2 228 }; 229 230 enum lb_mode { 231 LB_YUV_3840X5 = 0x0, 232 LB_YUV_2560X8 = 0x1, 233 LB_RGB_3840X2 = 0x2, 234 LB_RGB_2560X4 = 0x3, 235 LB_RGB_1920X5 = 0x4, 236 LB_RGB_1280X8 = 0x5 237 }; 238 239 enum sacle_up_mode { 240 SCALE_UP_BIL = 0x0, 241 SCALE_UP_BIC = 0x1 242 }; 243 244 enum scale_down_mode { 245 SCALE_DOWN_BIL = 0x0, 246 SCALE_DOWN_AVG = 0x1 247 }; 248 249 enum vop_pol { 250 HSYNC_POSITIVE = 0, 251 VSYNC_POSITIVE = 1, 252 DEN_NEGATIVE = 2, 253 DCLK_INVERT = 3 254 }; 255 256 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 257 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 258 #define SCL_MAX_VSKIPLINES 4 259 #define MIN_SCL_FT_AFTER_VSKIP 1 260 261 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 262 { 263 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 264 } 265 266 static inline uint16_t scl_cal_scale2(int src, int dst) 267 { 268 return ((src - 1) << 12) / (dst - 1); 269 } 270 271 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 272 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 273 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 274 275 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 276 int vskiplines) 277 { 278 int act_height; 279 280 act_height = (src_h + vskiplines - 1) / vskiplines; 281 282 return GET_SCL_FT_BILI_DN(act_height, dst_h); 283 } 284 285 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 286 { 287 if (src < dst) 288 return SCALE_UP; 289 else if (src > dst) 290 return SCALE_DOWN; 291 292 return SCALE_NONE; 293 } 294 295 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 296 { 297 uint32_t vskiplines; 298 299 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 300 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 301 break; 302 303 return vskiplines; 304 } 305 306 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 307 { 308 int lb_mode; 309 310 if (width > 2560) 311 lb_mode = LB_RGB_3840X2; 312 else if (width > 1920) 313 lb_mode = LB_RGB_2560X4; 314 else if (!is_yuv) 315 lb_mode = LB_RGB_1920X5; 316 else if (width > 1280) 317 lb_mode = LB_YUV_3840X5; 318 else 319 lb_mode = LB_YUV_2560X8; 320 321 return lb_mode; 322 } 323 324 extern const struct component_ops vop_component_ops; 325 #endif /* _ROCKCHIP_DRM_VOP_H */ 326