1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef _ROCKCHIP_DRM_VOP_H 16 #define _ROCKCHIP_DRM_VOP_H 17 18 /* 19 * major: IP major version, used for IP structure 20 * minor: big feature change under same structure 21 */ 22 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 23 #define VOP_MAJOR(version) ((version) >> 8) 24 #define VOP_MINOR(version) ((version) & 0xff) 25 26 #define NUM_YUV2YUV_COEFFICIENTS 12 27 28 enum vop_data_format { 29 VOP_FMT_ARGB8888 = 0, 30 VOP_FMT_RGB888, 31 VOP_FMT_RGB565, 32 VOP_FMT_YUV420SP = 4, 33 VOP_FMT_YUV422SP, 34 VOP_FMT_YUV444SP, 35 }; 36 37 struct vop_reg { 38 uint32_t mask; 39 uint16_t offset; 40 uint8_t shift; 41 bool write_mask; 42 bool relaxed; 43 }; 44 45 struct vop_modeset { 46 struct vop_reg htotal_pw; 47 struct vop_reg hact_st_end; 48 struct vop_reg hpost_st_end; 49 struct vop_reg vtotal_pw; 50 struct vop_reg vact_st_end; 51 struct vop_reg vpost_st_end; 52 }; 53 54 struct vop_output { 55 struct vop_reg pin_pol; 56 struct vop_reg dp_pin_pol; 57 struct vop_reg edp_pin_pol; 58 struct vop_reg hdmi_pin_pol; 59 struct vop_reg mipi_pin_pol; 60 struct vop_reg rgb_pin_pol; 61 struct vop_reg dp_en; 62 struct vop_reg edp_en; 63 struct vop_reg hdmi_en; 64 struct vop_reg mipi_en; 65 struct vop_reg mipi_dual_channel_en; 66 struct vop_reg rgb_en; 67 }; 68 69 struct vop_common { 70 struct vop_reg cfg_done; 71 struct vop_reg dsp_blank; 72 struct vop_reg data_blank; 73 struct vop_reg pre_dither_down; 74 struct vop_reg dither_down; 75 struct vop_reg dither_up; 76 struct vop_reg gate_en; 77 struct vop_reg mmu_en; 78 struct vop_reg out_mode; 79 struct vop_reg standby; 80 }; 81 82 struct vop_misc { 83 struct vop_reg global_regdone_en; 84 }; 85 86 struct vop_intr { 87 const int *intrs; 88 uint32_t nintrs; 89 90 struct vop_reg line_flag_num[2]; 91 struct vop_reg enable; 92 struct vop_reg clear; 93 struct vop_reg status; 94 }; 95 96 struct vop_scl_extension { 97 struct vop_reg cbcr_vsd_mode; 98 struct vop_reg cbcr_vsu_mode; 99 struct vop_reg cbcr_hsd_mode; 100 struct vop_reg cbcr_ver_scl_mode; 101 struct vop_reg cbcr_hor_scl_mode; 102 struct vop_reg yrgb_vsd_mode; 103 struct vop_reg yrgb_vsu_mode; 104 struct vop_reg yrgb_hsd_mode; 105 struct vop_reg yrgb_ver_scl_mode; 106 struct vop_reg yrgb_hor_scl_mode; 107 struct vop_reg line_load_mode; 108 struct vop_reg cbcr_axi_gather_num; 109 struct vop_reg yrgb_axi_gather_num; 110 struct vop_reg vsd_cbcr_gt2; 111 struct vop_reg vsd_cbcr_gt4; 112 struct vop_reg vsd_yrgb_gt2; 113 struct vop_reg vsd_yrgb_gt4; 114 struct vop_reg bic_coe_sel; 115 struct vop_reg cbcr_axi_gather_en; 116 struct vop_reg yrgb_axi_gather_en; 117 struct vop_reg lb_mode; 118 }; 119 120 struct vop_scl_regs { 121 const struct vop_scl_extension *ext; 122 123 struct vop_reg scale_yrgb_x; 124 struct vop_reg scale_yrgb_y; 125 struct vop_reg scale_cbcr_x; 126 struct vop_reg scale_cbcr_y; 127 }; 128 129 struct vop_yuv2yuv_phy { 130 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS]; 131 }; 132 133 struct vop_win_phy { 134 const struct vop_scl_regs *scl; 135 const uint32_t *data_formats; 136 uint32_t nformats; 137 138 struct vop_reg enable; 139 struct vop_reg gate; 140 struct vop_reg format; 141 struct vop_reg rb_swap; 142 struct vop_reg act_info; 143 struct vop_reg dsp_info; 144 struct vop_reg dsp_st; 145 struct vop_reg yrgb_mst; 146 struct vop_reg uv_mst; 147 struct vop_reg yrgb_vir; 148 struct vop_reg uv_vir; 149 struct vop_reg y_mir_en; 150 struct vop_reg x_mir_en; 151 152 struct vop_reg dst_alpha_ctl; 153 struct vop_reg src_alpha_ctl; 154 struct vop_reg channel; 155 }; 156 157 struct vop_win_yuv2yuv_data { 158 uint32_t base; 159 const struct vop_yuv2yuv_phy *phy; 160 struct vop_reg y2r_en; 161 }; 162 163 struct vop_win_data { 164 uint32_t base; 165 const struct vop_win_phy *phy; 166 enum drm_plane_type type; 167 }; 168 169 struct vop_data { 170 uint32_t version; 171 const struct vop_intr *intr; 172 const struct vop_common *common; 173 const struct vop_misc *misc; 174 const struct vop_modeset *modeset; 175 const struct vop_output *output; 176 const struct vop_win_yuv2yuv_data *win_yuv2yuv; 177 const struct vop_win_data *win; 178 unsigned int win_size; 179 180 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) 181 #define VOP_FEATURE_INTERNAL_RGB BIT(1) 182 u64 feature; 183 }; 184 185 /* interrupt define */ 186 #define DSP_HOLD_VALID_INTR (1 << 0) 187 #define FS_INTR (1 << 1) 188 #define LINE_FLAG_INTR (1 << 2) 189 #define BUS_ERROR_INTR (1 << 3) 190 191 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 192 LINE_FLAG_INTR | BUS_ERROR_INTR) 193 194 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 195 #define FS_INTR_EN(x) ((x) << 5) 196 #define LINE_FLAG_INTR_EN(x) ((x) << 6) 197 #define BUS_ERROR_INTR_EN(x) ((x) << 7) 198 #define DSP_HOLD_VALID_INTR_MASK (1 << 4) 199 #define FS_INTR_MASK (1 << 5) 200 #define LINE_FLAG_INTR_MASK (1 << 6) 201 #define BUS_ERROR_INTR_MASK (1 << 7) 202 203 #define INTR_CLR_SHIFT 8 204 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 205 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 206 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 207 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 208 209 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 210 #define DSP_LINE_NUM_MASK (0x1fff << 12) 211 212 /* src alpha ctrl define */ 213 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 214 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 215 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 216 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 217 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 218 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 219 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 220 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 221 /* dst alpha ctrl define */ 222 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 223 224 /* 225 * display output interface supported by rockchip lcdc 226 */ 227 #define ROCKCHIP_OUT_MODE_P888 0 228 #define ROCKCHIP_OUT_MODE_P666 1 229 #define ROCKCHIP_OUT_MODE_P565 2 230 /* for use special outface */ 231 #define ROCKCHIP_OUT_MODE_AAAA 15 232 233 /* output flags */ 234 #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) 235 236 enum alpha_mode { 237 ALPHA_STRAIGHT, 238 ALPHA_INVERSE, 239 }; 240 241 enum global_blend_mode { 242 ALPHA_GLOBAL, 243 ALPHA_PER_PIX, 244 ALPHA_PER_PIX_GLOBAL, 245 }; 246 247 enum alpha_cal_mode { 248 ALPHA_SATURATION, 249 ALPHA_NO_SATURATION, 250 }; 251 252 enum color_mode { 253 ALPHA_SRC_PRE_MUL, 254 ALPHA_SRC_NO_PRE_MUL, 255 }; 256 257 enum factor_mode { 258 ALPHA_ZERO, 259 ALPHA_ONE, 260 ALPHA_SRC, 261 ALPHA_SRC_INVERSE, 262 ALPHA_SRC_GLOBAL, 263 }; 264 265 enum scale_mode { 266 SCALE_NONE = 0x0, 267 SCALE_UP = 0x1, 268 SCALE_DOWN = 0x2 269 }; 270 271 enum lb_mode { 272 LB_YUV_3840X5 = 0x0, 273 LB_YUV_2560X8 = 0x1, 274 LB_RGB_3840X2 = 0x2, 275 LB_RGB_2560X4 = 0x3, 276 LB_RGB_1920X5 = 0x4, 277 LB_RGB_1280X8 = 0x5 278 }; 279 280 enum sacle_up_mode { 281 SCALE_UP_BIL = 0x0, 282 SCALE_UP_BIC = 0x1 283 }; 284 285 enum scale_down_mode { 286 SCALE_DOWN_BIL = 0x0, 287 SCALE_DOWN_AVG = 0x1 288 }; 289 290 enum vop_pol { 291 HSYNC_POSITIVE = 0, 292 VSYNC_POSITIVE = 1, 293 DEN_NEGATIVE = 2, 294 DCLK_INVERT = 3 295 }; 296 297 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 298 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 299 #define SCL_MAX_VSKIPLINES 4 300 #define MIN_SCL_FT_AFTER_VSKIP 1 301 302 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 303 { 304 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 305 } 306 307 static inline uint16_t scl_cal_scale2(int src, int dst) 308 { 309 return ((src - 1) << 12) / (dst - 1); 310 } 311 312 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 313 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 314 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 315 316 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 317 int vskiplines) 318 { 319 int act_height; 320 321 act_height = (src_h + vskiplines - 1) / vskiplines; 322 323 if (act_height == dst_h) 324 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; 325 326 return GET_SCL_FT_BILI_DN(act_height, dst_h); 327 } 328 329 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 330 { 331 if (src < dst) 332 return SCALE_UP; 333 else if (src > dst) 334 return SCALE_DOWN; 335 336 return SCALE_NONE; 337 } 338 339 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 340 { 341 uint32_t vskiplines; 342 343 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 344 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 345 break; 346 347 return vskiplines; 348 } 349 350 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 351 { 352 int lb_mode; 353 354 if (is_yuv) { 355 if (width > 1280) 356 lb_mode = LB_YUV_3840X5; 357 else 358 lb_mode = LB_YUV_2560X8; 359 } else { 360 if (width > 2560) 361 lb_mode = LB_RGB_3840X2; 362 else if (width > 1920) 363 lb_mode = LB_RGB_2560X4; 364 else 365 lb_mode = LB_RGB_1920X5; 366 } 367 368 return lb_mode; 369 } 370 371 extern const struct component_ops vop_component_ops; 372 #endif /* _ROCKCHIP_DRM_VOP_H */ 373