1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef _ROCKCHIP_DRM_VOP_H 16 #define _ROCKCHIP_DRM_VOP_H 17 18 enum vop_data_format { 19 VOP_FMT_ARGB8888 = 0, 20 VOP_FMT_RGB888, 21 VOP_FMT_RGB565, 22 VOP_FMT_YUV420SP = 4, 23 VOP_FMT_YUV422SP, 24 VOP_FMT_YUV444SP, 25 }; 26 27 struct vop_reg_data { 28 uint32_t offset; 29 uint32_t value; 30 }; 31 32 struct vop_reg { 33 uint32_t offset; 34 uint32_t shift; 35 uint32_t mask; 36 }; 37 38 struct vop_ctrl { 39 struct vop_reg standby; 40 struct vop_reg data_blank; 41 struct vop_reg gate_en; 42 struct vop_reg mmu_en; 43 struct vop_reg rgb_en; 44 struct vop_reg edp_en; 45 struct vop_reg hdmi_en; 46 struct vop_reg mipi_en; 47 struct vop_reg out_mode; 48 struct vop_reg dither_down; 49 struct vop_reg dither_up; 50 struct vop_reg pin_pol; 51 52 struct vop_reg htotal_pw; 53 struct vop_reg hact_st_end; 54 struct vop_reg vtotal_pw; 55 struct vop_reg vact_st_end; 56 struct vop_reg hpost_st_end; 57 struct vop_reg vpost_st_end; 58 59 struct vop_reg cfg_done; 60 }; 61 62 struct vop_intr { 63 const int *intrs; 64 uint32_t nintrs; 65 struct vop_reg enable; 66 struct vop_reg clear; 67 struct vop_reg status; 68 }; 69 70 struct vop_scl_extension { 71 struct vop_reg cbcr_vsd_mode; 72 struct vop_reg cbcr_vsu_mode; 73 struct vop_reg cbcr_hsd_mode; 74 struct vop_reg cbcr_ver_scl_mode; 75 struct vop_reg cbcr_hor_scl_mode; 76 struct vop_reg yrgb_vsd_mode; 77 struct vop_reg yrgb_vsu_mode; 78 struct vop_reg yrgb_hsd_mode; 79 struct vop_reg yrgb_ver_scl_mode; 80 struct vop_reg yrgb_hor_scl_mode; 81 struct vop_reg line_load_mode; 82 struct vop_reg cbcr_axi_gather_num; 83 struct vop_reg yrgb_axi_gather_num; 84 struct vop_reg vsd_cbcr_gt2; 85 struct vop_reg vsd_cbcr_gt4; 86 struct vop_reg vsd_yrgb_gt2; 87 struct vop_reg vsd_yrgb_gt4; 88 struct vop_reg bic_coe_sel; 89 struct vop_reg cbcr_axi_gather_en; 90 struct vop_reg yrgb_axi_gather_en; 91 struct vop_reg lb_mode; 92 }; 93 94 struct vop_scl_regs { 95 const struct vop_scl_extension *ext; 96 97 struct vop_reg scale_yrgb_x; 98 struct vop_reg scale_yrgb_y; 99 struct vop_reg scale_cbcr_x; 100 struct vop_reg scale_cbcr_y; 101 }; 102 103 struct vop_win_phy { 104 const struct vop_scl_regs *scl; 105 const uint32_t *data_formats; 106 uint32_t nformats; 107 108 struct vop_reg enable; 109 struct vop_reg format; 110 struct vop_reg rb_swap; 111 struct vop_reg act_info; 112 struct vop_reg dsp_info; 113 struct vop_reg dsp_st; 114 struct vop_reg yrgb_mst; 115 struct vop_reg uv_mst; 116 struct vop_reg yrgb_vir; 117 struct vop_reg uv_vir; 118 119 struct vop_reg dst_alpha_ctl; 120 struct vop_reg src_alpha_ctl; 121 }; 122 123 struct vop_win_data { 124 uint32_t base; 125 const struct vop_win_phy *phy; 126 enum drm_plane_type type; 127 }; 128 129 struct vop_data { 130 const struct vop_reg_data *init_table; 131 unsigned int table_size; 132 const struct vop_ctrl *ctrl; 133 const struct vop_intr *intr; 134 const struct vop_win_data *win; 135 unsigned int win_size; 136 }; 137 138 /* interrupt define */ 139 #define DSP_HOLD_VALID_INTR (1 << 0) 140 #define FS_INTR (1 << 1) 141 #define LINE_FLAG_INTR (1 << 2) 142 #define BUS_ERROR_INTR (1 << 3) 143 144 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 145 LINE_FLAG_INTR | BUS_ERROR_INTR) 146 147 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 148 #define FS_INTR_EN(x) ((x) << 5) 149 #define LINE_FLAG_INTR_EN(x) ((x) << 6) 150 #define BUS_ERROR_INTR_EN(x) ((x) << 7) 151 #define DSP_HOLD_VALID_INTR_MASK (1 << 4) 152 #define FS_INTR_MASK (1 << 5) 153 #define LINE_FLAG_INTR_MASK (1 << 6) 154 #define BUS_ERROR_INTR_MASK (1 << 7) 155 156 #define INTR_CLR_SHIFT 8 157 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 158 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 159 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 160 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 161 162 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 163 #define DSP_LINE_NUM_MASK (0x1fff << 12) 164 165 /* src alpha ctrl define */ 166 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 167 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 168 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 169 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 170 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 171 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 172 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 173 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 174 /* dst alpha ctrl define */ 175 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 176 177 /* 178 * display output interface supported by rockchip lcdc 179 */ 180 #define ROCKCHIP_OUT_MODE_P888 0 181 #define ROCKCHIP_OUT_MODE_P666 1 182 #define ROCKCHIP_OUT_MODE_P565 2 183 /* for use special outface */ 184 #define ROCKCHIP_OUT_MODE_AAAA 15 185 186 enum alpha_mode { 187 ALPHA_STRAIGHT, 188 ALPHA_INVERSE, 189 }; 190 191 enum global_blend_mode { 192 ALPHA_GLOBAL, 193 ALPHA_PER_PIX, 194 ALPHA_PER_PIX_GLOBAL, 195 }; 196 197 enum alpha_cal_mode { 198 ALPHA_SATURATION, 199 ALPHA_NO_SATURATION, 200 }; 201 202 enum color_mode { 203 ALPHA_SRC_PRE_MUL, 204 ALPHA_SRC_NO_PRE_MUL, 205 }; 206 207 enum factor_mode { 208 ALPHA_ZERO, 209 ALPHA_ONE, 210 ALPHA_SRC, 211 ALPHA_SRC_INVERSE, 212 ALPHA_SRC_GLOBAL, 213 }; 214 215 enum scale_mode { 216 SCALE_NONE = 0x0, 217 SCALE_UP = 0x1, 218 SCALE_DOWN = 0x2 219 }; 220 221 enum lb_mode { 222 LB_YUV_3840X5 = 0x0, 223 LB_YUV_2560X8 = 0x1, 224 LB_RGB_3840X2 = 0x2, 225 LB_RGB_2560X4 = 0x3, 226 LB_RGB_1920X5 = 0x4, 227 LB_RGB_1280X8 = 0x5 228 }; 229 230 enum sacle_up_mode { 231 SCALE_UP_BIL = 0x0, 232 SCALE_UP_BIC = 0x1 233 }; 234 235 enum scale_down_mode { 236 SCALE_DOWN_BIL = 0x0, 237 SCALE_DOWN_AVG = 0x1 238 }; 239 240 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 241 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 242 #define SCL_MAX_VSKIPLINES 4 243 #define MIN_SCL_FT_AFTER_VSKIP 1 244 245 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 246 { 247 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 248 } 249 250 static inline uint16_t scl_cal_scale2(int src, int dst) 251 { 252 return ((src - 1) << 12) / (dst - 1); 253 } 254 255 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 256 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 257 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 258 259 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 260 int vskiplines) 261 { 262 int act_height; 263 264 act_height = (src_h + vskiplines - 1) / vskiplines; 265 266 return GET_SCL_FT_BILI_DN(act_height, dst_h); 267 } 268 269 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 270 { 271 if (src < dst) 272 return SCALE_UP; 273 else if (src > dst) 274 return SCALE_DOWN; 275 276 return SCALE_NONE; 277 } 278 279 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 280 { 281 uint32_t vskiplines; 282 283 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 284 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 285 break; 286 287 return vskiplines; 288 } 289 290 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 291 { 292 int lb_mode; 293 294 if (width > 2560) 295 lb_mode = LB_RGB_3840X2; 296 else if (width > 1920) 297 lb_mode = LB_RGB_2560X4; 298 else if (!is_yuv) 299 lb_mode = LB_RGB_1920X5; 300 else if (width > 1280) 301 lb_mode = LB_YUV_3840X5; 302 else 303 lb_mode = LB_YUV_2560X8; 304 305 return lb_mode; 306 } 307 308 extern const struct component_ops vop_component_ops; 309 #endif /* _ROCKCHIP_DRM_VOP_H */ 310