1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_blend.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_flip_work.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_framebuffer.h> 28 #include <drm/drm_gem_atomic_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_self_refresh_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #ifdef CONFIG_DRM_ANALOGIX_DP 35 #include <drm/bridge/analogix_dp.h> 36 #endif 37 38 #include "rockchip_drm_drv.h" 39 #include "rockchip_drm_gem.h" 40 #include "rockchip_drm_fb.h" 41 #include "rockchip_drm_vop.h" 42 #include "rockchip_rgb.h" 43 44 #define VOP_WIN_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 46 #define VOP_SCL_SET(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 48 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 49 vop_reg_set(vop, &win->phy->scl->ext->name, \ 50 win->base, ~0, v, #name) 51 52 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 53 do { \ 54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 56 } while (0) 57 58 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 59 do { \ 60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 62 } while (0) 63 64 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 66 67 #define VOP_REG_SET(vop, group, name, v) \ 68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 69 70 #define VOP_HAS_REG(vop, group, name) \ 71 (!!(vop->data->group->name.mask)) 72 73 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 74 do { \ 75 int i, reg = 0, mask = 0; \ 76 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 77 if (vop->data->intr->intrs[i] & type) { \ 78 reg |= (v) << i; \ 79 mask |= 1 << i; \ 80 } \ 81 } \ 82 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 83 } while (0) 84 #define VOP_INTR_GET_TYPE(vop, name, type) \ 85 vop_get_intr_type(vop, &vop->data->intr->name, type) 86 87 #define VOP_WIN_GET(vop, win, name) \ 88 vop_read_reg(vop, win->base, &win->phy->name) 89 90 #define VOP_WIN_HAS_REG(win, name) \ 91 (!!(win->phy->name.mask)) 92 93 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 95 96 #define VOP_WIN_TO_INDEX(vop_win) \ 97 ((vop_win) - (vop_win)->vop->win) 98 99 #define VOP_AFBC_SET(vop, name, v) \ 100 do { \ 101 if ((vop)->data->afbc) \ 102 vop_reg_set((vop), &(vop)->data->afbc->name, \ 103 0, ~0, v, #name); \ 104 } while (0) 105 106 #define to_vop(x) container_of(x, struct vop, crtc) 107 #define to_vop_win(x) container_of(x, struct vop_win, base) 108 109 #define AFBC_FMT_RGB565 0x0 110 #define AFBC_FMT_U8U8U8U8 0x5 111 #define AFBC_FMT_U8U8U8 0x4 112 113 #define AFBC_TILE_16x16 BIT(4) 114 115 /* 116 * The coefficients of the following matrix are all fixed points. 117 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 118 * They are all represented in two's complement. 119 */ 120 static const uint32_t bt601_yuv2rgb[] = { 121 0x4A8, 0x0, 0x662, 122 0x4A8, 0x1E6F, 0x1CBF, 123 0x4A8, 0x812, 0x0, 124 0x321168, 0x0877CF, 0x2EB127 125 }; 126 127 enum vop_pending { 128 VOP_PENDING_FB_UNREF, 129 }; 130 131 struct vop_win { 132 struct drm_plane base; 133 const struct vop_win_data *data; 134 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 135 struct vop *vop; 136 }; 137 138 struct rockchip_rgb; 139 struct vop { 140 struct drm_crtc crtc; 141 struct device *dev; 142 struct drm_device *drm_dev; 143 bool is_enabled; 144 145 struct completion dsp_hold_completion; 146 unsigned int win_enabled; 147 148 /* protected by dev->event_lock */ 149 struct drm_pending_vblank_event *event; 150 151 struct drm_flip_work fb_unref_work; 152 unsigned long pending; 153 154 struct completion line_flag_completion; 155 156 const struct vop_data *data; 157 158 uint32_t *regsbak; 159 void __iomem *regs; 160 void __iomem *lut_regs; 161 162 /* physical map length of vop register */ 163 uint32_t len; 164 165 /* one time only one process allowed to config the register */ 166 spinlock_t reg_lock; 167 /* lock vop irq reg */ 168 spinlock_t irq_lock; 169 /* protects crtc enable/disable */ 170 struct mutex vop_lock; 171 172 unsigned int irq; 173 174 /* vop AHP clk */ 175 struct clk *hclk; 176 /* vop dclk */ 177 struct clk *dclk; 178 /* vop share memory frequency */ 179 struct clk *aclk; 180 181 /* vop dclk reset */ 182 struct reset_control *dclk_rst; 183 184 /* optional internal rgb encoder */ 185 struct rockchip_rgb *rgb; 186 187 struct vop_win win[]; 188 }; 189 190 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 191 { 192 return readl(vop->regs + offset); 193 } 194 195 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 196 const struct vop_reg *reg) 197 { 198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 199 } 200 201 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 202 uint32_t _offset, uint32_t _mask, uint32_t v, 203 const char *reg_name) 204 { 205 int offset, mask, shift; 206 207 if (!reg || !reg->mask) { 208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 209 return; 210 } 211 212 offset = reg->offset + _offset; 213 mask = reg->mask & _mask; 214 shift = reg->shift; 215 216 if (reg->write_mask) { 217 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 218 } else { 219 uint32_t cached_val = vop->regsbak[offset >> 2]; 220 221 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 222 vop->regsbak[offset >> 2] = v; 223 } 224 225 if (reg->relaxed) 226 writel_relaxed(v, vop->regs + offset); 227 else 228 writel(v, vop->regs + offset); 229 } 230 231 static inline uint32_t vop_get_intr_type(struct vop *vop, 232 const struct vop_reg *reg, int type) 233 { 234 uint32_t i, ret = 0; 235 uint32_t regs = vop_read_reg(vop, 0, reg); 236 237 for (i = 0; i < vop->data->intr->nintrs; i++) { 238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 239 ret |= vop->data->intr->intrs[i]; 240 } 241 242 return ret; 243 } 244 245 static inline void vop_cfg_done(struct vop *vop) 246 { 247 VOP_REG_SET(vop, common, cfg_done, 1); 248 } 249 250 static bool has_rb_swapped(uint32_t version, uint32_t format) 251 { 252 switch (format) { 253 case DRM_FORMAT_XBGR8888: 254 case DRM_FORMAT_ABGR8888: 255 case DRM_FORMAT_BGR565: 256 return true; 257 /* 258 * full framework (IP version 3.x) only need rb swapped for RGB888 and 259 * little framework (IP version 2.x) only need rb swapped for BGR888, 260 * check for 3.x to also only rb swap BGR888 for unknown vop version 261 */ 262 case DRM_FORMAT_RGB888: 263 return VOP_MAJOR(version) == 3; 264 case DRM_FORMAT_BGR888: 265 return VOP_MAJOR(version) != 3; 266 default: 267 return false; 268 } 269 } 270 271 static bool has_uv_swapped(uint32_t format) 272 { 273 switch (format) { 274 case DRM_FORMAT_NV21: 275 case DRM_FORMAT_NV61: 276 case DRM_FORMAT_NV42: 277 return true; 278 default: 279 return false; 280 } 281 } 282 283 static bool is_fmt_10(uint32_t format) 284 { 285 switch (format) { 286 case DRM_FORMAT_NV15: 287 case DRM_FORMAT_NV20: 288 case DRM_FORMAT_NV30: 289 return true; 290 default: 291 return false; 292 } 293 } 294 295 static enum vop_data_format vop_convert_format(uint32_t format) 296 { 297 switch (format) { 298 case DRM_FORMAT_XRGB8888: 299 case DRM_FORMAT_ARGB8888: 300 case DRM_FORMAT_XBGR8888: 301 case DRM_FORMAT_ABGR8888: 302 return VOP_FMT_ARGB8888; 303 case DRM_FORMAT_RGB888: 304 case DRM_FORMAT_BGR888: 305 return VOP_FMT_RGB888; 306 case DRM_FORMAT_RGB565: 307 case DRM_FORMAT_BGR565: 308 return VOP_FMT_RGB565; 309 case DRM_FORMAT_NV12: 310 case DRM_FORMAT_NV15: 311 case DRM_FORMAT_NV21: 312 return VOP_FMT_YUV420SP; 313 case DRM_FORMAT_NV16: 314 case DRM_FORMAT_NV20: 315 case DRM_FORMAT_NV61: 316 return VOP_FMT_YUV422SP; 317 case DRM_FORMAT_NV24: 318 case DRM_FORMAT_NV30: 319 case DRM_FORMAT_NV42: 320 return VOP_FMT_YUV444SP; 321 default: 322 DRM_ERROR("unsupported format[%08x]\n", format); 323 return -EINVAL; 324 } 325 } 326 327 static int vop_convert_afbc_format(uint32_t format) 328 { 329 switch (format) { 330 case DRM_FORMAT_XRGB8888: 331 case DRM_FORMAT_ARGB8888: 332 case DRM_FORMAT_XBGR8888: 333 case DRM_FORMAT_ABGR8888: 334 return AFBC_FMT_U8U8U8U8; 335 case DRM_FORMAT_RGB888: 336 case DRM_FORMAT_BGR888: 337 return AFBC_FMT_U8U8U8; 338 case DRM_FORMAT_RGB565: 339 case DRM_FORMAT_BGR565: 340 return AFBC_FMT_RGB565; 341 default: 342 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format); 343 return -EINVAL; 344 } 345 } 346 347 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 348 uint32_t dst, bool is_horizontal, 349 int vsu_mode, int *vskiplines) 350 { 351 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 352 353 if (vskiplines) 354 *vskiplines = 0; 355 356 if (is_horizontal) { 357 if (mode == SCALE_UP) 358 val = GET_SCL_FT_BIC(src, dst); 359 else if (mode == SCALE_DOWN) 360 val = GET_SCL_FT_BILI_DN(src, dst); 361 } else { 362 if (mode == SCALE_UP) { 363 if (vsu_mode == SCALE_UP_BIL) 364 val = GET_SCL_FT_BILI_UP(src, dst); 365 else 366 val = GET_SCL_FT_BIC(src, dst); 367 } else if (mode == SCALE_DOWN) { 368 if (vskiplines) { 369 *vskiplines = scl_get_vskiplines(src, dst); 370 val = scl_get_bili_dn_vskip(src, dst, 371 *vskiplines); 372 } else { 373 val = GET_SCL_FT_BILI_DN(src, dst); 374 } 375 } 376 } 377 378 return val; 379 } 380 381 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 382 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 383 uint32_t dst_h, const struct drm_format_info *info) 384 { 385 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 386 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 387 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 388 bool is_yuv = false; 389 uint16_t cbcr_src_w = src_w / info->hsub; 390 uint16_t cbcr_src_h = src_h / info->vsub; 391 uint16_t vsu_mode; 392 uint16_t lb_mode; 393 uint32_t val; 394 int vskiplines; 395 396 if (info->is_yuv) 397 is_yuv = true; 398 399 if (dst_w > 4096) { 400 DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n"); 401 return; 402 } 403 404 if (!win->phy->scl->ext) { 405 VOP_SCL_SET(vop, win, scale_yrgb_x, 406 scl_cal_scale2(src_w, dst_w)); 407 VOP_SCL_SET(vop, win, scale_yrgb_y, 408 scl_cal_scale2(src_h, dst_h)); 409 if (is_yuv) { 410 VOP_SCL_SET(vop, win, scale_cbcr_x, 411 scl_cal_scale2(cbcr_src_w, dst_w)); 412 VOP_SCL_SET(vop, win, scale_cbcr_y, 413 scl_cal_scale2(cbcr_src_h, dst_h)); 414 } 415 return; 416 } 417 418 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 419 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 420 421 if (is_yuv) { 422 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 423 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 424 if (cbcr_hor_scl_mode == SCALE_DOWN) 425 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 426 else 427 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 428 } else { 429 if (yrgb_hor_scl_mode == SCALE_DOWN) 430 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 431 else 432 lb_mode = scl_vop_cal_lb_mode(src_w, false); 433 } 434 435 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 436 if (lb_mode == LB_RGB_3840X2) { 437 if (yrgb_ver_scl_mode != SCALE_NONE) { 438 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 439 return; 440 } 441 if (cbcr_ver_scl_mode != SCALE_NONE) { 442 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 443 return; 444 } 445 vsu_mode = SCALE_UP_BIL; 446 } else if (lb_mode == LB_RGB_2560X4) { 447 vsu_mode = SCALE_UP_BIL; 448 } else { 449 vsu_mode = SCALE_UP_BIC; 450 } 451 452 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 453 true, 0, NULL); 454 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 455 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 456 false, vsu_mode, &vskiplines); 457 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 458 459 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 460 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 461 462 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 463 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 464 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 465 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 466 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 467 if (is_yuv) { 468 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 469 dst_w, true, 0, NULL); 470 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 471 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 472 dst_h, false, vsu_mode, &vskiplines); 473 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 474 475 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 476 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 477 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 478 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 479 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 480 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 481 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 482 } 483 } 484 485 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 486 { 487 unsigned long flags; 488 489 if (WARN_ON(!vop->is_enabled)) 490 return; 491 492 spin_lock_irqsave(&vop->irq_lock, flags); 493 494 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 495 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 496 497 spin_unlock_irqrestore(&vop->irq_lock, flags); 498 } 499 500 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 501 { 502 unsigned long flags; 503 504 if (WARN_ON(!vop->is_enabled)) 505 return; 506 507 spin_lock_irqsave(&vop->irq_lock, flags); 508 509 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 510 511 spin_unlock_irqrestore(&vop->irq_lock, flags); 512 } 513 514 /* 515 * (1) each frame starts at the start of the Vsync pulse which is signaled by 516 * the "FRAME_SYNC" interrupt. 517 * (2) the active data region of each frame ends at dsp_vact_end 518 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 519 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 520 * 521 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 522 * Interrupts 523 * LINE_FLAG -------------------------------+ 524 * FRAME_SYNC ----+ | 525 * | | 526 * v v 527 * | Vsync | Vbp | Vactive | Vfp | 528 * ^ ^ ^ ^ 529 * | | | | 530 * | | | | 531 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 532 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 533 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 534 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 535 */ 536 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 537 { 538 uint32_t line_flag_irq; 539 unsigned long flags; 540 541 spin_lock_irqsave(&vop->irq_lock, flags); 542 543 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 544 545 spin_unlock_irqrestore(&vop->irq_lock, flags); 546 547 return !!line_flag_irq; 548 } 549 550 static void vop_line_flag_irq_enable(struct vop *vop) 551 { 552 unsigned long flags; 553 554 if (WARN_ON(!vop->is_enabled)) 555 return; 556 557 spin_lock_irqsave(&vop->irq_lock, flags); 558 559 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 560 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 561 562 spin_unlock_irqrestore(&vop->irq_lock, flags); 563 } 564 565 static void vop_line_flag_irq_disable(struct vop *vop) 566 { 567 unsigned long flags; 568 569 if (WARN_ON(!vop->is_enabled)) 570 return; 571 572 spin_lock_irqsave(&vop->irq_lock, flags); 573 574 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 575 576 spin_unlock_irqrestore(&vop->irq_lock, flags); 577 } 578 579 static int vop_core_clks_enable(struct vop *vop) 580 { 581 int ret; 582 583 ret = clk_enable(vop->hclk); 584 if (ret < 0) 585 return ret; 586 587 ret = clk_enable(vop->aclk); 588 if (ret < 0) 589 goto err_disable_hclk; 590 591 return 0; 592 593 err_disable_hclk: 594 clk_disable(vop->hclk); 595 return ret; 596 } 597 598 static void vop_core_clks_disable(struct vop *vop) 599 { 600 clk_disable(vop->aclk); 601 clk_disable(vop->hclk); 602 } 603 604 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 605 { 606 const struct vop_win_data *win = vop_win->data; 607 608 if (win->phy->scl && win->phy->scl->ext) { 609 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 610 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 611 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 612 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 613 } 614 615 VOP_WIN_SET(vop, win, enable, 0); 616 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 617 } 618 619 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 620 { 621 struct vop *vop = to_vop(crtc); 622 int ret, i; 623 624 ret = pm_runtime_resume_and_get(vop->dev); 625 if (ret < 0) { 626 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 627 return ret; 628 } 629 630 ret = vop_core_clks_enable(vop); 631 if (WARN_ON(ret < 0)) 632 goto err_put_pm_runtime; 633 634 ret = clk_enable(vop->dclk); 635 if (WARN_ON(ret < 0)) 636 goto err_disable_core; 637 638 /* 639 * Slave iommu shares power, irq and clock with vop. It was associated 640 * automatically with this master device via common driver code. 641 * Now that we have enabled the clock we attach it to the shared drm 642 * mapping. 643 */ 644 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 645 if (ret) { 646 DRM_DEV_ERROR(vop->dev, 647 "failed to attach dma mapping, %d\n", ret); 648 goto err_disable_dclk; 649 } 650 651 spin_lock(&vop->reg_lock); 652 for (i = 0; i < vop->len; i += 4) 653 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 654 655 /* 656 * We need to make sure that all windows are disabled before we 657 * enable the crtc. Otherwise we might try to scan from a destroyed 658 * buffer later. 659 * 660 * In the case of enable-after-PSR, we don't need to worry about this 661 * case since the buffer is guaranteed to be valid and disabling the 662 * window will result in screen glitches on PSR exit. 663 */ 664 if (!old_state || !old_state->self_refresh_active) { 665 for (i = 0; i < vop->data->win_size; i++) { 666 struct vop_win *vop_win = &vop->win[i]; 667 668 vop_win_disable(vop, vop_win); 669 } 670 } 671 672 if (vop->data->afbc) { 673 struct rockchip_crtc_state *s; 674 /* 675 * Disable AFBC and forget there was a vop window with AFBC 676 */ 677 VOP_AFBC_SET(vop, enable, 0); 678 s = to_rockchip_crtc_state(crtc->state); 679 s->enable_afbc = false; 680 } 681 682 vop_cfg_done(vop); 683 684 spin_unlock(&vop->reg_lock); 685 686 /* 687 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 688 */ 689 vop->is_enabled = true; 690 691 spin_lock(&vop->reg_lock); 692 693 VOP_REG_SET(vop, common, standby, 1); 694 695 spin_unlock(&vop->reg_lock); 696 697 drm_crtc_vblank_on(crtc); 698 699 return 0; 700 701 err_disable_dclk: 702 clk_disable(vop->dclk); 703 err_disable_core: 704 vop_core_clks_disable(vop); 705 err_put_pm_runtime: 706 pm_runtime_put_sync(vop->dev); 707 return ret; 708 } 709 710 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 711 { 712 struct vop *vop = to_vop(crtc); 713 int i; 714 715 spin_lock(&vop->reg_lock); 716 717 for (i = 0; i < vop->data->win_size; i++) { 718 struct vop_win *vop_win = &vop->win[i]; 719 const struct vop_win_data *win = vop_win->data; 720 721 VOP_WIN_SET(vop, win, enable, 722 enabled && (vop->win_enabled & BIT(i))); 723 } 724 vop_cfg_done(vop); 725 726 spin_unlock(&vop->reg_lock); 727 } 728 729 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 730 struct drm_atomic_state *state) 731 { 732 struct vop *vop = to_vop(crtc); 733 734 WARN_ON(vop->event); 735 736 if (crtc->state->self_refresh_active) { 737 rockchip_drm_set_win_enabled(crtc, false); 738 goto out; 739 } 740 741 mutex_lock(&vop->vop_lock); 742 743 drm_crtc_vblank_off(crtc); 744 745 /* 746 * Vop standby will take effect at end of current frame, 747 * if dsp hold valid irq happen, it means standby complete. 748 * 749 * we must wait standby complete when we want to disable aclk, 750 * if not, memory bus maybe dead. 751 */ 752 reinit_completion(&vop->dsp_hold_completion); 753 vop_dsp_hold_valid_irq_enable(vop); 754 755 spin_lock(&vop->reg_lock); 756 757 VOP_REG_SET(vop, common, standby, 1); 758 759 spin_unlock(&vop->reg_lock); 760 761 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 762 msecs_to_jiffies(200))) 763 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 764 765 vop_dsp_hold_valid_irq_disable(vop); 766 767 vop->is_enabled = false; 768 769 /* 770 * vop standby complete, so iommu detach is safe. 771 */ 772 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 773 774 clk_disable(vop->dclk); 775 vop_core_clks_disable(vop); 776 pm_runtime_put(vop->dev); 777 778 mutex_unlock(&vop->vop_lock); 779 780 out: 781 if (crtc->state->event && !crtc->state->active) { 782 spin_lock_irq(&crtc->dev->event_lock); 783 drm_crtc_send_vblank_event(crtc, crtc->state->event); 784 spin_unlock_irq(&crtc->dev->event_lock); 785 786 crtc->state->event = NULL; 787 } 788 } 789 790 static inline bool rockchip_afbc(u64 modifier) 791 { 792 return modifier == ROCKCHIP_AFBC_MOD; 793 } 794 795 static bool rockchip_mod_supported(struct drm_plane *plane, 796 u32 format, u64 modifier) 797 { 798 if (modifier == DRM_FORMAT_MOD_LINEAR) 799 return true; 800 801 if (!rockchip_afbc(modifier)) { 802 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 803 804 return false; 805 } 806 807 return vop_convert_afbc_format(format) >= 0; 808 } 809 810 static int vop_plane_atomic_check(struct drm_plane *plane, 811 struct drm_atomic_state *state) 812 { 813 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 814 plane); 815 struct drm_crtc *crtc = new_plane_state->crtc; 816 struct drm_crtc_state *crtc_state; 817 struct drm_framebuffer *fb = new_plane_state->fb; 818 struct vop_win *vop_win = to_vop_win(plane); 819 const struct vop_win_data *win = vop_win->data; 820 int ret; 821 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 822 DRM_PLANE_NO_SCALING; 823 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 824 DRM_PLANE_NO_SCALING; 825 826 if (!crtc || WARN_ON(!fb)) 827 return 0; 828 829 crtc_state = drm_atomic_get_existing_crtc_state(state, 830 crtc); 831 if (WARN_ON(!crtc_state)) 832 return -EINVAL; 833 834 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 835 min_scale, max_scale, 836 true, true); 837 if (ret) 838 return ret; 839 840 if (!new_plane_state->visible) 841 return 0; 842 843 ret = vop_convert_format(fb->format->format); 844 if (ret < 0) 845 return ret; 846 847 /* 848 * Src.x1 can be odd when do clip, but yuv plane start point 849 * need align with 2 pixel. 850 */ 851 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 852 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n"); 853 return -EINVAL; 854 } 855 856 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 857 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n"); 858 return -EINVAL; 859 } 860 861 if (rockchip_afbc(fb->modifier)) { 862 struct vop *vop = to_vop(crtc); 863 864 if (!vop->data->afbc) { 865 DRM_DEBUG_KMS("vop does not support AFBC\n"); 866 return -EINVAL; 867 } 868 869 ret = vop_convert_afbc_format(fb->format->format); 870 if (ret < 0) 871 return ret; 872 873 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 874 DRM_DEBUG_KMS("AFBC does not support offset display, " \ 875 "xpos=%d, ypos=%d, offset=%d\n", 876 new_plane_state->src.x1, new_plane_state->src.y1, 877 fb->offsets[0]); 878 return -EINVAL; 879 } 880 881 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 882 DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n", 883 new_plane_state->rotation); 884 return -EINVAL; 885 } 886 } 887 888 return 0; 889 } 890 891 static void vop_plane_atomic_disable(struct drm_plane *plane, 892 struct drm_atomic_state *state) 893 { 894 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 895 plane); 896 struct vop_win *vop_win = to_vop_win(plane); 897 struct vop *vop = to_vop(old_state->crtc); 898 899 if (!old_state->crtc) 900 return; 901 902 spin_lock(&vop->reg_lock); 903 904 vop_win_disable(vop, vop_win); 905 906 spin_unlock(&vop->reg_lock); 907 } 908 909 static void vop_plane_atomic_update(struct drm_plane *plane, 910 struct drm_atomic_state *state) 911 { 912 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 913 plane); 914 struct drm_crtc *crtc = new_state->crtc; 915 struct vop_win *vop_win = to_vop_win(plane); 916 const struct vop_win_data *win = vop_win->data; 917 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 918 struct vop *vop = to_vop(new_state->crtc); 919 struct drm_framebuffer *fb = new_state->fb; 920 unsigned int actual_w, actual_h; 921 unsigned int dsp_stx, dsp_sty; 922 uint32_t act_info, dsp_info, dsp_st; 923 struct drm_rect *src = &new_state->src; 924 struct drm_rect *dest = &new_state->dst; 925 struct drm_gem_object *obj, *uv_obj; 926 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 927 unsigned long offset; 928 dma_addr_t dma_addr; 929 uint32_t val; 930 bool rb_swap, uv_swap; 931 int win_index = VOP_WIN_TO_INDEX(vop_win); 932 int format; 933 int is_yuv = fb->format->is_yuv; 934 int i; 935 936 /* 937 * can't update plane when vop is disabled. 938 */ 939 if (WARN_ON(!crtc)) 940 return; 941 942 if (WARN_ON(!vop->is_enabled)) 943 return; 944 945 if (!new_state->visible) { 946 vop_plane_atomic_disable(plane, state); 947 return; 948 } 949 950 obj = fb->obj[0]; 951 rk_obj = to_rockchip_obj(obj); 952 953 actual_w = drm_rect_width(src) >> 16; 954 actual_h = drm_rect_height(src) >> 16; 955 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 956 957 dsp_info = (drm_rect_height(dest) - 1) << 16; 958 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 959 960 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 961 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 962 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 963 964 if (fb->format->char_per_block[0]) 965 offset = drm_format_info_min_pitch(fb->format, 0, 966 src->x1 >> 16); 967 else 968 offset = (src->x1 >> 16) * fb->format->cpp[0]; 969 970 offset += (src->y1 >> 16) * fb->pitches[0]; 971 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 972 973 /* 974 * For y-mirroring we need to move address 975 * to the beginning of the last line. 976 */ 977 if (new_state->rotation & DRM_MODE_REFLECT_Y) 978 dma_addr += (actual_h - 1) * fb->pitches[0]; 979 980 format = vop_convert_format(fb->format->format); 981 982 spin_lock(&vop->reg_lock); 983 984 if (rockchip_afbc(fb->modifier)) { 985 int afbc_format = vop_convert_afbc_format(fb->format->format); 986 987 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 988 VOP_AFBC_SET(vop, hreg_block_split, 0); 989 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 990 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 991 VOP_AFBC_SET(vop, pic_size, act_info); 992 } 993 994 VOP_WIN_SET(vop, win, format, format); 995 VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); 996 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 997 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 998 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 999 VOP_WIN_SET(vop, win, y_mir_en, 1000 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 1001 VOP_WIN_SET(vop, win, x_mir_en, 1002 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 1003 1004 if (is_yuv) { 1005 uv_obj = fb->obj[1]; 1006 rk_uv_obj = to_rockchip_obj(uv_obj); 1007 1008 if (fb->format->char_per_block[1]) 1009 offset = drm_format_info_min_pitch(fb->format, 1, 1010 src->x1 >> 16); 1011 else 1012 offset = (src->x1 >> 16) * fb->format->cpp[1]; 1013 offset /= fb->format->hsub; 1014 offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub; 1015 1016 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 1017 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 1018 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 1019 1020 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 1021 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 1022 win_yuv2yuv, 1023 y2r_coefficients[i], 1024 bt601_yuv2rgb[i]); 1025 } 1026 1027 uv_swap = has_uv_swapped(fb->format->format); 1028 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1029 } 1030 1031 if (win->phy->scl) 1032 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1033 drm_rect_width(dest), drm_rect_height(dest), 1034 fb->format); 1035 1036 VOP_WIN_SET(vop, win, act_info, act_info); 1037 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1038 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1039 1040 rb_swap = has_rb_swapped(vop->data->version, fb->format->format); 1041 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1042 1043 /* 1044 * Blending win0 with the background color doesn't seem to work 1045 * correctly. We only get the background color, no matter the contents 1046 * of the win0 framebuffer. However, blending pre-multiplied color 1047 * with the default opaque black default background color is a no-op, 1048 * so we can just disable blending to get the correct result. 1049 */ 1050 if (fb->format->has_alpha && win_index > 0) { 1051 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1052 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1053 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1054 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1055 SRC_BLEND_M0(ALPHA_PER_PIX) | 1056 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1057 SRC_FACTOR_M0(ALPHA_ONE); 1058 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1059 1060 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1061 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1062 VOP_WIN_SET(vop, win, alpha_en, 1); 1063 } else { 1064 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1065 VOP_WIN_SET(vop, win, alpha_en, 0); 1066 } 1067 1068 VOP_WIN_SET(vop, win, enable, 1); 1069 vop->win_enabled |= BIT(win_index); 1070 spin_unlock(&vop->reg_lock); 1071 } 1072 1073 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1074 struct drm_atomic_state *state, bool flip) 1075 { 1076 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1077 plane); 1078 struct vop_win *vop_win = to_vop_win(plane); 1079 const struct vop_win_data *win = vop_win->data; 1080 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1081 DRM_PLANE_NO_SCALING; 1082 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1083 DRM_PLANE_NO_SCALING; 1084 struct drm_crtc_state *crtc_state; 1085 1086 if (plane != new_plane_state->crtc->cursor) 1087 return -EINVAL; 1088 1089 if (!plane->state) 1090 return -EINVAL; 1091 1092 if (!plane->state->fb) 1093 return -EINVAL; 1094 1095 crtc_state = drm_atomic_get_existing_crtc_state(state, new_plane_state->crtc); 1096 1097 /* Special case for asynchronous cursor updates. */ 1098 if (!crtc_state) 1099 crtc_state = plane->crtc->state; 1100 1101 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1102 min_scale, max_scale, 1103 true, true); 1104 } 1105 1106 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1107 struct drm_atomic_state *state) 1108 { 1109 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1110 plane); 1111 struct vop *vop = to_vop(plane->state->crtc); 1112 struct drm_framebuffer *old_fb = plane->state->fb; 1113 1114 plane->state->crtc_x = new_state->crtc_x; 1115 plane->state->crtc_y = new_state->crtc_y; 1116 plane->state->crtc_h = new_state->crtc_h; 1117 plane->state->crtc_w = new_state->crtc_w; 1118 plane->state->src_x = new_state->src_x; 1119 plane->state->src_y = new_state->src_y; 1120 plane->state->src_h = new_state->src_h; 1121 plane->state->src_w = new_state->src_w; 1122 swap(plane->state->fb, new_state->fb); 1123 1124 if (vop->is_enabled) { 1125 vop_plane_atomic_update(plane, state); 1126 spin_lock(&vop->reg_lock); 1127 vop_cfg_done(vop); 1128 spin_unlock(&vop->reg_lock); 1129 1130 /* 1131 * A scanout can still be occurring, so we can't drop the 1132 * reference to the old framebuffer. To solve this we get a 1133 * reference to old_fb and set a worker to release it later. 1134 * FIXME: if we perform 500 async_update calls before the 1135 * vblank, then we can have 500 different framebuffers waiting 1136 * to be released. 1137 */ 1138 if (old_fb && plane->state->fb != old_fb) { 1139 drm_framebuffer_get(old_fb); 1140 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1141 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1142 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1143 } 1144 } 1145 } 1146 1147 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1148 .atomic_check = vop_plane_atomic_check, 1149 .atomic_update = vop_plane_atomic_update, 1150 .atomic_disable = vop_plane_atomic_disable, 1151 .atomic_async_check = vop_plane_atomic_async_check, 1152 .atomic_async_update = vop_plane_atomic_async_update, 1153 }; 1154 1155 static const struct drm_plane_funcs vop_plane_funcs = { 1156 .update_plane = drm_atomic_helper_update_plane, 1157 .disable_plane = drm_atomic_helper_disable_plane, 1158 .destroy = drm_plane_cleanup, 1159 .reset = drm_atomic_helper_plane_reset, 1160 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1161 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1162 .format_mod_supported = rockchip_mod_supported, 1163 }; 1164 1165 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1166 { 1167 struct vop *vop = to_vop(crtc); 1168 unsigned long flags; 1169 1170 if (WARN_ON(!vop->is_enabled)) 1171 return -EPERM; 1172 1173 spin_lock_irqsave(&vop->irq_lock, flags); 1174 1175 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1176 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1177 1178 spin_unlock_irqrestore(&vop->irq_lock, flags); 1179 1180 return 0; 1181 } 1182 1183 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1184 { 1185 struct vop *vop = to_vop(crtc); 1186 unsigned long flags; 1187 1188 if (WARN_ON(!vop->is_enabled)) 1189 return; 1190 1191 spin_lock_irqsave(&vop->irq_lock, flags); 1192 1193 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1194 1195 spin_unlock_irqrestore(&vop->irq_lock, flags); 1196 } 1197 1198 static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, 1199 const struct drm_display_mode *mode) 1200 { 1201 struct vop *vop = to_vop(crtc); 1202 1203 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) 1204 return MODE_BAD_HVALUE; 1205 1206 return MODE_OK; 1207 } 1208 1209 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1210 const struct drm_display_mode *mode, 1211 struct drm_display_mode *adjusted_mode) 1212 { 1213 struct vop *vop = to_vop(crtc); 1214 unsigned long rate; 1215 1216 /* 1217 * Clock craziness. 1218 * 1219 * Key points: 1220 * 1221 * - DRM works in kHz. 1222 * - Clock framework works in Hz. 1223 * - Rockchip's clock driver picks the clock rate that is the 1224 * same _OR LOWER_ than the one requested. 1225 * 1226 * Action plan: 1227 * 1228 * 1. Try to set the exact rate first, and confirm the clock framework 1229 * can provide it. 1230 * 1231 * 2. If the clock framework cannot provide the exact rate, we should 1232 * add 999 Hz to the requested rate. That way if the clock we need 1233 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1234 * the clock framework will actually give us the right clock. 1235 * 1236 * 3. Get the clock framework to round the rate for us to tell us 1237 * what it will actually make. 1238 * 1239 * 4. Store the rounded up rate so that we don't need to worry about 1240 * this in the actual clk_set_rate(). 1241 */ 1242 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1243 if (rate / 1000 != adjusted_mode->clock) 1244 rate = clk_round_rate(vop->dclk, 1245 adjusted_mode->clock * 1000 + 999); 1246 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1247 1248 return true; 1249 } 1250 1251 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1252 { 1253 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1254 } 1255 1256 static u32 vop_lut_buffer_index(struct vop *vop) 1257 { 1258 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1259 } 1260 1261 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1262 { 1263 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1264 unsigned int i, bpc = ilog2(vop->data->lut_size); 1265 1266 for (i = 0; i < crtc->gamma_size; i++) { 1267 u32 word; 1268 1269 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1270 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1271 drm_color_lut_extract(lut[i].blue, bpc); 1272 writel(word, vop->lut_regs + i * 4); 1273 } 1274 } 1275 1276 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1277 struct drm_crtc_state *old_state) 1278 { 1279 struct drm_crtc_state *state = crtc->state; 1280 unsigned int idle; 1281 u32 lut_idx, old_idx; 1282 int ret; 1283 1284 if (!vop->lut_regs) 1285 return; 1286 1287 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1288 /* 1289 * To disable gamma (gamma_lut is null) or to write 1290 * an update to the LUT, clear dsp_lut_en. 1291 */ 1292 spin_lock(&vop->reg_lock); 1293 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1294 vop_cfg_done(vop); 1295 spin_unlock(&vop->reg_lock); 1296 1297 /* 1298 * In order to write the LUT to the internal memory, 1299 * we need to first make sure the dsp_lut_en bit is cleared. 1300 */ 1301 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1302 idle, !idle, 5, 30 * 1000); 1303 if (ret) { 1304 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1305 return; 1306 } 1307 1308 if (!state->gamma_lut) 1309 return; 1310 } else { 1311 /* 1312 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1313 * by setting update_gamma_lut then waiting for lut_buffer_index change 1314 */ 1315 old_idx = vop_lut_buffer_index(vop); 1316 } 1317 1318 spin_lock(&vop->reg_lock); 1319 vop_crtc_write_gamma_lut(vop, crtc); 1320 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1321 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1322 vop_cfg_done(vop); 1323 spin_unlock(&vop->reg_lock); 1324 1325 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1326 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1327 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1328 if (ret) { 1329 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1330 return; 1331 } 1332 1333 /* 1334 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1335 * in our backup of the regs. 1336 */ 1337 spin_lock(&vop->reg_lock); 1338 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1339 spin_unlock(&vop->reg_lock); 1340 } 1341 } 1342 1343 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1344 struct drm_atomic_state *state) 1345 { 1346 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1347 crtc); 1348 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1349 crtc); 1350 struct vop *vop = to_vop(crtc); 1351 1352 /* 1353 * Only update GAMMA if the 'active' flag is not changed, 1354 * otherwise it's updated by .atomic_enable. 1355 */ 1356 if (crtc_state->color_mgmt_changed && 1357 !crtc_state->active_changed) 1358 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1359 } 1360 1361 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1362 struct drm_atomic_state *state) 1363 { 1364 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1365 crtc); 1366 struct vop *vop = to_vop(crtc); 1367 const struct vop_data *vop_data = vop->data; 1368 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1369 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1370 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1371 u16 hdisplay = adjusted_mode->hdisplay; 1372 u16 htotal = adjusted_mode->htotal; 1373 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1374 u16 hact_end = hact_st + hdisplay; 1375 u16 vdisplay = adjusted_mode->vdisplay; 1376 u16 vtotal = adjusted_mode->vtotal; 1377 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1378 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1379 u16 vact_end = vact_st + vdisplay; 1380 uint32_t pin_pol, val; 1381 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1382 int ret; 1383 1384 if (old_state && old_state->self_refresh_active) { 1385 drm_crtc_vblank_on(crtc); 1386 rockchip_drm_set_win_enabled(crtc, true); 1387 return; 1388 } 1389 1390 mutex_lock(&vop->vop_lock); 1391 1392 WARN_ON(vop->event); 1393 1394 ret = vop_enable(crtc, old_state); 1395 if (ret) { 1396 mutex_unlock(&vop->vop_lock); 1397 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1398 return; 1399 } 1400 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1401 BIT(HSYNC_POSITIVE) : 0; 1402 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1403 BIT(VSYNC_POSITIVE) : 0; 1404 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1405 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1406 1407 switch (s->output_type) { 1408 case DRM_MODE_CONNECTOR_LVDS: 1409 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1410 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1411 VOP_REG_SET(vop, output, rgb_en, 1); 1412 break; 1413 case DRM_MODE_CONNECTOR_eDP: 1414 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1415 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1416 VOP_REG_SET(vop, output, edp_en, 1); 1417 break; 1418 case DRM_MODE_CONNECTOR_HDMIA: 1419 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1420 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1421 VOP_REG_SET(vop, output, hdmi_en, 1); 1422 break; 1423 case DRM_MODE_CONNECTOR_DSI: 1424 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1425 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1426 VOP_REG_SET(vop, output, mipi_en, 1); 1427 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1428 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1429 break; 1430 case DRM_MODE_CONNECTOR_DisplayPort: 1431 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1432 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1433 VOP_REG_SET(vop, output, dp_en, 1); 1434 break; 1435 default: 1436 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1437 s->output_type); 1438 } 1439 1440 /* 1441 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1442 */ 1443 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1444 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1445 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1446 1447 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1448 VOP_REG_SET(vop, common, pre_dither_down, 1); 1449 else 1450 VOP_REG_SET(vop, common, pre_dither_down, 0); 1451 1452 if (dither_bpc == 6) { 1453 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1454 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1455 VOP_REG_SET(vop, common, dither_down_en, 1); 1456 } else { 1457 VOP_REG_SET(vop, common, dither_down_en, 0); 1458 } 1459 1460 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1461 1462 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1463 val = hact_st << 16; 1464 val |= hact_end; 1465 VOP_REG_SET(vop, modeset, hact_st_end, val); 1466 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1467 1468 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1469 val = vact_st << 16; 1470 val |= vact_end; 1471 VOP_REG_SET(vop, modeset, vact_st_end, val); 1472 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1473 1474 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1475 1476 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1477 1478 VOP_REG_SET(vop, common, standby, 0); 1479 mutex_unlock(&vop->vop_lock); 1480 1481 /* 1482 * If we have a GAMMA LUT in the state, then let's make sure 1483 * it's updated. We might be coming out of suspend, 1484 * which means the LUT internal memory needs to be re-written. 1485 */ 1486 if (crtc->state->gamma_lut) 1487 vop_crtc_gamma_set(vop, crtc, old_state); 1488 } 1489 1490 static bool vop_fs_irq_is_pending(struct vop *vop) 1491 { 1492 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1493 } 1494 1495 static void vop_wait_for_irq_handler(struct vop *vop) 1496 { 1497 bool pending; 1498 int ret; 1499 1500 /* 1501 * Spin until frame start interrupt status bit goes low, which means 1502 * that interrupt handler was invoked and cleared it. The timeout of 1503 * 10 msecs is really too long, but it is just a safety measure if 1504 * something goes really wrong. The wait will only happen in the very 1505 * unlikely case of a vblank happening exactly at the same time and 1506 * shouldn't exceed microseconds range. 1507 */ 1508 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1509 !pending, 0, 10 * 1000); 1510 if (ret) 1511 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1512 1513 synchronize_irq(vop->irq); 1514 } 1515 1516 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1517 struct drm_atomic_state *state) 1518 { 1519 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1520 crtc); 1521 struct vop *vop = to_vop(crtc); 1522 struct drm_plane *plane; 1523 struct drm_plane_state *plane_state; 1524 struct rockchip_crtc_state *s; 1525 int afbc_planes = 0; 1526 1527 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1528 crtc_state->gamma_lut) { 1529 unsigned int len; 1530 1531 len = drm_color_lut_size(crtc_state->gamma_lut); 1532 if (len != crtc->gamma_size) { 1533 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1534 len, crtc->gamma_size); 1535 return -EINVAL; 1536 } 1537 } 1538 1539 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1540 plane_state = 1541 drm_atomic_get_plane_state(crtc_state->state, plane); 1542 if (IS_ERR(plane_state)) { 1543 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1544 plane->name); 1545 return PTR_ERR(plane_state); 1546 } 1547 1548 if (drm_is_afbc(plane_state->fb->modifier)) 1549 ++afbc_planes; 1550 } 1551 1552 if (afbc_planes > 1) { 1553 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1554 return -EINVAL; 1555 } 1556 1557 s = to_rockchip_crtc_state(crtc_state); 1558 s->enable_afbc = afbc_planes > 0; 1559 1560 return 0; 1561 } 1562 1563 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1564 struct drm_atomic_state *state) 1565 { 1566 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1567 crtc); 1568 struct drm_atomic_state *old_state = old_crtc_state->state; 1569 struct drm_plane_state *old_plane_state, *new_plane_state; 1570 struct vop *vop = to_vop(crtc); 1571 struct drm_plane *plane; 1572 struct rockchip_crtc_state *s; 1573 int i; 1574 1575 if (WARN_ON(!vop->is_enabled)) 1576 return; 1577 1578 spin_lock(&vop->reg_lock); 1579 1580 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1581 s = to_rockchip_crtc_state(crtc->state); 1582 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1583 vop_cfg_done(vop); 1584 1585 /* Ack the DMA transfer of the previous frame (RK3066). */ 1586 if (VOP_HAS_REG(vop, common, dma_stop)) 1587 VOP_REG_SET(vop, common, dma_stop, 0); 1588 1589 spin_unlock(&vop->reg_lock); 1590 1591 /* 1592 * There is a (rather unlikely) possiblity that a vblank interrupt 1593 * fired before we set the cfg_done bit. To avoid spuriously 1594 * signalling flip completion we need to wait for it to finish. 1595 */ 1596 vop_wait_for_irq_handler(vop); 1597 1598 spin_lock_irq(&crtc->dev->event_lock); 1599 if (crtc->state->event) { 1600 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1601 WARN_ON(vop->event); 1602 1603 vop->event = crtc->state->event; 1604 crtc->state->event = NULL; 1605 } 1606 spin_unlock_irq(&crtc->dev->event_lock); 1607 1608 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1609 new_plane_state, i) { 1610 if (!old_plane_state->fb) 1611 continue; 1612 1613 if (old_plane_state->fb == new_plane_state->fb) 1614 continue; 1615 1616 drm_framebuffer_get(old_plane_state->fb); 1617 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1618 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1619 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1620 } 1621 } 1622 1623 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1624 .mode_valid = vop_crtc_mode_valid, 1625 .mode_fixup = vop_crtc_mode_fixup, 1626 .atomic_check = vop_crtc_atomic_check, 1627 .atomic_begin = vop_crtc_atomic_begin, 1628 .atomic_flush = vop_crtc_atomic_flush, 1629 .atomic_enable = vop_crtc_atomic_enable, 1630 .atomic_disable = vop_crtc_atomic_disable, 1631 }; 1632 1633 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1634 { 1635 struct rockchip_crtc_state *rockchip_state; 1636 1637 if (WARN_ON(!crtc->state)) 1638 return NULL; 1639 1640 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), 1641 sizeof(*rockchip_state), GFP_KERNEL); 1642 if (!rockchip_state) 1643 return NULL; 1644 1645 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1646 return &rockchip_state->base; 1647 } 1648 1649 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1650 struct drm_crtc_state *state) 1651 { 1652 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1653 1654 __drm_atomic_helper_crtc_destroy_state(&s->base); 1655 kfree(s); 1656 } 1657 1658 static void vop_crtc_reset(struct drm_crtc *crtc) 1659 { 1660 struct rockchip_crtc_state *crtc_state = 1661 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1662 1663 if (crtc->state) 1664 vop_crtc_destroy_state(crtc, crtc->state); 1665 1666 if (crtc_state) 1667 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1668 else 1669 __drm_atomic_helper_crtc_reset(crtc, NULL); 1670 } 1671 1672 #ifdef CONFIG_DRM_ANALOGIX_DP 1673 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1674 { 1675 struct drm_connector *connector; 1676 struct drm_connector_list_iter conn_iter; 1677 1678 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1679 drm_for_each_connector_iter(connector, &conn_iter) { 1680 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1681 drm_connector_list_iter_end(&conn_iter); 1682 return connector; 1683 } 1684 } 1685 drm_connector_list_iter_end(&conn_iter); 1686 1687 return NULL; 1688 } 1689 1690 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1691 const char *source_name) 1692 { 1693 struct vop *vop = to_vop(crtc); 1694 struct drm_connector *connector; 1695 int ret; 1696 1697 connector = vop_get_edp_connector(vop); 1698 if (!connector) 1699 return -EINVAL; 1700 1701 if (source_name && strcmp(source_name, "auto") == 0) 1702 ret = analogix_dp_start_crc(connector); 1703 else if (!source_name) 1704 ret = analogix_dp_stop_crc(connector); 1705 else 1706 ret = -EINVAL; 1707 1708 return ret; 1709 } 1710 1711 static int 1712 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1713 size_t *values_cnt) 1714 { 1715 if (source_name && strcmp(source_name, "auto") != 0) 1716 return -EINVAL; 1717 1718 *values_cnt = 3; 1719 return 0; 1720 } 1721 1722 #else 1723 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1724 const char *source_name) 1725 { 1726 return -ENODEV; 1727 } 1728 1729 static int 1730 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1731 size_t *values_cnt) 1732 { 1733 return -ENODEV; 1734 } 1735 #endif 1736 1737 static const struct drm_crtc_funcs vop_crtc_funcs = { 1738 .set_config = drm_atomic_helper_set_config, 1739 .page_flip = drm_atomic_helper_page_flip, 1740 .destroy = drm_crtc_cleanup, 1741 .reset = vop_crtc_reset, 1742 .atomic_duplicate_state = vop_crtc_duplicate_state, 1743 .atomic_destroy_state = vop_crtc_destroy_state, 1744 .enable_vblank = vop_crtc_enable_vblank, 1745 .disable_vblank = vop_crtc_disable_vblank, 1746 .set_crc_source = vop_crtc_set_crc_source, 1747 .verify_crc_source = vop_crtc_verify_crc_source, 1748 }; 1749 1750 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1751 { 1752 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1753 struct drm_framebuffer *fb = val; 1754 1755 drm_crtc_vblank_put(&vop->crtc); 1756 drm_framebuffer_put(fb); 1757 } 1758 1759 static void vop_handle_vblank(struct vop *vop) 1760 { 1761 struct drm_device *drm = vop->drm_dev; 1762 struct drm_crtc *crtc = &vop->crtc; 1763 1764 spin_lock(&drm->event_lock); 1765 if (vop->event) { 1766 drm_crtc_send_vblank_event(crtc, vop->event); 1767 drm_crtc_vblank_put(crtc); 1768 vop->event = NULL; 1769 } 1770 spin_unlock(&drm->event_lock); 1771 1772 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1773 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1774 } 1775 1776 static irqreturn_t vop_isr(int irq, void *data) 1777 { 1778 struct vop *vop = data; 1779 struct drm_crtc *crtc = &vop->crtc; 1780 uint32_t active_irqs; 1781 int ret = IRQ_NONE; 1782 1783 /* 1784 * The irq is shared with the iommu. If the runtime-pm state of the 1785 * vop-device is disabled the irq has to be targeted at the iommu. 1786 */ 1787 if (!pm_runtime_get_if_in_use(vop->dev)) 1788 return IRQ_NONE; 1789 1790 if (vop_core_clks_enable(vop)) { 1791 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1792 goto out; 1793 } 1794 1795 /* 1796 * interrupt register has interrupt status, enable and clear bits, we 1797 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1798 */ 1799 spin_lock(&vop->irq_lock); 1800 1801 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1802 /* Clear all active interrupt sources */ 1803 if (active_irqs) 1804 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1805 1806 spin_unlock(&vop->irq_lock); 1807 1808 /* This is expected for vop iommu irqs, since the irq is shared */ 1809 if (!active_irqs) 1810 goto out_disable; 1811 1812 if (active_irqs & DSP_HOLD_VALID_INTR) { 1813 complete(&vop->dsp_hold_completion); 1814 active_irqs &= ~DSP_HOLD_VALID_INTR; 1815 ret = IRQ_HANDLED; 1816 } 1817 1818 if (active_irqs & LINE_FLAG_INTR) { 1819 complete(&vop->line_flag_completion); 1820 active_irqs &= ~LINE_FLAG_INTR; 1821 ret = IRQ_HANDLED; 1822 } 1823 1824 if (active_irqs & FS_INTR) { 1825 drm_crtc_handle_vblank(crtc); 1826 vop_handle_vblank(vop); 1827 active_irqs &= ~FS_INTR; 1828 ret = IRQ_HANDLED; 1829 } 1830 1831 /* Unhandled irqs are spurious. */ 1832 if (active_irqs) 1833 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1834 active_irqs); 1835 1836 out_disable: 1837 vop_core_clks_disable(vop); 1838 out: 1839 pm_runtime_put(vop->dev); 1840 return ret; 1841 } 1842 1843 static void vop_plane_add_properties(struct drm_plane *plane, 1844 const struct vop_win_data *win_data) 1845 { 1846 unsigned int flags = 0; 1847 1848 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1849 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1850 if (flags) 1851 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1852 DRM_MODE_ROTATE_0 | flags); 1853 } 1854 1855 static int vop_create_crtc(struct vop *vop) 1856 { 1857 const struct vop_data *vop_data = vop->data; 1858 struct device *dev = vop->dev; 1859 struct drm_device *drm_dev = vop->drm_dev; 1860 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1861 struct drm_crtc *crtc = &vop->crtc; 1862 struct device_node *port; 1863 int ret; 1864 int i; 1865 1866 /* 1867 * Create drm_plane for primary and cursor planes first, since we need 1868 * to pass them to drm_crtc_init_with_planes, which sets the 1869 * "possible_crtcs" to the newly initialized crtc. 1870 */ 1871 for (i = 0; i < vop_data->win_size; i++) { 1872 struct vop_win *vop_win = &vop->win[i]; 1873 const struct vop_win_data *win_data = vop_win->data; 1874 1875 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1876 win_data->type != DRM_PLANE_TYPE_CURSOR) 1877 continue; 1878 1879 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1880 0, &vop_plane_funcs, 1881 win_data->phy->data_formats, 1882 win_data->phy->nformats, 1883 win_data->phy->format_modifiers, 1884 win_data->type, NULL); 1885 if (ret) { 1886 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1887 ret); 1888 goto err_cleanup_planes; 1889 } 1890 1891 plane = &vop_win->base; 1892 drm_plane_helper_add(plane, &plane_helper_funcs); 1893 vop_plane_add_properties(plane, win_data); 1894 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1895 primary = plane; 1896 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1897 cursor = plane; 1898 } 1899 1900 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1901 &vop_crtc_funcs, NULL); 1902 if (ret) 1903 goto err_cleanup_planes; 1904 1905 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1906 if (vop->lut_regs) { 1907 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1908 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1909 } 1910 1911 /* 1912 * Create drm_planes for overlay windows with possible_crtcs restricted 1913 * to the newly created crtc. 1914 */ 1915 for (i = 0; i < vop_data->win_size; i++) { 1916 struct vop_win *vop_win = &vop->win[i]; 1917 const struct vop_win_data *win_data = vop_win->data; 1918 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1919 1920 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1921 continue; 1922 1923 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1924 possible_crtcs, 1925 &vop_plane_funcs, 1926 win_data->phy->data_formats, 1927 win_data->phy->nformats, 1928 win_data->phy->format_modifiers, 1929 win_data->type, NULL); 1930 if (ret) { 1931 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1932 ret); 1933 goto err_cleanup_crtc; 1934 } 1935 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1936 vop_plane_add_properties(&vop_win->base, win_data); 1937 } 1938 1939 port = of_get_child_by_name(dev->of_node, "port"); 1940 if (!port) { 1941 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1942 dev->of_node); 1943 ret = -ENOENT; 1944 goto err_cleanup_crtc; 1945 } 1946 1947 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1948 vop_fb_unref_worker); 1949 1950 init_completion(&vop->dsp_hold_completion); 1951 init_completion(&vop->line_flag_completion); 1952 crtc->port = port; 1953 1954 ret = drm_self_refresh_helper_init(crtc); 1955 if (ret) 1956 DRM_DEV_DEBUG_KMS(vop->dev, 1957 "Failed to init %s with SR helpers %d, ignoring\n", 1958 crtc->name, ret); 1959 1960 return 0; 1961 1962 err_cleanup_crtc: 1963 drm_crtc_cleanup(crtc); 1964 err_cleanup_planes: 1965 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1966 head) 1967 drm_plane_cleanup(plane); 1968 return ret; 1969 } 1970 1971 static void vop_destroy_crtc(struct vop *vop) 1972 { 1973 struct drm_crtc *crtc = &vop->crtc; 1974 struct drm_device *drm_dev = vop->drm_dev; 1975 struct drm_plane *plane, *tmp; 1976 1977 drm_self_refresh_helper_cleanup(crtc); 1978 1979 of_node_put(crtc->port); 1980 1981 /* 1982 * We need to cleanup the planes now. Why? 1983 * 1984 * The planes are "&vop->win[i].base". That means the memory is 1985 * all part of the big "struct vop" chunk of memory. That memory 1986 * was devm allocated and associated with this component. We need to 1987 * free it ourselves before vop_unbind() finishes. 1988 */ 1989 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1990 head) 1991 drm_plane_cleanup(plane); 1992 1993 /* 1994 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1995 * references the CRTC. 1996 */ 1997 drm_crtc_cleanup(crtc); 1998 drm_flip_work_cleanup(&vop->fb_unref_work); 1999 } 2000 2001 static int vop_initial(struct vop *vop) 2002 { 2003 struct reset_control *ahb_rst; 2004 int i, ret; 2005 2006 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 2007 if (IS_ERR(vop->hclk)) { 2008 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 2009 return PTR_ERR(vop->hclk); 2010 } 2011 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 2012 if (IS_ERR(vop->aclk)) { 2013 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 2014 return PTR_ERR(vop->aclk); 2015 } 2016 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 2017 if (IS_ERR(vop->dclk)) { 2018 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 2019 return PTR_ERR(vop->dclk); 2020 } 2021 2022 ret = pm_runtime_resume_and_get(vop->dev); 2023 if (ret < 0) { 2024 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 2025 return ret; 2026 } 2027 2028 ret = clk_prepare(vop->dclk); 2029 if (ret < 0) { 2030 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 2031 goto err_put_pm_runtime; 2032 } 2033 2034 /* Enable both the hclk and aclk to setup the vop */ 2035 ret = clk_prepare_enable(vop->hclk); 2036 if (ret < 0) { 2037 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 2038 goto err_unprepare_dclk; 2039 } 2040 2041 ret = clk_prepare_enable(vop->aclk); 2042 if (ret < 0) { 2043 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2044 goto err_disable_hclk; 2045 } 2046 2047 /* 2048 * do hclk_reset, reset all vop registers. 2049 */ 2050 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2051 if (IS_ERR(ahb_rst)) { 2052 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2053 ret = PTR_ERR(ahb_rst); 2054 goto err_disable_aclk; 2055 } 2056 reset_control_assert(ahb_rst); 2057 usleep_range(10, 20); 2058 reset_control_deassert(ahb_rst); 2059 2060 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2061 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2062 2063 for (i = 0; i < vop->len; i += sizeof(u32)) 2064 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2065 2066 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2067 VOP_REG_SET(vop, common, dsp_blank, 0); 2068 2069 for (i = 0; i < vop->data->win_size; i++) { 2070 struct vop_win *vop_win = &vop->win[i]; 2071 const struct vop_win_data *win = vop_win->data; 2072 int channel = i * 2 + 1; 2073 2074 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2075 vop_win_disable(vop, vop_win); 2076 VOP_WIN_SET(vop, win, gate, 1); 2077 } 2078 2079 vop_cfg_done(vop); 2080 2081 /* 2082 * do dclk_reset, let all config take affect. 2083 */ 2084 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2085 if (IS_ERR(vop->dclk_rst)) { 2086 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2087 ret = PTR_ERR(vop->dclk_rst); 2088 goto err_disable_aclk; 2089 } 2090 reset_control_assert(vop->dclk_rst); 2091 usleep_range(10, 20); 2092 reset_control_deassert(vop->dclk_rst); 2093 2094 clk_disable(vop->hclk); 2095 clk_disable(vop->aclk); 2096 2097 vop->is_enabled = false; 2098 2099 pm_runtime_put_sync(vop->dev); 2100 2101 return 0; 2102 2103 err_disable_aclk: 2104 clk_disable_unprepare(vop->aclk); 2105 err_disable_hclk: 2106 clk_disable_unprepare(vop->hclk); 2107 err_unprepare_dclk: 2108 clk_unprepare(vop->dclk); 2109 err_put_pm_runtime: 2110 pm_runtime_put_sync(vop->dev); 2111 return ret; 2112 } 2113 2114 /* 2115 * Initialize the vop->win array elements. 2116 */ 2117 static void vop_win_init(struct vop *vop) 2118 { 2119 const struct vop_data *vop_data = vop->data; 2120 unsigned int i; 2121 2122 for (i = 0; i < vop_data->win_size; i++) { 2123 struct vop_win *vop_win = &vop->win[i]; 2124 const struct vop_win_data *win_data = &vop_data->win[i]; 2125 2126 vop_win->data = win_data; 2127 vop_win->vop = vop; 2128 2129 if (vop_data->win_yuv2yuv) 2130 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2131 } 2132 } 2133 2134 /** 2135 * rockchip_drm_wait_vact_end 2136 * @crtc: CRTC to enable line flag 2137 * @mstimeout: millisecond for timeout 2138 * 2139 * Wait for vact_end line flag irq or timeout. 2140 * 2141 * Returns: 2142 * Zero on success, negative errno on failure. 2143 */ 2144 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2145 { 2146 struct vop *vop = to_vop(crtc); 2147 unsigned long jiffies_left; 2148 int ret = 0; 2149 2150 if (!crtc || !vop->is_enabled) 2151 return -ENODEV; 2152 2153 mutex_lock(&vop->vop_lock); 2154 if (mstimeout <= 0) { 2155 ret = -EINVAL; 2156 goto out; 2157 } 2158 2159 if (vop_line_flag_irq_is_enabled(vop)) { 2160 ret = -EBUSY; 2161 goto out; 2162 } 2163 2164 reinit_completion(&vop->line_flag_completion); 2165 vop_line_flag_irq_enable(vop); 2166 2167 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2168 msecs_to_jiffies(mstimeout)); 2169 vop_line_flag_irq_disable(vop); 2170 2171 if (jiffies_left == 0) { 2172 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2173 ret = -ETIMEDOUT; 2174 goto out; 2175 } 2176 2177 out: 2178 mutex_unlock(&vop->vop_lock); 2179 return ret; 2180 } 2181 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2182 2183 static int vop_bind(struct device *dev, struct device *master, void *data) 2184 { 2185 struct platform_device *pdev = to_platform_device(dev); 2186 const struct vop_data *vop_data; 2187 struct drm_device *drm_dev = data; 2188 struct vop *vop; 2189 struct resource *res; 2190 int ret, irq; 2191 2192 vop_data = of_device_get_match_data(dev); 2193 if (!vop_data) 2194 return -ENODEV; 2195 2196 /* Allocate vop struct and its vop_win array */ 2197 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2198 GFP_KERNEL); 2199 if (!vop) 2200 return -ENOMEM; 2201 2202 vop->dev = dev; 2203 vop->data = vop_data; 2204 vop->drm_dev = drm_dev; 2205 dev_set_drvdata(dev, vop); 2206 2207 vop_win_init(vop); 2208 2209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2210 vop->regs = devm_ioremap_resource(dev, res); 2211 if (IS_ERR(vop->regs)) 2212 return PTR_ERR(vop->regs); 2213 vop->len = resource_size(res); 2214 2215 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2216 if (res) { 2217 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2218 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2219 return -EINVAL; 2220 } 2221 vop->lut_regs = devm_ioremap_resource(dev, res); 2222 if (IS_ERR(vop->lut_regs)) 2223 return PTR_ERR(vop->lut_regs); 2224 } 2225 2226 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2227 if (!vop->regsbak) 2228 return -ENOMEM; 2229 2230 irq = platform_get_irq(pdev, 0); 2231 if (irq < 0) { 2232 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2233 return irq; 2234 } 2235 vop->irq = (unsigned int)irq; 2236 2237 spin_lock_init(&vop->reg_lock); 2238 spin_lock_init(&vop->irq_lock); 2239 mutex_init(&vop->vop_lock); 2240 2241 ret = vop_create_crtc(vop); 2242 if (ret) 2243 return ret; 2244 2245 pm_runtime_enable(&pdev->dev); 2246 2247 ret = vop_initial(vop); 2248 if (ret < 0) { 2249 DRM_DEV_ERROR(&pdev->dev, 2250 "cannot initial vop dev - err %d\n", ret); 2251 goto err_disable_pm_runtime; 2252 } 2253 2254 ret = devm_request_irq(dev, vop->irq, vop_isr, 2255 IRQF_SHARED, dev_name(dev), vop); 2256 if (ret) 2257 goto err_disable_pm_runtime; 2258 2259 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2260 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); 2261 if (IS_ERR(vop->rgb)) { 2262 ret = PTR_ERR(vop->rgb); 2263 goto err_disable_pm_runtime; 2264 } 2265 } 2266 2267 rockchip_drm_dma_init_device(drm_dev, dev); 2268 2269 return 0; 2270 2271 err_disable_pm_runtime: 2272 pm_runtime_disable(&pdev->dev); 2273 vop_destroy_crtc(vop); 2274 return ret; 2275 } 2276 2277 static void vop_unbind(struct device *dev, struct device *master, void *data) 2278 { 2279 struct vop *vop = dev_get_drvdata(dev); 2280 2281 if (vop->rgb) 2282 rockchip_rgb_fini(vop->rgb); 2283 2284 pm_runtime_disable(dev); 2285 vop_destroy_crtc(vop); 2286 2287 clk_unprepare(vop->aclk); 2288 clk_unprepare(vop->hclk); 2289 clk_unprepare(vop->dclk); 2290 } 2291 2292 const struct component_ops vop_component_ops = { 2293 .bind = vop_bind, 2294 .unbind = vop_unbind, 2295 }; 2296 EXPORT_SYMBOL_GPL(vop_component_ops); 2297