1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_crtc_helper.h> 19 #include <drm/drm_plane_helper.h> 20 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/clk.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/component.h> 29 30 #include <linux/reset.h> 31 #include <linux/delay.h> 32 33 #include "rockchip_drm_drv.h" 34 #include "rockchip_drm_gem.h" 35 #include "rockchip_drm_fb.h" 36 #include "rockchip_drm_vop.h" 37 38 #define VOP_REG(off, _mask, s) \ 39 {.offset = off, \ 40 .mask = _mask, \ 41 .shift = s,} 42 43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 46 vop_mask_write(x, off, (mask) << shift, (v) << shift) 47 48 #define REG_SET(x, base, reg, v, mode) \ 49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 50 51 #define VOP_WIN_SET(x, win, name, v) \ 52 REG_SET(x, win->base, win->phy->name, v, RELAXED) 53 #define VOP_SCL_SET(x, win, name, v) \ 54 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 55 #define VOP_CTRL_SET(x, name, v) \ 56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 57 58 #define VOP_WIN_GET(x, win, name) \ 59 vop_read_reg(x, win->base, &win->phy->name) 60 61 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 62 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 63 64 #define to_vop(x) container_of(x, struct vop, crtc) 65 #define to_vop_win(x) container_of(x, struct vop_win, base) 66 67 struct vop_win_state { 68 struct list_head head; 69 struct drm_framebuffer *fb; 70 dma_addr_t yrgb_mst; 71 struct drm_pending_vblank_event *event; 72 }; 73 74 struct vop_win { 75 struct drm_plane base; 76 const struct vop_win_data *data; 77 struct vop *vop; 78 79 struct list_head pending; 80 struct vop_win_state *active; 81 }; 82 83 struct vop { 84 struct drm_crtc crtc; 85 struct device *dev; 86 struct drm_device *drm_dev; 87 bool is_enabled; 88 89 int connector_type; 90 int connector_out_mode; 91 92 /* mutex vsync_ work */ 93 struct mutex vsync_mutex; 94 bool vsync_work_pending; 95 struct completion dsp_hold_completion; 96 97 const struct vop_data *data; 98 99 uint32_t *regsbak; 100 void __iomem *regs; 101 102 /* physical map length of vop register */ 103 uint32_t len; 104 105 /* one time only one process allowed to config the register */ 106 spinlock_t reg_lock; 107 /* lock vop irq reg */ 108 spinlock_t irq_lock; 109 110 unsigned int irq; 111 112 /* vop AHP clk */ 113 struct clk *hclk; 114 /* vop dclk */ 115 struct clk *dclk; 116 /* vop share memory frequency */ 117 struct clk *aclk; 118 119 /* vop dclk reset */ 120 struct reset_control *dclk_rst; 121 122 int pipe; 123 124 struct vop_win win[]; 125 }; 126 127 enum vop_data_format { 128 VOP_FMT_ARGB8888 = 0, 129 VOP_FMT_RGB888, 130 VOP_FMT_RGB565, 131 VOP_FMT_YUV420SP = 4, 132 VOP_FMT_YUV422SP, 133 VOP_FMT_YUV444SP, 134 }; 135 136 struct vop_reg_data { 137 uint32_t offset; 138 uint32_t value; 139 }; 140 141 struct vop_reg { 142 uint32_t offset; 143 uint32_t shift; 144 uint32_t mask; 145 }; 146 147 struct vop_ctrl { 148 struct vop_reg standby; 149 struct vop_reg data_blank; 150 struct vop_reg gate_en; 151 struct vop_reg mmu_en; 152 struct vop_reg rgb_en; 153 struct vop_reg edp_en; 154 struct vop_reg hdmi_en; 155 struct vop_reg mipi_en; 156 struct vop_reg out_mode; 157 struct vop_reg dither_down; 158 struct vop_reg dither_up; 159 struct vop_reg pin_pol; 160 161 struct vop_reg htotal_pw; 162 struct vop_reg hact_st_end; 163 struct vop_reg vtotal_pw; 164 struct vop_reg vact_st_end; 165 struct vop_reg hpost_st_end; 166 struct vop_reg vpost_st_end; 167 }; 168 169 struct vop_scl_regs { 170 struct vop_reg cbcr_vsd_mode; 171 struct vop_reg cbcr_vsu_mode; 172 struct vop_reg cbcr_hsd_mode; 173 struct vop_reg cbcr_ver_scl_mode; 174 struct vop_reg cbcr_hor_scl_mode; 175 struct vop_reg yrgb_vsd_mode; 176 struct vop_reg yrgb_vsu_mode; 177 struct vop_reg yrgb_hsd_mode; 178 struct vop_reg yrgb_ver_scl_mode; 179 struct vop_reg yrgb_hor_scl_mode; 180 struct vop_reg line_load_mode; 181 struct vop_reg cbcr_axi_gather_num; 182 struct vop_reg yrgb_axi_gather_num; 183 struct vop_reg vsd_cbcr_gt2; 184 struct vop_reg vsd_cbcr_gt4; 185 struct vop_reg vsd_yrgb_gt2; 186 struct vop_reg vsd_yrgb_gt4; 187 struct vop_reg bic_coe_sel; 188 struct vop_reg cbcr_axi_gather_en; 189 struct vop_reg yrgb_axi_gather_en; 190 191 struct vop_reg lb_mode; 192 struct vop_reg scale_yrgb_x; 193 struct vop_reg scale_yrgb_y; 194 struct vop_reg scale_cbcr_x; 195 struct vop_reg scale_cbcr_y; 196 }; 197 198 struct vop_win_phy { 199 const struct vop_scl_regs *scl; 200 const uint32_t *data_formats; 201 uint32_t nformats; 202 203 struct vop_reg enable; 204 struct vop_reg format; 205 struct vop_reg rb_swap; 206 struct vop_reg act_info; 207 struct vop_reg dsp_info; 208 struct vop_reg dsp_st; 209 struct vop_reg yrgb_mst; 210 struct vop_reg uv_mst; 211 struct vop_reg yrgb_vir; 212 struct vop_reg uv_vir; 213 214 struct vop_reg dst_alpha_ctl; 215 struct vop_reg src_alpha_ctl; 216 }; 217 218 struct vop_win_data { 219 uint32_t base; 220 const struct vop_win_phy *phy; 221 enum drm_plane_type type; 222 }; 223 224 struct vop_data { 225 const struct vop_reg_data *init_table; 226 unsigned int table_size; 227 const struct vop_ctrl *ctrl; 228 const struct vop_win_data *win; 229 unsigned int win_size; 230 }; 231 232 static const uint32_t formats_01[] = { 233 DRM_FORMAT_XRGB8888, 234 DRM_FORMAT_ARGB8888, 235 DRM_FORMAT_XBGR8888, 236 DRM_FORMAT_ABGR8888, 237 DRM_FORMAT_RGB888, 238 DRM_FORMAT_BGR888, 239 DRM_FORMAT_RGB565, 240 DRM_FORMAT_BGR565, 241 DRM_FORMAT_NV12, 242 DRM_FORMAT_NV16, 243 DRM_FORMAT_NV24, 244 }; 245 246 static const uint32_t formats_234[] = { 247 DRM_FORMAT_XRGB8888, 248 DRM_FORMAT_ARGB8888, 249 DRM_FORMAT_XBGR8888, 250 DRM_FORMAT_ABGR8888, 251 DRM_FORMAT_RGB888, 252 DRM_FORMAT_BGR888, 253 DRM_FORMAT_RGB565, 254 DRM_FORMAT_BGR565, 255 }; 256 257 static const struct vop_scl_regs win_full_scl = { 258 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), 259 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), 260 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), 261 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), 262 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), 263 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), 264 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), 265 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), 266 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), 267 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), 268 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), 269 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), 270 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), 271 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), 272 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), 273 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), 274 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), 275 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), 276 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), 277 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), 278 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), 279 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 280 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 281 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 282 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), 283 }; 284 285 static const struct vop_win_phy win01_data = { 286 .scl = &win_full_scl, 287 .data_formats = formats_01, 288 .nformats = ARRAY_SIZE(formats_01), 289 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 290 .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 291 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12), 292 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 293 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 294 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 295 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 296 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 297 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 298 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 299 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 300 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 301 }; 302 303 static const struct vop_win_phy win23_data = { 304 .data_formats = formats_234, 305 .nformats = ARRAY_SIZE(formats_234), 306 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 307 .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 308 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12), 309 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 310 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 311 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 312 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 313 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 314 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 315 }; 316 317 static const struct vop_ctrl ctrl_data = { 318 .standby = VOP_REG(SYS_CTRL, 0x1, 22), 319 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 320 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 321 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 322 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 323 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 324 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 325 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 326 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 327 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 328 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 329 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 330 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 331 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 332 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 333 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 334 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 335 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 336 }; 337 338 static const struct vop_reg_data vop_init_reg_table[] = { 339 {SYS_CTRL, 0x00c00000}, 340 {DSP_CTRL0, 0x00000000}, 341 {WIN0_CTRL0, 0x00000080}, 342 {WIN1_CTRL0, 0x00000080}, 343 /* TODO: Win2/3 support multiple area function, but we haven't found 344 * a suitable way to use it yet, so let's just use them as other windows 345 * with only area 0 enabled. 346 */ 347 {WIN2_CTRL0, 0x00000010}, 348 {WIN3_CTRL0, 0x00000010}, 349 }; 350 351 /* 352 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 353 * special support to get alpha blending working. For now, just use overlay 354 * window 3 for the drm cursor. 355 * 356 */ 357 static const struct vop_win_data rk3288_vop_win_data[] = { 358 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 359 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, 360 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 361 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, 362 }; 363 364 static const struct vop_data rk3288_vop = { 365 .init_table = vop_init_reg_table, 366 .table_size = ARRAY_SIZE(vop_init_reg_table), 367 .ctrl = &ctrl_data, 368 .win = rk3288_vop_win_data, 369 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 370 }; 371 372 static const struct of_device_id vop_driver_dt_match[] = { 373 { .compatible = "rockchip,rk3288-vop", 374 .data = &rk3288_vop }, 375 {}, 376 }; 377 378 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 379 { 380 writel(v, vop->regs + offset); 381 vop->regsbak[offset >> 2] = v; 382 } 383 384 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 385 { 386 return readl(vop->regs + offset); 387 } 388 389 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 390 const struct vop_reg *reg) 391 { 392 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 393 } 394 395 static inline void vop_cfg_done(struct vop *vop) 396 { 397 writel(0x01, vop->regs + REG_CFG_DONE); 398 } 399 400 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 401 uint32_t mask, uint32_t v) 402 { 403 if (mask) { 404 uint32_t cached_val = vop->regsbak[offset >> 2]; 405 406 cached_val = (cached_val & ~mask) | v; 407 writel(cached_val, vop->regs + offset); 408 vop->regsbak[offset >> 2] = cached_val; 409 } 410 } 411 412 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 413 uint32_t mask, uint32_t v) 414 { 415 if (mask) { 416 uint32_t cached_val = vop->regsbak[offset >> 2]; 417 418 cached_val = (cached_val & ~mask) | v; 419 writel_relaxed(cached_val, vop->regs + offset); 420 vop->regsbak[offset >> 2] = cached_val; 421 } 422 } 423 424 static bool has_rb_swapped(uint32_t format) 425 { 426 switch (format) { 427 case DRM_FORMAT_XBGR8888: 428 case DRM_FORMAT_ABGR8888: 429 case DRM_FORMAT_BGR888: 430 case DRM_FORMAT_BGR565: 431 return true; 432 default: 433 return false; 434 } 435 } 436 437 static enum vop_data_format vop_convert_format(uint32_t format) 438 { 439 switch (format) { 440 case DRM_FORMAT_XRGB8888: 441 case DRM_FORMAT_ARGB8888: 442 case DRM_FORMAT_XBGR8888: 443 case DRM_FORMAT_ABGR8888: 444 return VOP_FMT_ARGB8888; 445 case DRM_FORMAT_RGB888: 446 case DRM_FORMAT_BGR888: 447 return VOP_FMT_RGB888; 448 case DRM_FORMAT_RGB565: 449 case DRM_FORMAT_BGR565: 450 return VOP_FMT_RGB565; 451 case DRM_FORMAT_NV12: 452 return VOP_FMT_YUV420SP; 453 case DRM_FORMAT_NV16: 454 return VOP_FMT_YUV422SP; 455 case DRM_FORMAT_NV24: 456 return VOP_FMT_YUV444SP; 457 default: 458 DRM_ERROR("unsupport format[%08x]\n", format); 459 return -EINVAL; 460 } 461 } 462 463 static bool is_yuv_support(uint32_t format) 464 { 465 switch (format) { 466 case DRM_FORMAT_NV12: 467 case DRM_FORMAT_NV16: 468 case DRM_FORMAT_NV24: 469 return true; 470 default: 471 return false; 472 } 473 } 474 475 static bool is_alpha_support(uint32_t format) 476 { 477 switch (format) { 478 case DRM_FORMAT_ARGB8888: 479 case DRM_FORMAT_ABGR8888: 480 return true; 481 default: 482 return false; 483 } 484 } 485 486 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 487 uint32_t dst, bool is_horizontal, 488 int vsu_mode, int *vskiplines) 489 { 490 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 491 492 if (is_horizontal) { 493 if (mode == SCALE_UP) 494 val = GET_SCL_FT_BIC(src, dst); 495 else if (mode == SCALE_DOWN) 496 val = GET_SCL_FT_BILI_DN(src, dst); 497 } else { 498 if (mode == SCALE_UP) { 499 if (vsu_mode == SCALE_UP_BIL) 500 val = GET_SCL_FT_BILI_UP(src, dst); 501 else 502 val = GET_SCL_FT_BIC(src, dst); 503 } else if (mode == SCALE_DOWN) { 504 if (vskiplines) { 505 *vskiplines = scl_get_vskiplines(src, dst); 506 val = scl_get_bili_dn_vskip(src, dst, 507 *vskiplines); 508 } else { 509 val = GET_SCL_FT_BILI_DN(src, dst); 510 } 511 } 512 } 513 514 return val; 515 } 516 517 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 518 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 519 uint32_t dst_h, uint32_t pixel_format) 520 { 521 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 522 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 523 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 524 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 525 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 526 bool is_yuv = is_yuv_support(pixel_format); 527 uint16_t cbcr_src_w = src_w / hsub; 528 uint16_t cbcr_src_h = src_h / vsub; 529 uint16_t vsu_mode; 530 uint16_t lb_mode; 531 uint32_t val; 532 int vskiplines; 533 534 if (dst_w > 3840) { 535 DRM_ERROR("Maximum destination width (3840) exceeded\n"); 536 return; 537 } 538 539 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 540 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 541 542 if (is_yuv) { 543 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 544 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 545 if (cbcr_hor_scl_mode == SCALE_DOWN) 546 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 547 else 548 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 549 } else { 550 if (yrgb_hor_scl_mode == SCALE_DOWN) 551 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 552 else 553 lb_mode = scl_vop_cal_lb_mode(src_w, false); 554 } 555 556 VOP_SCL_SET(vop, win, lb_mode, lb_mode); 557 if (lb_mode == LB_RGB_3840X2) { 558 if (yrgb_ver_scl_mode != SCALE_NONE) { 559 DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 560 return; 561 } 562 if (cbcr_ver_scl_mode != SCALE_NONE) { 563 DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 564 return; 565 } 566 vsu_mode = SCALE_UP_BIL; 567 } else if (lb_mode == LB_RGB_2560X4) { 568 vsu_mode = SCALE_UP_BIL; 569 } else { 570 vsu_mode = SCALE_UP_BIC; 571 } 572 573 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 574 true, 0, NULL); 575 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 576 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 577 false, vsu_mode, &vskiplines); 578 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 579 580 VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); 581 VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); 582 583 VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 584 VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 585 VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 586 VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 587 VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); 588 if (is_yuv) { 589 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 590 dst_w, true, 0, NULL); 591 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 592 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 593 dst_h, false, vsu_mode, &vskiplines); 594 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 595 596 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); 597 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); 598 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 599 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 600 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 601 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 602 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); 603 } 604 } 605 606 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 607 { 608 unsigned long flags; 609 610 if (WARN_ON(!vop->is_enabled)) 611 return; 612 613 spin_lock_irqsave(&vop->irq_lock, flags); 614 615 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 616 DSP_HOLD_VALID_INTR_EN(1)); 617 618 spin_unlock_irqrestore(&vop->irq_lock, flags); 619 } 620 621 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 622 { 623 unsigned long flags; 624 625 if (WARN_ON(!vop->is_enabled)) 626 return; 627 628 spin_lock_irqsave(&vop->irq_lock, flags); 629 630 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, 631 DSP_HOLD_VALID_INTR_EN(0)); 632 633 spin_unlock_irqrestore(&vop->irq_lock, flags); 634 } 635 636 static void vop_enable(struct drm_crtc *crtc) 637 { 638 struct vop *vop = to_vop(crtc); 639 int ret; 640 641 if (vop->is_enabled) 642 return; 643 644 ret = pm_runtime_get_sync(vop->dev); 645 if (ret < 0) { 646 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 647 return; 648 } 649 650 ret = clk_enable(vop->hclk); 651 if (ret < 0) { 652 dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 653 return; 654 } 655 656 ret = clk_enable(vop->dclk); 657 if (ret < 0) { 658 dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 659 goto err_disable_hclk; 660 } 661 662 ret = clk_enable(vop->aclk); 663 if (ret < 0) { 664 dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 665 goto err_disable_dclk; 666 } 667 668 /* 669 * Slave iommu shares power, irq and clock with vop. It was associated 670 * automatically with this master device via common driver code. 671 * Now that we have enabled the clock we attach it to the shared drm 672 * mapping. 673 */ 674 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 675 if (ret) { 676 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 677 goto err_disable_aclk; 678 } 679 680 memcpy(vop->regs, vop->regsbak, vop->len); 681 /* 682 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 683 */ 684 vop->is_enabled = true; 685 686 spin_lock(&vop->reg_lock); 687 688 VOP_CTRL_SET(vop, standby, 0); 689 690 spin_unlock(&vop->reg_lock); 691 692 enable_irq(vop->irq); 693 694 drm_vblank_on(vop->drm_dev, vop->pipe); 695 696 return; 697 698 err_disable_aclk: 699 clk_disable(vop->aclk); 700 err_disable_dclk: 701 clk_disable(vop->dclk); 702 err_disable_hclk: 703 clk_disable(vop->hclk); 704 } 705 706 static void vop_disable(struct drm_crtc *crtc) 707 { 708 struct vop *vop = to_vop(crtc); 709 710 if (!vop->is_enabled) 711 return; 712 713 drm_vblank_off(crtc->dev, vop->pipe); 714 715 /* 716 * Vop standby will take effect at end of current frame, 717 * if dsp hold valid irq happen, it means standby complete. 718 * 719 * we must wait standby complete when we want to disable aclk, 720 * if not, memory bus maybe dead. 721 */ 722 reinit_completion(&vop->dsp_hold_completion); 723 vop_dsp_hold_valid_irq_enable(vop); 724 725 spin_lock(&vop->reg_lock); 726 727 VOP_CTRL_SET(vop, standby, 1); 728 729 spin_unlock(&vop->reg_lock); 730 731 wait_for_completion(&vop->dsp_hold_completion); 732 733 vop_dsp_hold_valid_irq_disable(vop); 734 735 disable_irq(vop->irq); 736 737 vop->is_enabled = false; 738 739 /* 740 * vop standby complete, so iommu detach is safe. 741 */ 742 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 743 744 clk_disable(vop->dclk); 745 clk_disable(vop->aclk); 746 clk_disable(vop->hclk); 747 pm_runtime_put(vop->dev); 748 } 749 750 /* 751 * Caller must hold vsync_mutex. 752 */ 753 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win) 754 { 755 struct vop_win_state *last; 756 struct vop_win_state *active = vop_win->active; 757 758 if (list_empty(&vop_win->pending)) 759 return active ? active->fb : NULL; 760 761 last = list_last_entry(&vop_win->pending, struct vop_win_state, head); 762 return last ? last->fb : NULL; 763 } 764 765 /* 766 * Caller must hold vsync_mutex. 767 */ 768 static int vop_win_queue_fb(struct vop_win *vop_win, 769 struct drm_framebuffer *fb, dma_addr_t yrgb_mst, 770 struct drm_pending_vblank_event *event) 771 { 772 struct vop_win_state *state; 773 774 state = kzalloc(sizeof(*state), GFP_KERNEL); 775 if (!state) 776 return -ENOMEM; 777 778 state->fb = fb; 779 state->yrgb_mst = yrgb_mst; 780 state->event = event; 781 782 list_add_tail(&state->head, &vop_win->pending); 783 784 return 0; 785 } 786 787 static int vop_update_plane_event(struct drm_plane *plane, 788 struct drm_crtc *crtc, 789 struct drm_framebuffer *fb, int crtc_x, 790 int crtc_y, unsigned int crtc_w, 791 unsigned int crtc_h, uint32_t src_x, 792 uint32_t src_y, uint32_t src_w, 793 uint32_t src_h, 794 struct drm_pending_vblank_event *event) 795 { 796 struct vop_win *vop_win = to_vop_win(plane); 797 const struct vop_win_data *win = vop_win->data; 798 struct vop *vop = to_vop(crtc); 799 struct drm_gem_object *obj; 800 struct rockchip_gem_object *rk_obj; 801 struct drm_gem_object *uv_obj; 802 struct rockchip_gem_object *rk_uv_obj; 803 unsigned long offset; 804 unsigned int actual_w; 805 unsigned int actual_h; 806 unsigned int dsp_stx; 807 unsigned int dsp_sty; 808 unsigned int y_vir_stride; 809 unsigned int uv_vir_stride = 0; 810 dma_addr_t yrgb_mst; 811 dma_addr_t uv_mst = 0; 812 enum vop_data_format format; 813 uint32_t val; 814 bool is_alpha; 815 bool rb_swap; 816 bool is_yuv; 817 bool visible; 818 int ret; 819 struct drm_rect dest = { 820 .x1 = crtc_x, 821 .y1 = crtc_y, 822 .x2 = crtc_x + crtc_w, 823 .y2 = crtc_y + crtc_h, 824 }; 825 struct drm_rect src = { 826 /* 16.16 fixed point */ 827 .x1 = src_x, 828 .y1 = src_y, 829 .x2 = src_x + src_w, 830 .y2 = src_y + src_h, 831 }; 832 const struct drm_rect clip = { 833 .x2 = crtc->mode.hdisplay, 834 .y2 = crtc->mode.vdisplay, 835 }; 836 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; 837 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 838 DRM_PLANE_HELPER_NO_SCALING; 839 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 840 DRM_PLANE_HELPER_NO_SCALING; 841 842 ret = drm_plane_helper_check_update(plane, crtc, fb, 843 &src, &dest, &clip, 844 min_scale, 845 max_scale, 846 can_position, false, &visible); 847 if (ret) 848 return ret; 849 850 if (!visible) 851 return 0; 852 853 is_alpha = is_alpha_support(fb->pixel_format); 854 rb_swap = has_rb_swapped(fb->pixel_format); 855 is_yuv = is_yuv_support(fb->pixel_format); 856 857 format = vop_convert_format(fb->pixel_format); 858 if (format < 0) 859 return format; 860 861 obj = rockchip_fb_get_gem_obj(fb, 0); 862 if (!obj) { 863 DRM_ERROR("fail to get rockchip gem object from framebuffer\n"); 864 return -EINVAL; 865 } 866 867 rk_obj = to_rockchip_obj(obj); 868 869 if (is_yuv) { 870 /* 871 * Src.x1 can be odd when do clip, but yuv plane start point 872 * need align with 2 pixel. 873 */ 874 val = (src.x1 >> 16) % 2; 875 src.x1 += val << 16; 876 src.x2 += val << 16; 877 } 878 879 actual_w = (src.x2 - src.x1) >> 16; 880 actual_h = (src.y2 - src.y1) >> 16; 881 882 dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start; 883 dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 884 885 offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 886 offset += (src.y1 >> 16) * fb->pitches[0]; 887 888 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 889 y_vir_stride = fb->pitches[0] >> 2; 890 891 if (is_yuv) { 892 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 893 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 894 int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 895 896 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 897 if (!uv_obj) { 898 DRM_ERROR("fail to get uv object from framebuffer\n"); 899 return -EINVAL; 900 } 901 rk_uv_obj = to_rockchip_obj(uv_obj); 902 uv_vir_stride = fb->pitches[1] >> 2; 903 904 offset = (src.x1 >> 16) * bpp / hsub; 905 offset += (src.y1 >> 16) * fb->pitches[1] / vsub; 906 907 uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 908 } 909 910 /* 911 * If this plane update changes the plane's framebuffer, (or more 912 * precisely, if this update has a different framebuffer than the last 913 * update), enqueue it so we can track when it completes. 914 * 915 * Only when we discover that this update has completed, can we 916 * unreference any previous framebuffers. 917 */ 918 mutex_lock(&vop->vsync_mutex); 919 if (fb != vop_win_last_pending_fb(vop_win)) { 920 ret = drm_vblank_get(plane->dev, vop->pipe); 921 if (ret) { 922 DRM_ERROR("failed to get vblank, %d\n", ret); 923 mutex_unlock(&vop->vsync_mutex); 924 return ret; 925 } 926 927 drm_framebuffer_reference(fb); 928 929 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event); 930 if (ret) { 931 drm_vblank_put(plane->dev, vop->pipe); 932 mutex_unlock(&vop->vsync_mutex); 933 return ret; 934 } 935 936 vop->vsync_work_pending = true; 937 } 938 mutex_unlock(&vop->vsync_mutex); 939 940 spin_lock(&vop->reg_lock); 941 942 VOP_WIN_SET(vop, win, format, format); 943 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); 944 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); 945 if (is_yuv) { 946 VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); 947 VOP_WIN_SET(vop, win, uv_mst, uv_mst); 948 } 949 950 if (win->phy->scl) 951 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 952 dest.x2 - dest.x1, dest.y2 - dest.y1, 953 fb->pixel_format); 954 955 val = (actual_h - 1) << 16; 956 val |= (actual_w - 1) & 0xffff; 957 VOP_WIN_SET(vop, win, act_info, val); 958 959 val = (dest.y2 - dest.y1 - 1) << 16; 960 val |= (dest.x2 - dest.x1 - 1) & 0xffff; 961 VOP_WIN_SET(vop, win, dsp_info, val); 962 val = (dsp_sty - 1) << 16; 963 val |= (dsp_stx - 1) & 0xffff; 964 VOP_WIN_SET(vop, win, dsp_st, val); 965 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 966 967 if (is_alpha) { 968 VOP_WIN_SET(vop, win, dst_alpha_ctl, 969 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 970 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 971 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 972 SRC_BLEND_M0(ALPHA_PER_PIX) | 973 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 974 SRC_FACTOR_M0(ALPHA_ONE); 975 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 976 } else { 977 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 978 } 979 980 VOP_WIN_SET(vop, win, enable, 1); 981 982 vop_cfg_done(vop); 983 spin_unlock(&vop->reg_lock); 984 985 return 0; 986 } 987 988 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 989 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 990 unsigned int crtc_w, unsigned int crtc_h, 991 uint32_t src_x, uint32_t src_y, uint32_t src_w, 992 uint32_t src_h) 993 { 994 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w, 995 crtc_h, src_x, src_y, src_w, src_h, 996 NULL); 997 } 998 999 static int vop_update_primary_plane(struct drm_crtc *crtc, 1000 struct drm_pending_vblank_event *event) 1001 { 1002 unsigned int crtc_w, crtc_h; 1003 1004 crtc_w = crtc->primary->fb->width - crtc->x; 1005 crtc_h = crtc->primary->fb->height - crtc->y; 1006 1007 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb, 1008 0, 0, crtc_w, crtc_h, crtc->x << 16, 1009 crtc->y << 16, crtc_w << 16, 1010 crtc_h << 16, event); 1011 } 1012 1013 static int vop_disable_plane(struct drm_plane *plane) 1014 { 1015 struct vop_win *vop_win = to_vop_win(plane); 1016 const struct vop_win_data *win = vop_win->data; 1017 struct vop *vop; 1018 int ret; 1019 1020 if (!plane->crtc) 1021 return 0; 1022 1023 vop = to_vop(plane->crtc); 1024 1025 ret = drm_vblank_get(plane->dev, vop->pipe); 1026 if (ret) { 1027 DRM_ERROR("failed to get vblank, %d\n", ret); 1028 return ret; 1029 } 1030 1031 mutex_lock(&vop->vsync_mutex); 1032 1033 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL); 1034 if (ret) { 1035 drm_vblank_put(plane->dev, vop->pipe); 1036 mutex_unlock(&vop->vsync_mutex); 1037 return ret; 1038 } 1039 1040 vop->vsync_work_pending = true; 1041 mutex_unlock(&vop->vsync_mutex); 1042 1043 spin_lock(&vop->reg_lock); 1044 VOP_WIN_SET(vop, win, enable, 0); 1045 vop_cfg_done(vop); 1046 spin_unlock(&vop->reg_lock); 1047 1048 return 0; 1049 } 1050 1051 static void vop_plane_destroy(struct drm_plane *plane) 1052 { 1053 vop_disable_plane(plane); 1054 drm_plane_cleanup(plane); 1055 } 1056 1057 static const struct drm_plane_funcs vop_plane_funcs = { 1058 .update_plane = vop_update_plane, 1059 .disable_plane = vop_disable_plane, 1060 .destroy = vop_plane_destroy, 1061 }; 1062 1063 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 1064 int connector_type, 1065 int out_mode) 1066 { 1067 struct vop *vop = to_vop(crtc); 1068 1069 vop->connector_type = connector_type; 1070 vop->connector_out_mode = out_mode; 1071 1072 return 0; 1073 } 1074 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config); 1075 1076 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1077 { 1078 struct vop *vop = to_vop(crtc); 1079 unsigned long flags; 1080 1081 if (!vop->is_enabled) 1082 return -EPERM; 1083 1084 spin_lock_irqsave(&vop->irq_lock, flags); 1085 1086 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); 1087 1088 spin_unlock_irqrestore(&vop->irq_lock, flags); 1089 1090 return 0; 1091 } 1092 1093 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1094 { 1095 struct vop *vop = to_vop(crtc); 1096 unsigned long flags; 1097 1098 if (!vop->is_enabled) 1099 return; 1100 1101 spin_lock_irqsave(&vop->irq_lock, flags); 1102 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); 1103 spin_unlock_irqrestore(&vop->irq_lock, flags); 1104 } 1105 1106 static const struct rockchip_crtc_funcs private_crtc_funcs = { 1107 .enable_vblank = vop_crtc_enable_vblank, 1108 .disable_vblank = vop_crtc_disable_vblank, 1109 }; 1110 1111 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode) 1112 { 1113 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode); 1114 1115 switch (mode) { 1116 case DRM_MODE_DPMS_ON: 1117 vop_enable(crtc); 1118 break; 1119 case DRM_MODE_DPMS_STANDBY: 1120 case DRM_MODE_DPMS_SUSPEND: 1121 case DRM_MODE_DPMS_OFF: 1122 vop_disable(crtc); 1123 break; 1124 default: 1125 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 1126 break; 1127 } 1128 } 1129 1130 static void vop_crtc_prepare(struct drm_crtc *crtc) 1131 { 1132 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1133 } 1134 1135 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1136 const struct drm_display_mode *mode, 1137 struct drm_display_mode *adjusted_mode) 1138 { 1139 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 1140 return false; 1141 1142 return true; 1143 } 1144 1145 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 1146 struct drm_framebuffer *old_fb) 1147 { 1148 int ret; 1149 1150 crtc->x = x; 1151 crtc->y = y; 1152 1153 ret = vop_update_primary_plane(crtc, NULL); 1154 if (ret < 0) { 1155 DRM_ERROR("fail to update plane\n"); 1156 return ret; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int vop_crtc_mode_set(struct drm_crtc *crtc, 1163 struct drm_display_mode *mode, 1164 struct drm_display_mode *adjusted_mode, 1165 int x, int y, struct drm_framebuffer *fb) 1166 { 1167 struct vop *vop = to_vop(crtc); 1168 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1169 u16 hdisplay = adjusted_mode->hdisplay; 1170 u16 htotal = adjusted_mode->htotal; 1171 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1172 u16 hact_end = hact_st + hdisplay; 1173 u16 vdisplay = adjusted_mode->vdisplay; 1174 u16 vtotal = adjusted_mode->vtotal; 1175 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1176 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1177 u16 vact_end = vact_st + vdisplay; 1178 int ret, ret_clk; 1179 uint32_t val; 1180 1181 /* 1182 * disable dclk to stop frame scan, so that we can safe config mode and 1183 * enable iommu. 1184 */ 1185 clk_disable(vop->dclk); 1186 1187 switch (vop->connector_type) { 1188 case DRM_MODE_CONNECTOR_LVDS: 1189 VOP_CTRL_SET(vop, rgb_en, 1); 1190 break; 1191 case DRM_MODE_CONNECTOR_eDP: 1192 VOP_CTRL_SET(vop, edp_en, 1); 1193 break; 1194 case DRM_MODE_CONNECTOR_HDMIA: 1195 VOP_CTRL_SET(vop, hdmi_en, 1); 1196 break; 1197 default: 1198 DRM_ERROR("unsupport connector_type[%d]\n", 1199 vop->connector_type); 1200 ret = -EINVAL; 1201 goto out; 1202 }; 1203 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode); 1204 1205 val = 0x8; 1206 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 1207 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 1208 VOP_CTRL_SET(vop, pin_pol, val); 1209 1210 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 1211 val = hact_st << 16; 1212 val |= hact_end; 1213 VOP_CTRL_SET(vop, hact_st_end, val); 1214 VOP_CTRL_SET(vop, hpost_st_end, val); 1215 1216 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 1217 val = vact_st << 16; 1218 val |= vact_end; 1219 VOP_CTRL_SET(vop, vact_st_end, val); 1220 VOP_CTRL_SET(vop, vpost_st_end, val); 1221 1222 ret = vop_crtc_mode_set_base(crtc, x, y, fb); 1223 if (ret) 1224 goto out; 1225 1226 /* 1227 * reset dclk, take all mode config affect, so the clk would run in 1228 * correct frame. 1229 */ 1230 reset_control_assert(vop->dclk_rst); 1231 usleep_range(10, 20); 1232 reset_control_deassert(vop->dclk_rst); 1233 1234 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1235 out: 1236 ret_clk = clk_enable(vop->dclk); 1237 if (ret_clk < 0) { 1238 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk); 1239 return ret_clk; 1240 } 1241 1242 return ret; 1243 } 1244 1245 static void vop_crtc_commit(struct drm_crtc *crtc) 1246 { 1247 } 1248 1249 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1250 .dpms = vop_crtc_dpms, 1251 .prepare = vop_crtc_prepare, 1252 .mode_fixup = vop_crtc_mode_fixup, 1253 .mode_set = vop_crtc_mode_set, 1254 .mode_set_base = vop_crtc_mode_set_base, 1255 .commit = vop_crtc_commit, 1256 }; 1257 1258 static int vop_crtc_page_flip(struct drm_crtc *crtc, 1259 struct drm_framebuffer *fb, 1260 struct drm_pending_vblank_event *event, 1261 uint32_t page_flip_flags) 1262 { 1263 struct vop *vop = to_vop(crtc); 1264 struct drm_framebuffer *old_fb = crtc->primary->fb; 1265 int ret; 1266 1267 /* when the page flip is requested, crtc should be on */ 1268 if (!vop->is_enabled) { 1269 DRM_DEBUG("page flip request rejected because crtc is off.\n"); 1270 return 0; 1271 } 1272 1273 crtc->primary->fb = fb; 1274 1275 ret = vop_update_primary_plane(crtc, event); 1276 if (ret) 1277 crtc->primary->fb = old_fb; 1278 1279 return ret; 1280 } 1281 1282 static void vop_win_state_complete(struct vop_win *vop_win, 1283 struct vop_win_state *state) 1284 { 1285 struct vop *vop = vop_win->vop; 1286 struct drm_crtc *crtc = &vop->crtc; 1287 struct drm_device *drm = crtc->dev; 1288 unsigned long flags; 1289 1290 if (state->event) { 1291 spin_lock_irqsave(&drm->event_lock, flags); 1292 drm_send_vblank_event(drm, -1, state->event); 1293 spin_unlock_irqrestore(&drm->event_lock, flags); 1294 } 1295 1296 list_del(&state->head); 1297 drm_vblank_put(crtc->dev, vop->pipe); 1298 } 1299 1300 static void vop_crtc_destroy(struct drm_crtc *crtc) 1301 { 1302 drm_crtc_cleanup(crtc); 1303 } 1304 1305 static const struct drm_crtc_funcs vop_crtc_funcs = { 1306 .set_config = drm_crtc_helper_set_config, 1307 .page_flip = vop_crtc_page_flip, 1308 .destroy = vop_crtc_destroy, 1309 }; 1310 1311 static bool vop_win_state_is_active(struct vop_win *vop_win, 1312 struct vop_win_state *state) 1313 { 1314 bool active = false; 1315 1316 if (state->fb) { 1317 dma_addr_t yrgb_mst; 1318 1319 /* check yrgb_mst to tell if pending_fb is now front */ 1320 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 1321 1322 active = (yrgb_mst == state->yrgb_mst); 1323 } else { 1324 bool enabled; 1325 1326 /* if enable bit is clear, plane is now disabled */ 1327 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable); 1328 1329 active = (enabled == 0); 1330 } 1331 1332 return active; 1333 } 1334 1335 static void vop_win_state_destroy(struct vop_win_state *state) 1336 { 1337 struct drm_framebuffer *fb = state->fb; 1338 1339 if (fb) 1340 drm_framebuffer_unreference(fb); 1341 1342 kfree(state); 1343 } 1344 1345 static void vop_win_update_state(struct vop_win *vop_win) 1346 { 1347 struct vop_win_state *state, *n, *new_active = NULL; 1348 1349 /* Check if any pending states are now active */ 1350 list_for_each_entry(state, &vop_win->pending, head) 1351 if (vop_win_state_is_active(vop_win, state)) { 1352 new_active = state; 1353 break; 1354 } 1355 1356 if (!new_active) 1357 return; 1358 1359 /* 1360 * Destroy any 'skipped' pending states - states that were queued 1361 * before the newly active state. 1362 */ 1363 list_for_each_entry_safe(state, n, &vop_win->pending, head) { 1364 if (state == new_active) 1365 break; 1366 vop_win_state_complete(vop_win, state); 1367 vop_win_state_destroy(state); 1368 } 1369 1370 vop_win_state_complete(vop_win, new_active); 1371 1372 if (vop_win->active) 1373 vop_win_state_destroy(vop_win->active); 1374 vop_win->active = new_active; 1375 } 1376 1377 static bool vop_win_has_pending_state(struct vop_win *vop_win) 1378 { 1379 return !list_empty(&vop_win->pending); 1380 } 1381 1382 static irqreturn_t vop_isr_thread(int irq, void *data) 1383 { 1384 struct vop *vop = data; 1385 const struct vop_data *vop_data = vop->data; 1386 unsigned int i; 1387 1388 mutex_lock(&vop->vsync_mutex); 1389 1390 if (!vop->vsync_work_pending) 1391 goto done; 1392 1393 vop->vsync_work_pending = false; 1394 1395 for (i = 0; i < vop_data->win_size; i++) { 1396 struct vop_win *vop_win = &vop->win[i]; 1397 1398 vop_win_update_state(vop_win); 1399 if (vop_win_has_pending_state(vop_win)) 1400 vop->vsync_work_pending = true; 1401 } 1402 1403 done: 1404 mutex_unlock(&vop->vsync_mutex); 1405 1406 return IRQ_HANDLED; 1407 } 1408 1409 static irqreturn_t vop_isr(int irq, void *data) 1410 { 1411 struct vop *vop = data; 1412 uint32_t intr0_reg, active_irqs; 1413 unsigned long flags; 1414 int ret = IRQ_NONE; 1415 1416 /* 1417 * INTR_CTRL0 register has interrupt status, enable and clear bits, we 1418 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1419 */ 1420 spin_lock_irqsave(&vop->irq_lock, flags); 1421 intr0_reg = vop_readl(vop, INTR_CTRL0); 1422 active_irqs = intr0_reg & INTR_MASK; 1423 /* Clear all active interrupt sources */ 1424 if (active_irqs) 1425 vop_writel(vop, INTR_CTRL0, 1426 intr0_reg | (active_irqs << INTR_CLR_SHIFT)); 1427 spin_unlock_irqrestore(&vop->irq_lock, flags); 1428 1429 /* This is expected for vop iommu irqs, since the irq is shared */ 1430 if (!active_irqs) 1431 return IRQ_NONE; 1432 1433 if (active_irqs & DSP_HOLD_VALID_INTR) { 1434 complete(&vop->dsp_hold_completion); 1435 active_irqs &= ~DSP_HOLD_VALID_INTR; 1436 ret = IRQ_HANDLED; 1437 } 1438 1439 if (active_irqs & FS_INTR) { 1440 drm_handle_vblank(vop->drm_dev, vop->pipe); 1441 active_irqs &= ~FS_INTR; 1442 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 1443 } 1444 1445 /* Unhandled irqs are spurious. */ 1446 if (active_irqs) 1447 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 1448 1449 return ret; 1450 } 1451 1452 static int vop_create_crtc(struct vop *vop) 1453 { 1454 const struct vop_data *vop_data = vop->data; 1455 struct device *dev = vop->dev; 1456 struct drm_device *drm_dev = vop->drm_dev; 1457 struct drm_plane *primary = NULL, *cursor = NULL, *plane; 1458 struct drm_crtc *crtc = &vop->crtc; 1459 struct device_node *port; 1460 int ret; 1461 int i; 1462 1463 /* 1464 * Create drm_plane for primary and cursor planes first, since we need 1465 * to pass them to drm_crtc_init_with_planes, which sets the 1466 * "possible_crtcs" to the newly initialized crtc. 1467 */ 1468 for (i = 0; i < vop_data->win_size; i++) { 1469 struct vop_win *vop_win = &vop->win[i]; 1470 const struct vop_win_data *win_data = vop_win->data; 1471 1472 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1473 win_data->type != DRM_PLANE_TYPE_CURSOR) 1474 continue; 1475 1476 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1477 0, &vop_plane_funcs, 1478 win_data->phy->data_formats, 1479 win_data->phy->nformats, 1480 win_data->type); 1481 if (ret) { 1482 DRM_ERROR("failed to initialize plane\n"); 1483 goto err_cleanup_planes; 1484 } 1485 1486 plane = &vop_win->base; 1487 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1488 primary = plane; 1489 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1490 cursor = plane; 1491 } 1492 1493 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1494 &vop_crtc_funcs); 1495 if (ret) 1496 return ret; 1497 1498 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1499 1500 /* 1501 * Create drm_planes for overlay windows with possible_crtcs restricted 1502 * to the newly created crtc. 1503 */ 1504 for (i = 0; i < vop_data->win_size; i++) { 1505 struct vop_win *vop_win = &vop->win[i]; 1506 const struct vop_win_data *win_data = vop_win->data; 1507 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1508 1509 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1510 continue; 1511 1512 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1513 possible_crtcs, 1514 &vop_plane_funcs, 1515 win_data->phy->data_formats, 1516 win_data->phy->nformats, 1517 win_data->type); 1518 if (ret) { 1519 DRM_ERROR("failed to initialize overlay plane\n"); 1520 goto err_cleanup_crtc; 1521 } 1522 } 1523 1524 port = of_get_child_by_name(dev->of_node, "port"); 1525 if (!port) { 1526 DRM_ERROR("no port node found in %s\n", 1527 dev->of_node->full_name); 1528 goto err_cleanup_crtc; 1529 } 1530 1531 init_completion(&vop->dsp_hold_completion); 1532 crtc->port = port; 1533 vop->pipe = drm_crtc_index(crtc); 1534 rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe); 1535 1536 return 0; 1537 1538 err_cleanup_crtc: 1539 drm_crtc_cleanup(crtc); 1540 err_cleanup_planes: 1541 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 1542 drm_plane_cleanup(plane); 1543 return ret; 1544 } 1545 1546 static void vop_destroy_crtc(struct vop *vop) 1547 { 1548 struct drm_crtc *crtc = &vop->crtc; 1549 1550 rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe); 1551 of_node_put(crtc->port); 1552 drm_crtc_cleanup(crtc); 1553 } 1554 1555 static int vop_initial(struct vop *vop) 1556 { 1557 const struct vop_data *vop_data = vop->data; 1558 const struct vop_reg_data *init_table = vop_data->init_table; 1559 struct reset_control *ahb_rst; 1560 int i, ret; 1561 1562 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1563 if (IS_ERR(vop->hclk)) { 1564 dev_err(vop->dev, "failed to get hclk source\n"); 1565 return PTR_ERR(vop->hclk); 1566 } 1567 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1568 if (IS_ERR(vop->aclk)) { 1569 dev_err(vop->dev, "failed to get aclk source\n"); 1570 return PTR_ERR(vop->aclk); 1571 } 1572 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1573 if (IS_ERR(vop->dclk)) { 1574 dev_err(vop->dev, "failed to get dclk source\n"); 1575 return PTR_ERR(vop->dclk); 1576 } 1577 1578 ret = clk_prepare(vop->hclk); 1579 if (ret < 0) { 1580 dev_err(vop->dev, "failed to prepare hclk\n"); 1581 return ret; 1582 } 1583 1584 ret = clk_prepare(vop->dclk); 1585 if (ret < 0) { 1586 dev_err(vop->dev, "failed to prepare dclk\n"); 1587 goto err_unprepare_hclk; 1588 } 1589 1590 ret = clk_prepare(vop->aclk); 1591 if (ret < 0) { 1592 dev_err(vop->dev, "failed to prepare aclk\n"); 1593 goto err_unprepare_dclk; 1594 } 1595 1596 /* 1597 * enable hclk, so that we can config vop register. 1598 */ 1599 ret = clk_enable(vop->hclk); 1600 if (ret < 0) { 1601 dev_err(vop->dev, "failed to prepare aclk\n"); 1602 goto err_unprepare_aclk; 1603 } 1604 /* 1605 * do hclk_reset, reset all vop registers. 1606 */ 1607 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1608 if (IS_ERR(ahb_rst)) { 1609 dev_err(vop->dev, "failed to get ahb reset\n"); 1610 ret = PTR_ERR(ahb_rst); 1611 goto err_disable_hclk; 1612 } 1613 reset_control_assert(ahb_rst); 1614 usleep_range(10, 20); 1615 reset_control_deassert(ahb_rst); 1616 1617 memcpy(vop->regsbak, vop->regs, vop->len); 1618 1619 for (i = 0; i < vop_data->table_size; i++) 1620 vop_writel(vop, init_table[i].offset, init_table[i].value); 1621 1622 for (i = 0; i < vop_data->win_size; i++) { 1623 const struct vop_win_data *win = &vop_data->win[i]; 1624 1625 VOP_WIN_SET(vop, win, enable, 0); 1626 } 1627 1628 vop_cfg_done(vop); 1629 1630 /* 1631 * do dclk_reset, let all config take affect. 1632 */ 1633 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1634 if (IS_ERR(vop->dclk_rst)) { 1635 dev_err(vop->dev, "failed to get dclk reset\n"); 1636 ret = PTR_ERR(vop->dclk_rst); 1637 goto err_unprepare_aclk; 1638 } 1639 reset_control_assert(vop->dclk_rst); 1640 usleep_range(10, 20); 1641 reset_control_deassert(vop->dclk_rst); 1642 1643 clk_disable(vop->hclk); 1644 1645 vop->is_enabled = false; 1646 1647 return 0; 1648 1649 err_disable_hclk: 1650 clk_disable(vop->hclk); 1651 err_unprepare_aclk: 1652 clk_unprepare(vop->aclk); 1653 err_unprepare_dclk: 1654 clk_unprepare(vop->dclk); 1655 err_unprepare_hclk: 1656 clk_unprepare(vop->hclk); 1657 return ret; 1658 } 1659 1660 /* 1661 * Initialize the vop->win array elements. 1662 */ 1663 static void vop_win_init(struct vop *vop) 1664 { 1665 const struct vop_data *vop_data = vop->data; 1666 unsigned int i; 1667 1668 for (i = 0; i < vop_data->win_size; i++) { 1669 struct vop_win *vop_win = &vop->win[i]; 1670 const struct vop_win_data *win_data = &vop_data->win[i]; 1671 1672 vop_win->data = win_data; 1673 vop_win->vop = vop; 1674 INIT_LIST_HEAD(&vop_win->pending); 1675 } 1676 } 1677 1678 static int vop_bind(struct device *dev, struct device *master, void *data) 1679 { 1680 struct platform_device *pdev = to_platform_device(dev); 1681 const struct of_device_id *of_id; 1682 const struct vop_data *vop_data; 1683 struct drm_device *drm_dev = data; 1684 struct vop *vop; 1685 struct resource *res; 1686 size_t alloc_size; 1687 int ret, irq; 1688 1689 of_id = of_match_device(vop_driver_dt_match, dev); 1690 vop_data = of_id->data; 1691 if (!vop_data) 1692 return -ENODEV; 1693 1694 /* Allocate vop struct and its vop_win array */ 1695 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1696 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1697 if (!vop) 1698 return -ENOMEM; 1699 1700 vop->dev = dev; 1701 vop->data = vop_data; 1702 vop->drm_dev = drm_dev; 1703 dev_set_drvdata(dev, vop); 1704 1705 vop_win_init(vop); 1706 1707 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1708 vop->len = resource_size(res); 1709 vop->regs = devm_ioremap_resource(dev, res); 1710 if (IS_ERR(vop->regs)) 1711 return PTR_ERR(vop->regs); 1712 1713 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1714 if (!vop->regsbak) 1715 return -ENOMEM; 1716 1717 ret = vop_initial(vop); 1718 if (ret < 0) { 1719 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 1720 return ret; 1721 } 1722 1723 irq = platform_get_irq(pdev, 0); 1724 if (irq < 0) { 1725 dev_err(dev, "cannot find irq for vop\n"); 1726 return irq; 1727 } 1728 vop->irq = (unsigned int)irq; 1729 1730 spin_lock_init(&vop->reg_lock); 1731 spin_lock_init(&vop->irq_lock); 1732 1733 mutex_init(&vop->vsync_mutex); 1734 1735 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread, 1736 IRQF_SHARED, dev_name(dev), vop); 1737 if (ret) 1738 return ret; 1739 1740 /* IRQ is initially disabled; it gets enabled in power_on */ 1741 disable_irq(vop->irq); 1742 1743 ret = vop_create_crtc(vop); 1744 if (ret) 1745 return ret; 1746 1747 pm_runtime_enable(&pdev->dev); 1748 return 0; 1749 } 1750 1751 static void vop_unbind(struct device *dev, struct device *master, void *data) 1752 { 1753 struct vop *vop = dev_get_drvdata(dev); 1754 1755 pm_runtime_disable(dev); 1756 vop_destroy_crtc(vop); 1757 } 1758 1759 static const struct component_ops vop_component_ops = { 1760 .bind = vop_bind, 1761 .unbind = vop_unbind, 1762 }; 1763 1764 static int vop_probe(struct platform_device *pdev) 1765 { 1766 struct device *dev = &pdev->dev; 1767 1768 if (!dev->of_node) { 1769 dev_err(dev, "can't find vop devices\n"); 1770 return -ENODEV; 1771 } 1772 1773 return component_add(dev, &vop_component_ops); 1774 } 1775 1776 static int vop_remove(struct platform_device *pdev) 1777 { 1778 component_del(&pdev->dev, &vop_component_ops); 1779 1780 return 0; 1781 } 1782 1783 struct platform_driver vop_platform_driver = { 1784 .probe = vop_probe, 1785 .remove = vop_remove, 1786 .driver = { 1787 .name = "rockchip-vop", 1788 .owner = THIS_MODULE, 1789 .of_match_table = of_match_ptr(vop_driver_dt_match), 1790 }, 1791 }; 1792 1793 module_platform_driver(vop_platform_driver); 1794 1795 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>"); 1796 MODULE_DESCRIPTION("ROCKCHIP VOP Driver"); 1797 MODULE_LICENSE("GPL v2"); 1798