1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_blend.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_flip_work.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_framebuffer.h> 28 #include <drm/drm_gem_atomic_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_self_refresh_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #ifdef CONFIG_DRM_ANALOGIX_DP 35 #include <drm/bridge/analogix_dp.h> 36 #endif 37 38 #include "rockchip_drm_drv.h" 39 #include "rockchip_drm_gem.h" 40 #include "rockchip_drm_fb.h" 41 #include "rockchip_drm_vop.h" 42 #include "rockchip_rgb.h" 43 44 #define VOP_WIN_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 46 #define VOP_SCL_SET(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 48 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 49 vop_reg_set(vop, &win->phy->scl->ext->name, \ 50 win->base, ~0, v, #name) 51 52 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 53 do { \ 54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 56 } while (0) 57 58 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 59 do { \ 60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 62 } while (0) 63 64 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 66 67 #define VOP_REG_SET(vop, group, name, v) \ 68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 69 70 #define VOP_HAS_REG(vop, group, name) \ 71 (!!(vop->data->group->name.mask)) 72 73 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 74 do { \ 75 int i, reg = 0, mask = 0; \ 76 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 77 if (vop->data->intr->intrs[i] & type) { \ 78 reg |= (v) << i; \ 79 mask |= 1 << i; \ 80 } \ 81 } \ 82 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 83 } while (0) 84 #define VOP_INTR_GET_TYPE(vop, name, type) \ 85 vop_get_intr_type(vop, &vop->data->intr->name, type) 86 87 #define VOP_WIN_GET(vop, win, name) \ 88 vop_read_reg(vop, win->base, &win->phy->name) 89 90 #define VOP_WIN_HAS_REG(win, name) \ 91 (!!(win->phy->name.mask)) 92 93 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 95 96 #define VOP_WIN_TO_INDEX(vop_win) \ 97 ((vop_win) - (vop_win)->vop->win) 98 99 #define VOP_AFBC_SET(vop, name, v) \ 100 do { \ 101 if ((vop)->data->afbc) \ 102 vop_reg_set((vop), &(vop)->data->afbc->name, \ 103 0, ~0, v, #name); \ 104 } while (0) 105 106 #define to_vop(x) container_of(x, struct vop, crtc) 107 #define to_vop_win(x) container_of(x, struct vop_win, base) 108 109 #define AFBC_FMT_RGB565 0x0 110 #define AFBC_FMT_U8U8U8U8 0x5 111 #define AFBC_FMT_U8U8U8 0x4 112 113 #define AFBC_TILE_16x16 BIT(4) 114 115 /* 116 * The coefficients of the following matrix are all fixed points. 117 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 118 * They are all represented in two's complement. 119 */ 120 static const uint32_t bt601_yuv2rgb[] = { 121 0x4A8, 0x0, 0x662, 122 0x4A8, 0x1E6F, 0x1CBF, 123 0x4A8, 0x812, 0x0, 124 0x321168, 0x0877CF, 0x2EB127 125 }; 126 127 enum vop_pending { 128 VOP_PENDING_FB_UNREF, 129 }; 130 131 struct vop_win { 132 struct drm_plane base; 133 const struct vop_win_data *data; 134 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 135 struct vop *vop; 136 }; 137 138 struct rockchip_rgb; 139 struct vop { 140 struct drm_crtc crtc; 141 struct device *dev; 142 struct drm_device *drm_dev; 143 bool is_enabled; 144 145 struct completion dsp_hold_completion; 146 unsigned int win_enabled; 147 148 /* protected by dev->event_lock */ 149 struct drm_pending_vblank_event *event; 150 151 struct drm_flip_work fb_unref_work; 152 unsigned long pending; 153 154 struct completion line_flag_completion; 155 156 const struct vop_data *data; 157 158 uint32_t *regsbak; 159 void __iomem *regs; 160 void __iomem *lut_regs; 161 162 /* physical map length of vop register */ 163 uint32_t len; 164 165 /* one time only one process allowed to config the register */ 166 spinlock_t reg_lock; 167 /* lock vop irq reg */ 168 spinlock_t irq_lock; 169 /* protects crtc enable/disable */ 170 struct mutex vop_lock; 171 172 unsigned int irq; 173 174 /* vop AHP clk */ 175 struct clk *hclk; 176 /* vop dclk */ 177 struct clk *dclk; 178 /* vop share memory frequency */ 179 struct clk *aclk; 180 181 /* vop dclk reset */ 182 struct reset_control *dclk_rst; 183 184 /* optional internal rgb encoder */ 185 struct rockchip_rgb *rgb; 186 187 struct vop_win win[]; 188 }; 189 190 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 191 { 192 return readl(vop->regs + offset); 193 } 194 195 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 196 const struct vop_reg *reg) 197 { 198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 199 } 200 201 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 202 uint32_t _offset, uint32_t _mask, uint32_t v, 203 const char *reg_name) 204 { 205 int offset, mask, shift; 206 207 if (!reg || !reg->mask) { 208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 209 return; 210 } 211 212 offset = reg->offset + _offset; 213 mask = reg->mask & _mask; 214 shift = reg->shift; 215 216 if (reg->write_mask) { 217 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 218 } else { 219 uint32_t cached_val = vop->regsbak[offset >> 2]; 220 221 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 222 vop->regsbak[offset >> 2] = v; 223 } 224 225 if (reg->relaxed) 226 writel_relaxed(v, vop->regs + offset); 227 else 228 writel(v, vop->regs + offset); 229 } 230 231 static inline uint32_t vop_get_intr_type(struct vop *vop, 232 const struct vop_reg *reg, int type) 233 { 234 uint32_t i, ret = 0; 235 uint32_t regs = vop_read_reg(vop, 0, reg); 236 237 for (i = 0; i < vop->data->intr->nintrs; i++) { 238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 239 ret |= vop->data->intr->intrs[i]; 240 } 241 242 return ret; 243 } 244 245 static inline void vop_cfg_done(struct vop *vop) 246 { 247 VOP_REG_SET(vop, common, cfg_done, 1); 248 } 249 250 static bool has_rb_swapped(uint32_t format) 251 { 252 switch (format) { 253 case DRM_FORMAT_XBGR8888: 254 case DRM_FORMAT_ABGR8888: 255 case DRM_FORMAT_BGR888: 256 case DRM_FORMAT_BGR565: 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 static bool has_uv_swapped(uint32_t format) 264 { 265 switch (format) { 266 case DRM_FORMAT_NV21: 267 case DRM_FORMAT_NV61: 268 case DRM_FORMAT_NV42: 269 return true; 270 default: 271 return false; 272 } 273 } 274 275 static bool is_fmt_10(uint32_t format) 276 { 277 switch (format) { 278 case DRM_FORMAT_NV15: 279 case DRM_FORMAT_NV20: 280 case DRM_FORMAT_NV30: 281 return true; 282 default: 283 return false; 284 } 285 } 286 287 static enum vop_data_format vop_convert_format(uint32_t format) 288 { 289 switch (format) { 290 case DRM_FORMAT_XRGB8888: 291 case DRM_FORMAT_ARGB8888: 292 case DRM_FORMAT_XBGR8888: 293 case DRM_FORMAT_ABGR8888: 294 return VOP_FMT_ARGB8888; 295 case DRM_FORMAT_RGB888: 296 case DRM_FORMAT_BGR888: 297 return VOP_FMT_RGB888; 298 case DRM_FORMAT_RGB565: 299 case DRM_FORMAT_BGR565: 300 return VOP_FMT_RGB565; 301 case DRM_FORMAT_NV12: 302 case DRM_FORMAT_NV15: 303 case DRM_FORMAT_NV21: 304 return VOP_FMT_YUV420SP; 305 case DRM_FORMAT_NV16: 306 case DRM_FORMAT_NV20: 307 case DRM_FORMAT_NV61: 308 return VOP_FMT_YUV422SP; 309 case DRM_FORMAT_NV24: 310 case DRM_FORMAT_NV30: 311 case DRM_FORMAT_NV42: 312 return VOP_FMT_YUV444SP; 313 default: 314 DRM_ERROR("unsupported format[%08x]\n", format); 315 return -EINVAL; 316 } 317 } 318 319 static int vop_convert_afbc_format(uint32_t format) 320 { 321 switch (format) { 322 case DRM_FORMAT_XRGB8888: 323 case DRM_FORMAT_ARGB8888: 324 case DRM_FORMAT_XBGR8888: 325 case DRM_FORMAT_ABGR8888: 326 return AFBC_FMT_U8U8U8U8; 327 case DRM_FORMAT_RGB888: 328 case DRM_FORMAT_BGR888: 329 return AFBC_FMT_U8U8U8; 330 case DRM_FORMAT_RGB565: 331 case DRM_FORMAT_BGR565: 332 return AFBC_FMT_RGB565; 333 default: 334 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format); 335 return -EINVAL; 336 } 337 } 338 339 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 340 uint32_t dst, bool is_horizontal, 341 int vsu_mode, int *vskiplines) 342 { 343 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 344 345 if (vskiplines) 346 *vskiplines = 0; 347 348 if (is_horizontal) { 349 if (mode == SCALE_UP) 350 val = GET_SCL_FT_BIC(src, dst); 351 else if (mode == SCALE_DOWN) 352 val = GET_SCL_FT_BILI_DN(src, dst); 353 } else { 354 if (mode == SCALE_UP) { 355 if (vsu_mode == SCALE_UP_BIL) 356 val = GET_SCL_FT_BILI_UP(src, dst); 357 else 358 val = GET_SCL_FT_BIC(src, dst); 359 } else if (mode == SCALE_DOWN) { 360 if (vskiplines) { 361 *vskiplines = scl_get_vskiplines(src, dst); 362 val = scl_get_bili_dn_vskip(src, dst, 363 *vskiplines); 364 } else { 365 val = GET_SCL_FT_BILI_DN(src, dst); 366 } 367 } 368 } 369 370 return val; 371 } 372 373 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 374 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 375 uint32_t dst_h, const struct drm_format_info *info) 376 { 377 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 378 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 379 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 380 bool is_yuv = false; 381 uint16_t cbcr_src_w = src_w / info->hsub; 382 uint16_t cbcr_src_h = src_h / info->vsub; 383 uint16_t vsu_mode; 384 uint16_t lb_mode; 385 uint32_t val; 386 int vskiplines; 387 388 if (info->is_yuv) 389 is_yuv = true; 390 391 if (dst_w > 3840) { 392 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 393 return; 394 } 395 396 if (!win->phy->scl->ext) { 397 VOP_SCL_SET(vop, win, scale_yrgb_x, 398 scl_cal_scale2(src_w, dst_w)); 399 VOP_SCL_SET(vop, win, scale_yrgb_y, 400 scl_cal_scale2(src_h, dst_h)); 401 if (is_yuv) { 402 VOP_SCL_SET(vop, win, scale_cbcr_x, 403 scl_cal_scale2(cbcr_src_w, dst_w)); 404 VOP_SCL_SET(vop, win, scale_cbcr_y, 405 scl_cal_scale2(cbcr_src_h, dst_h)); 406 } 407 return; 408 } 409 410 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 411 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 412 413 if (is_yuv) { 414 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 415 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 416 if (cbcr_hor_scl_mode == SCALE_DOWN) 417 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 418 else 419 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 420 } else { 421 if (yrgb_hor_scl_mode == SCALE_DOWN) 422 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 423 else 424 lb_mode = scl_vop_cal_lb_mode(src_w, false); 425 } 426 427 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 428 if (lb_mode == LB_RGB_3840X2) { 429 if (yrgb_ver_scl_mode != SCALE_NONE) { 430 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 431 return; 432 } 433 if (cbcr_ver_scl_mode != SCALE_NONE) { 434 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 435 return; 436 } 437 vsu_mode = SCALE_UP_BIL; 438 } else if (lb_mode == LB_RGB_2560X4) { 439 vsu_mode = SCALE_UP_BIL; 440 } else { 441 vsu_mode = SCALE_UP_BIC; 442 } 443 444 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 445 true, 0, NULL); 446 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 447 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 448 false, vsu_mode, &vskiplines); 449 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 450 451 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 452 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 453 454 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 455 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 456 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 457 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 458 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 459 if (is_yuv) { 460 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 461 dst_w, true, 0, NULL); 462 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 463 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 464 dst_h, false, vsu_mode, &vskiplines); 465 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 466 467 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 468 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 469 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 470 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 471 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 472 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 473 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 474 } 475 } 476 477 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 478 { 479 unsigned long flags; 480 481 if (WARN_ON(!vop->is_enabled)) 482 return; 483 484 spin_lock_irqsave(&vop->irq_lock, flags); 485 486 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 487 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 488 489 spin_unlock_irqrestore(&vop->irq_lock, flags); 490 } 491 492 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 493 { 494 unsigned long flags; 495 496 if (WARN_ON(!vop->is_enabled)) 497 return; 498 499 spin_lock_irqsave(&vop->irq_lock, flags); 500 501 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 502 503 spin_unlock_irqrestore(&vop->irq_lock, flags); 504 } 505 506 /* 507 * (1) each frame starts at the start of the Vsync pulse which is signaled by 508 * the "FRAME_SYNC" interrupt. 509 * (2) the active data region of each frame ends at dsp_vact_end 510 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 511 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 512 * 513 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 514 * Interrupts 515 * LINE_FLAG -------------------------------+ 516 * FRAME_SYNC ----+ | 517 * | | 518 * v v 519 * | Vsync | Vbp | Vactive | Vfp | 520 * ^ ^ ^ ^ 521 * | | | | 522 * | | | | 523 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 524 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 525 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 526 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 527 */ 528 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 529 { 530 uint32_t line_flag_irq; 531 unsigned long flags; 532 533 spin_lock_irqsave(&vop->irq_lock, flags); 534 535 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 536 537 spin_unlock_irqrestore(&vop->irq_lock, flags); 538 539 return !!line_flag_irq; 540 } 541 542 static void vop_line_flag_irq_enable(struct vop *vop) 543 { 544 unsigned long flags; 545 546 if (WARN_ON(!vop->is_enabled)) 547 return; 548 549 spin_lock_irqsave(&vop->irq_lock, flags); 550 551 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 552 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 553 554 spin_unlock_irqrestore(&vop->irq_lock, flags); 555 } 556 557 static void vop_line_flag_irq_disable(struct vop *vop) 558 { 559 unsigned long flags; 560 561 if (WARN_ON(!vop->is_enabled)) 562 return; 563 564 spin_lock_irqsave(&vop->irq_lock, flags); 565 566 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 567 568 spin_unlock_irqrestore(&vop->irq_lock, flags); 569 } 570 571 static int vop_core_clks_enable(struct vop *vop) 572 { 573 int ret; 574 575 ret = clk_enable(vop->hclk); 576 if (ret < 0) 577 return ret; 578 579 ret = clk_enable(vop->aclk); 580 if (ret < 0) 581 goto err_disable_hclk; 582 583 return 0; 584 585 err_disable_hclk: 586 clk_disable(vop->hclk); 587 return ret; 588 } 589 590 static void vop_core_clks_disable(struct vop *vop) 591 { 592 clk_disable(vop->aclk); 593 clk_disable(vop->hclk); 594 } 595 596 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 597 { 598 const struct vop_win_data *win = vop_win->data; 599 600 if (win->phy->scl && win->phy->scl->ext) { 601 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 602 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 603 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 604 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 605 } 606 607 VOP_WIN_SET(vop, win, enable, 0); 608 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 609 } 610 611 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 612 { 613 struct vop *vop = to_vop(crtc); 614 int ret, i; 615 616 ret = pm_runtime_resume_and_get(vop->dev); 617 if (ret < 0) { 618 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 619 return ret; 620 } 621 622 ret = vop_core_clks_enable(vop); 623 if (WARN_ON(ret < 0)) 624 goto err_put_pm_runtime; 625 626 ret = clk_enable(vop->dclk); 627 if (WARN_ON(ret < 0)) 628 goto err_disable_core; 629 630 /* 631 * Slave iommu shares power, irq and clock with vop. It was associated 632 * automatically with this master device via common driver code. 633 * Now that we have enabled the clock we attach it to the shared drm 634 * mapping. 635 */ 636 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 637 if (ret) { 638 DRM_DEV_ERROR(vop->dev, 639 "failed to attach dma mapping, %d\n", ret); 640 goto err_disable_dclk; 641 } 642 643 spin_lock(&vop->reg_lock); 644 for (i = 0; i < vop->len; i += 4) 645 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 646 647 /* 648 * We need to make sure that all windows are disabled before we 649 * enable the crtc. Otherwise we might try to scan from a destroyed 650 * buffer later. 651 * 652 * In the case of enable-after-PSR, we don't need to worry about this 653 * case since the buffer is guaranteed to be valid and disabling the 654 * window will result in screen glitches on PSR exit. 655 */ 656 if (!old_state || !old_state->self_refresh_active) { 657 for (i = 0; i < vop->data->win_size; i++) { 658 struct vop_win *vop_win = &vop->win[i]; 659 660 vop_win_disable(vop, vop_win); 661 } 662 } 663 664 if (vop->data->afbc) { 665 struct rockchip_crtc_state *s; 666 /* 667 * Disable AFBC and forget there was a vop window with AFBC 668 */ 669 VOP_AFBC_SET(vop, enable, 0); 670 s = to_rockchip_crtc_state(crtc->state); 671 s->enable_afbc = false; 672 } 673 674 vop_cfg_done(vop); 675 676 spin_unlock(&vop->reg_lock); 677 678 /* 679 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 680 */ 681 vop->is_enabled = true; 682 683 spin_lock(&vop->reg_lock); 684 685 VOP_REG_SET(vop, common, standby, 1); 686 687 spin_unlock(&vop->reg_lock); 688 689 drm_crtc_vblank_on(crtc); 690 691 return 0; 692 693 err_disable_dclk: 694 clk_disable(vop->dclk); 695 err_disable_core: 696 vop_core_clks_disable(vop); 697 err_put_pm_runtime: 698 pm_runtime_put_sync(vop->dev); 699 return ret; 700 } 701 702 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 703 { 704 struct vop *vop = to_vop(crtc); 705 int i; 706 707 spin_lock(&vop->reg_lock); 708 709 for (i = 0; i < vop->data->win_size; i++) { 710 struct vop_win *vop_win = &vop->win[i]; 711 const struct vop_win_data *win = vop_win->data; 712 713 VOP_WIN_SET(vop, win, enable, 714 enabled && (vop->win_enabled & BIT(i))); 715 } 716 vop_cfg_done(vop); 717 718 spin_unlock(&vop->reg_lock); 719 } 720 721 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 722 struct drm_atomic_state *state) 723 { 724 struct vop *vop = to_vop(crtc); 725 726 WARN_ON(vop->event); 727 728 if (crtc->state->self_refresh_active) 729 rockchip_drm_set_win_enabled(crtc, false); 730 731 if (crtc->state->self_refresh_active) 732 goto out; 733 734 mutex_lock(&vop->vop_lock); 735 736 drm_crtc_vblank_off(crtc); 737 738 /* 739 * Vop standby will take effect at end of current frame, 740 * if dsp hold valid irq happen, it means standby complete. 741 * 742 * we must wait standby complete when we want to disable aclk, 743 * if not, memory bus maybe dead. 744 */ 745 reinit_completion(&vop->dsp_hold_completion); 746 vop_dsp_hold_valid_irq_enable(vop); 747 748 spin_lock(&vop->reg_lock); 749 750 VOP_REG_SET(vop, common, standby, 1); 751 752 spin_unlock(&vop->reg_lock); 753 754 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 755 msecs_to_jiffies(200))) 756 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 757 758 vop_dsp_hold_valid_irq_disable(vop); 759 760 vop->is_enabled = false; 761 762 /* 763 * vop standby complete, so iommu detach is safe. 764 */ 765 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 766 767 clk_disable(vop->dclk); 768 vop_core_clks_disable(vop); 769 pm_runtime_put(vop->dev); 770 771 mutex_unlock(&vop->vop_lock); 772 773 out: 774 if (crtc->state->event && !crtc->state->active) { 775 spin_lock_irq(&crtc->dev->event_lock); 776 drm_crtc_send_vblank_event(crtc, crtc->state->event); 777 spin_unlock_irq(&crtc->dev->event_lock); 778 779 crtc->state->event = NULL; 780 } 781 } 782 783 static inline bool rockchip_afbc(u64 modifier) 784 { 785 return modifier == ROCKCHIP_AFBC_MOD; 786 } 787 788 static bool rockchip_mod_supported(struct drm_plane *plane, 789 u32 format, u64 modifier) 790 { 791 if (modifier == DRM_FORMAT_MOD_LINEAR) 792 return true; 793 794 if (!rockchip_afbc(modifier)) { 795 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 796 797 return false; 798 } 799 800 return vop_convert_afbc_format(format) >= 0; 801 } 802 803 static int vop_plane_atomic_check(struct drm_plane *plane, 804 struct drm_atomic_state *state) 805 { 806 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 807 plane); 808 struct drm_crtc *crtc = new_plane_state->crtc; 809 struct drm_crtc_state *crtc_state; 810 struct drm_framebuffer *fb = new_plane_state->fb; 811 struct vop_win *vop_win = to_vop_win(plane); 812 const struct vop_win_data *win = vop_win->data; 813 int ret; 814 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 815 DRM_PLANE_NO_SCALING; 816 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 817 DRM_PLANE_NO_SCALING; 818 819 if (!crtc || WARN_ON(!fb)) 820 return 0; 821 822 crtc_state = drm_atomic_get_existing_crtc_state(state, 823 crtc); 824 if (WARN_ON(!crtc_state)) 825 return -EINVAL; 826 827 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 828 min_scale, max_scale, 829 true, true); 830 if (ret) 831 return ret; 832 833 if (!new_plane_state->visible) 834 return 0; 835 836 ret = vop_convert_format(fb->format->format); 837 if (ret < 0) 838 return ret; 839 840 /* 841 * Src.x1 can be odd when do clip, but yuv plane start point 842 * need align with 2 pixel. 843 */ 844 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 845 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n"); 846 return -EINVAL; 847 } 848 849 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 850 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n"); 851 return -EINVAL; 852 } 853 854 if (rockchip_afbc(fb->modifier)) { 855 struct vop *vop = to_vop(crtc); 856 857 if (!vop->data->afbc) { 858 DRM_DEBUG_KMS("vop does not support AFBC\n"); 859 return -EINVAL; 860 } 861 862 ret = vop_convert_afbc_format(fb->format->format); 863 if (ret < 0) 864 return ret; 865 866 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 867 DRM_DEBUG_KMS("AFBC does not support offset display, " \ 868 "xpos=%d, ypos=%d, offset=%d\n", 869 new_plane_state->src.x1, new_plane_state->src.y1, 870 fb->offsets[0]); 871 return -EINVAL; 872 } 873 874 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 875 DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n", 876 new_plane_state->rotation); 877 return -EINVAL; 878 } 879 } 880 881 return 0; 882 } 883 884 static void vop_plane_atomic_disable(struct drm_plane *plane, 885 struct drm_atomic_state *state) 886 { 887 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 888 plane); 889 struct vop_win *vop_win = to_vop_win(plane); 890 struct vop *vop = to_vop(old_state->crtc); 891 892 if (!old_state->crtc) 893 return; 894 895 spin_lock(&vop->reg_lock); 896 897 vop_win_disable(vop, vop_win); 898 899 spin_unlock(&vop->reg_lock); 900 } 901 902 static void vop_plane_atomic_update(struct drm_plane *plane, 903 struct drm_atomic_state *state) 904 { 905 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 906 plane); 907 struct drm_crtc *crtc = new_state->crtc; 908 struct vop_win *vop_win = to_vop_win(plane); 909 const struct vop_win_data *win = vop_win->data; 910 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 911 struct vop *vop = to_vop(new_state->crtc); 912 struct drm_framebuffer *fb = new_state->fb; 913 unsigned int actual_w, actual_h; 914 unsigned int dsp_stx, dsp_sty; 915 uint32_t act_info, dsp_info, dsp_st; 916 struct drm_rect *src = &new_state->src; 917 struct drm_rect *dest = &new_state->dst; 918 struct drm_gem_object *obj, *uv_obj; 919 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 920 unsigned long offset; 921 dma_addr_t dma_addr; 922 uint32_t val; 923 bool rb_swap, uv_swap; 924 int win_index = VOP_WIN_TO_INDEX(vop_win); 925 int format; 926 int is_yuv = fb->format->is_yuv; 927 int i; 928 929 /* 930 * can't update plane when vop is disabled. 931 */ 932 if (WARN_ON(!crtc)) 933 return; 934 935 if (WARN_ON(!vop->is_enabled)) 936 return; 937 938 if (!new_state->visible) { 939 vop_plane_atomic_disable(plane, state); 940 return; 941 } 942 943 obj = fb->obj[0]; 944 rk_obj = to_rockchip_obj(obj); 945 946 actual_w = drm_rect_width(src) >> 16; 947 actual_h = drm_rect_height(src) >> 16; 948 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 949 950 dsp_info = (drm_rect_height(dest) - 1) << 16; 951 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 952 953 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 954 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 955 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 956 957 if (fb->format->char_per_block[0]) 958 offset = drm_format_info_min_pitch(fb->format, 0, 959 src->x1 >> 16); 960 else 961 offset = (src->x1 >> 16) * fb->format->cpp[0]; 962 963 offset += (src->y1 >> 16) * fb->pitches[0]; 964 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 965 966 /* 967 * For y-mirroring we need to move address 968 * to the beginning of the last line. 969 */ 970 if (new_state->rotation & DRM_MODE_REFLECT_Y) 971 dma_addr += (actual_h - 1) * fb->pitches[0]; 972 973 format = vop_convert_format(fb->format->format); 974 975 spin_lock(&vop->reg_lock); 976 977 if (rockchip_afbc(fb->modifier)) { 978 int afbc_format = vop_convert_afbc_format(fb->format->format); 979 980 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 981 VOP_AFBC_SET(vop, hreg_block_split, 0); 982 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 983 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 984 VOP_AFBC_SET(vop, pic_size, act_info); 985 } 986 987 VOP_WIN_SET(vop, win, format, format); 988 VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); 989 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 990 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 991 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 992 VOP_WIN_SET(vop, win, y_mir_en, 993 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 994 VOP_WIN_SET(vop, win, x_mir_en, 995 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 996 997 if (is_yuv) { 998 uv_obj = fb->obj[1]; 999 rk_uv_obj = to_rockchip_obj(uv_obj); 1000 1001 if (fb->format->char_per_block[1]) 1002 offset = drm_format_info_min_pitch(fb->format, 1, 1003 src->x1 >> 16); 1004 else 1005 offset = (src->x1 >> 16) * fb->format->cpp[1]; 1006 offset /= fb->format->hsub; 1007 offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub; 1008 1009 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 1010 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 1011 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 1012 1013 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 1014 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 1015 win_yuv2yuv, 1016 y2r_coefficients[i], 1017 bt601_yuv2rgb[i]); 1018 } 1019 1020 uv_swap = has_uv_swapped(fb->format->format); 1021 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1022 } 1023 1024 if (win->phy->scl) 1025 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1026 drm_rect_width(dest), drm_rect_height(dest), 1027 fb->format); 1028 1029 VOP_WIN_SET(vop, win, act_info, act_info); 1030 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1031 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1032 1033 rb_swap = has_rb_swapped(fb->format->format); 1034 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1035 1036 /* 1037 * Blending win0 with the background color doesn't seem to work 1038 * correctly. We only get the background color, no matter the contents 1039 * of the win0 framebuffer. However, blending pre-multiplied color 1040 * with the default opaque black default background color is a no-op, 1041 * so we can just disable blending to get the correct result. 1042 */ 1043 if (fb->format->has_alpha && win_index > 0) { 1044 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1045 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1046 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1047 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1048 SRC_BLEND_M0(ALPHA_PER_PIX) | 1049 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1050 SRC_FACTOR_M0(ALPHA_ONE); 1051 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1052 1053 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1054 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1055 VOP_WIN_SET(vop, win, alpha_en, 1); 1056 } else { 1057 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1058 VOP_WIN_SET(vop, win, alpha_en, 0); 1059 } 1060 1061 VOP_WIN_SET(vop, win, enable, 1); 1062 vop->win_enabled |= BIT(win_index); 1063 spin_unlock(&vop->reg_lock); 1064 } 1065 1066 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1067 struct drm_atomic_state *state) 1068 { 1069 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1070 plane); 1071 struct vop_win *vop_win = to_vop_win(plane); 1072 const struct vop_win_data *win = vop_win->data; 1073 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1074 DRM_PLANE_NO_SCALING; 1075 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1076 DRM_PLANE_NO_SCALING; 1077 struct drm_crtc_state *crtc_state; 1078 1079 if (plane != new_plane_state->crtc->cursor) 1080 return -EINVAL; 1081 1082 if (!plane->state) 1083 return -EINVAL; 1084 1085 if (!plane->state->fb) 1086 return -EINVAL; 1087 1088 if (state) 1089 crtc_state = drm_atomic_get_existing_crtc_state(state, 1090 new_plane_state->crtc); 1091 else /* Special case for asynchronous cursor updates. */ 1092 crtc_state = plane->crtc->state; 1093 1094 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1095 min_scale, max_scale, 1096 true, true); 1097 } 1098 1099 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1100 struct drm_atomic_state *state) 1101 { 1102 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1103 plane); 1104 struct vop *vop = to_vop(plane->state->crtc); 1105 struct drm_framebuffer *old_fb = plane->state->fb; 1106 1107 plane->state->crtc_x = new_state->crtc_x; 1108 plane->state->crtc_y = new_state->crtc_y; 1109 plane->state->crtc_h = new_state->crtc_h; 1110 plane->state->crtc_w = new_state->crtc_w; 1111 plane->state->src_x = new_state->src_x; 1112 plane->state->src_y = new_state->src_y; 1113 plane->state->src_h = new_state->src_h; 1114 plane->state->src_w = new_state->src_w; 1115 swap(plane->state->fb, new_state->fb); 1116 1117 if (vop->is_enabled) { 1118 vop_plane_atomic_update(plane, state); 1119 spin_lock(&vop->reg_lock); 1120 vop_cfg_done(vop); 1121 spin_unlock(&vop->reg_lock); 1122 1123 /* 1124 * A scanout can still be occurring, so we can't drop the 1125 * reference to the old framebuffer. To solve this we get a 1126 * reference to old_fb and set a worker to release it later. 1127 * FIXME: if we perform 500 async_update calls before the 1128 * vblank, then we can have 500 different framebuffers waiting 1129 * to be released. 1130 */ 1131 if (old_fb && plane->state->fb != old_fb) { 1132 drm_framebuffer_get(old_fb); 1133 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1134 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1135 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1136 } 1137 } 1138 } 1139 1140 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1141 .atomic_check = vop_plane_atomic_check, 1142 .atomic_update = vop_plane_atomic_update, 1143 .atomic_disable = vop_plane_atomic_disable, 1144 .atomic_async_check = vop_plane_atomic_async_check, 1145 .atomic_async_update = vop_plane_atomic_async_update, 1146 }; 1147 1148 static const struct drm_plane_funcs vop_plane_funcs = { 1149 .update_plane = drm_atomic_helper_update_plane, 1150 .disable_plane = drm_atomic_helper_disable_plane, 1151 .destroy = drm_plane_cleanup, 1152 .reset = drm_atomic_helper_plane_reset, 1153 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1154 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1155 .format_mod_supported = rockchip_mod_supported, 1156 }; 1157 1158 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1159 { 1160 struct vop *vop = to_vop(crtc); 1161 unsigned long flags; 1162 1163 if (WARN_ON(!vop->is_enabled)) 1164 return -EPERM; 1165 1166 spin_lock_irqsave(&vop->irq_lock, flags); 1167 1168 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1169 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1170 1171 spin_unlock_irqrestore(&vop->irq_lock, flags); 1172 1173 return 0; 1174 } 1175 1176 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1177 { 1178 struct vop *vop = to_vop(crtc); 1179 unsigned long flags; 1180 1181 if (WARN_ON(!vop->is_enabled)) 1182 return; 1183 1184 spin_lock_irqsave(&vop->irq_lock, flags); 1185 1186 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1187 1188 spin_unlock_irqrestore(&vop->irq_lock, flags); 1189 } 1190 1191 static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, 1192 const struct drm_display_mode *mode) 1193 { 1194 struct vop *vop = to_vop(crtc); 1195 1196 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) 1197 return MODE_BAD_HVALUE; 1198 1199 return MODE_OK; 1200 } 1201 1202 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1203 const struct drm_display_mode *mode, 1204 struct drm_display_mode *adjusted_mode) 1205 { 1206 struct vop *vop = to_vop(crtc); 1207 unsigned long rate; 1208 1209 /* 1210 * Clock craziness. 1211 * 1212 * Key points: 1213 * 1214 * - DRM works in kHz. 1215 * - Clock framework works in Hz. 1216 * - Rockchip's clock driver picks the clock rate that is the 1217 * same _OR LOWER_ than the one requested. 1218 * 1219 * Action plan: 1220 * 1221 * 1. Try to set the exact rate first, and confirm the clock framework 1222 * can provide it. 1223 * 1224 * 2. If the clock framework cannot provide the exact rate, we should 1225 * add 999 Hz to the requested rate. That way if the clock we need 1226 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1227 * the clock framework will actually give us the right clock. 1228 * 1229 * 3. Get the clock framework to round the rate for us to tell us 1230 * what it will actually make. 1231 * 1232 * 4. Store the rounded up rate so that we don't need to worry about 1233 * this in the actual clk_set_rate(). 1234 */ 1235 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1236 if (rate / 1000 != adjusted_mode->clock) 1237 rate = clk_round_rate(vop->dclk, 1238 adjusted_mode->clock * 1000 + 999); 1239 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1240 1241 return true; 1242 } 1243 1244 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1245 { 1246 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1247 } 1248 1249 static u32 vop_lut_buffer_index(struct vop *vop) 1250 { 1251 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1252 } 1253 1254 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1255 { 1256 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1257 unsigned int i, bpc = ilog2(vop->data->lut_size); 1258 1259 for (i = 0; i < crtc->gamma_size; i++) { 1260 u32 word; 1261 1262 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1263 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1264 drm_color_lut_extract(lut[i].blue, bpc); 1265 writel(word, vop->lut_regs + i * 4); 1266 } 1267 } 1268 1269 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1270 struct drm_crtc_state *old_state) 1271 { 1272 struct drm_crtc_state *state = crtc->state; 1273 unsigned int idle; 1274 u32 lut_idx, old_idx; 1275 int ret; 1276 1277 if (!vop->lut_regs) 1278 return; 1279 1280 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1281 /* 1282 * To disable gamma (gamma_lut is null) or to write 1283 * an update to the LUT, clear dsp_lut_en. 1284 */ 1285 spin_lock(&vop->reg_lock); 1286 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1287 vop_cfg_done(vop); 1288 spin_unlock(&vop->reg_lock); 1289 1290 /* 1291 * In order to write the LUT to the internal memory, 1292 * we need to first make sure the dsp_lut_en bit is cleared. 1293 */ 1294 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1295 idle, !idle, 5, 30 * 1000); 1296 if (ret) { 1297 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1298 return; 1299 } 1300 1301 if (!state->gamma_lut) 1302 return; 1303 } else { 1304 /* 1305 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1306 * by setting update_gamma_lut then waiting for lut_buffer_index change 1307 */ 1308 old_idx = vop_lut_buffer_index(vop); 1309 } 1310 1311 spin_lock(&vop->reg_lock); 1312 vop_crtc_write_gamma_lut(vop, crtc); 1313 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1314 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1315 vop_cfg_done(vop); 1316 spin_unlock(&vop->reg_lock); 1317 1318 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1319 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1320 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1321 if (ret) { 1322 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1323 return; 1324 } 1325 1326 /* 1327 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1328 * in our backup of the regs. 1329 */ 1330 spin_lock(&vop->reg_lock); 1331 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1332 spin_unlock(&vop->reg_lock); 1333 } 1334 } 1335 1336 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1337 struct drm_atomic_state *state) 1338 { 1339 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1340 crtc); 1341 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1342 crtc); 1343 struct vop *vop = to_vop(crtc); 1344 1345 /* 1346 * Only update GAMMA if the 'active' flag is not changed, 1347 * otherwise it's updated by .atomic_enable. 1348 */ 1349 if (crtc_state->color_mgmt_changed && 1350 !crtc_state->active_changed) 1351 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1352 } 1353 1354 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1355 struct drm_atomic_state *state) 1356 { 1357 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1358 crtc); 1359 struct vop *vop = to_vop(crtc); 1360 const struct vop_data *vop_data = vop->data; 1361 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1362 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1363 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1364 u16 hdisplay = adjusted_mode->hdisplay; 1365 u16 htotal = adjusted_mode->htotal; 1366 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1367 u16 hact_end = hact_st + hdisplay; 1368 u16 vdisplay = adjusted_mode->vdisplay; 1369 u16 vtotal = adjusted_mode->vtotal; 1370 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1371 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1372 u16 vact_end = vact_st + vdisplay; 1373 uint32_t pin_pol, val; 1374 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1375 int ret; 1376 1377 if (old_state && old_state->self_refresh_active) { 1378 drm_crtc_vblank_on(crtc); 1379 rockchip_drm_set_win_enabled(crtc, true); 1380 return; 1381 } 1382 1383 mutex_lock(&vop->vop_lock); 1384 1385 WARN_ON(vop->event); 1386 1387 ret = vop_enable(crtc, old_state); 1388 if (ret) { 1389 mutex_unlock(&vop->vop_lock); 1390 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1391 return; 1392 } 1393 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1394 BIT(HSYNC_POSITIVE) : 0; 1395 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1396 BIT(VSYNC_POSITIVE) : 0; 1397 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1398 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1399 1400 switch (s->output_type) { 1401 case DRM_MODE_CONNECTOR_LVDS: 1402 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1403 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1404 VOP_REG_SET(vop, output, rgb_en, 1); 1405 break; 1406 case DRM_MODE_CONNECTOR_eDP: 1407 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1408 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1409 VOP_REG_SET(vop, output, edp_en, 1); 1410 break; 1411 case DRM_MODE_CONNECTOR_HDMIA: 1412 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1413 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1414 VOP_REG_SET(vop, output, hdmi_en, 1); 1415 break; 1416 case DRM_MODE_CONNECTOR_DSI: 1417 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1418 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1419 VOP_REG_SET(vop, output, mipi_en, 1); 1420 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1421 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1422 break; 1423 case DRM_MODE_CONNECTOR_DisplayPort: 1424 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1425 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1426 VOP_REG_SET(vop, output, dp_en, 1); 1427 break; 1428 default: 1429 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1430 s->output_type); 1431 } 1432 1433 /* 1434 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1435 */ 1436 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1437 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1438 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1439 1440 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1441 VOP_REG_SET(vop, common, pre_dither_down, 1); 1442 else 1443 VOP_REG_SET(vop, common, pre_dither_down, 0); 1444 1445 if (dither_bpc == 6) { 1446 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1447 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1448 VOP_REG_SET(vop, common, dither_down_en, 1); 1449 } else { 1450 VOP_REG_SET(vop, common, dither_down_en, 0); 1451 } 1452 1453 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1454 1455 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1456 val = hact_st << 16; 1457 val |= hact_end; 1458 VOP_REG_SET(vop, modeset, hact_st_end, val); 1459 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1460 1461 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1462 val = vact_st << 16; 1463 val |= vact_end; 1464 VOP_REG_SET(vop, modeset, vact_st_end, val); 1465 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1466 1467 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1468 1469 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1470 1471 VOP_REG_SET(vop, common, standby, 0); 1472 mutex_unlock(&vop->vop_lock); 1473 1474 /* 1475 * If we have a GAMMA LUT in the state, then let's make sure 1476 * it's updated. We might be coming out of suspend, 1477 * which means the LUT internal memory needs to be re-written. 1478 */ 1479 if (crtc->state->gamma_lut) 1480 vop_crtc_gamma_set(vop, crtc, old_state); 1481 } 1482 1483 static bool vop_fs_irq_is_pending(struct vop *vop) 1484 { 1485 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1486 } 1487 1488 static void vop_wait_for_irq_handler(struct vop *vop) 1489 { 1490 bool pending; 1491 int ret; 1492 1493 /* 1494 * Spin until frame start interrupt status bit goes low, which means 1495 * that interrupt handler was invoked and cleared it. The timeout of 1496 * 10 msecs is really too long, but it is just a safety measure if 1497 * something goes really wrong. The wait will only happen in the very 1498 * unlikely case of a vblank happening exactly at the same time and 1499 * shouldn't exceed microseconds range. 1500 */ 1501 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1502 !pending, 0, 10 * 1000); 1503 if (ret) 1504 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1505 1506 synchronize_irq(vop->irq); 1507 } 1508 1509 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1510 struct drm_atomic_state *state) 1511 { 1512 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1513 crtc); 1514 struct vop *vop = to_vop(crtc); 1515 struct drm_plane *plane; 1516 struct drm_plane_state *plane_state; 1517 struct rockchip_crtc_state *s; 1518 int afbc_planes = 0; 1519 1520 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1521 crtc_state->gamma_lut) { 1522 unsigned int len; 1523 1524 len = drm_color_lut_size(crtc_state->gamma_lut); 1525 if (len != crtc->gamma_size) { 1526 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1527 len, crtc->gamma_size); 1528 return -EINVAL; 1529 } 1530 } 1531 1532 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1533 plane_state = 1534 drm_atomic_get_plane_state(crtc_state->state, plane); 1535 if (IS_ERR(plane_state)) { 1536 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1537 plane->name); 1538 return PTR_ERR(plane_state); 1539 } 1540 1541 if (drm_is_afbc(plane_state->fb->modifier)) 1542 ++afbc_planes; 1543 } 1544 1545 if (afbc_planes > 1) { 1546 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1547 return -EINVAL; 1548 } 1549 1550 s = to_rockchip_crtc_state(crtc_state); 1551 s->enable_afbc = afbc_planes > 0; 1552 1553 return 0; 1554 } 1555 1556 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1557 struct drm_atomic_state *state) 1558 { 1559 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1560 crtc); 1561 struct drm_atomic_state *old_state = old_crtc_state->state; 1562 struct drm_plane_state *old_plane_state, *new_plane_state; 1563 struct vop *vop = to_vop(crtc); 1564 struct drm_plane *plane; 1565 struct rockchip_crtc_state *s; 1566 int i; 1567 1568 if (WARN_ON(!vop->is_enabled)) 1569 return; 1570 1571 spin_lock(&vop->reg_lock); 1572 1573 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1574 s = to_rockchip_crtc_state(crtc->state); 1575 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1576 vop_cfg_done(vop); 1577 1578 spin_unlock(&vop->reg_lock); 1579 1580 /* 1581 * There is a (rather unlikely) possiblity that a vblank interrupt 1582 * fired before we set the cfg_done bit. To avoid spuriously 1583 * signalling flip completion we need to wait for it to finish. 1584 */ 1585 vop_wait_for_irq_handler(vop); 1586 1587 spin_lock_irq(&crtc->dev->event_lock); 1588 if (crtc->state->event) { 1589 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1590 WARN_ON(vop->event); 1591 1592 vop->event = crtc->state->event; 1593 crtc->state->event = NULL; 1594 } 1595 spin_unlock_irq(&crtc->dev->event_lock); 1596 1597 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1598 new_plane_state, i) { 1599 if (!old_plane_state->fb) 1600 continue; 1601 1602 if (old_plane_state->fb == new_plane_state->fb) 1603 continue; 1604 1605 drm_framebuffer_get(old_plane_state->fb); 1606 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1607 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1608 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1609 } 1610 } 1611 1612 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1613 .mode_valid = vop_crtc_mode_valid, 1614 .mode_fixup = vop_crtc_mode_fixup, 1615 .atomic_check = vop_crtc_atomic_check, 1616 .atomic_begin = vop_crtc_atomic_begin, 1617 .atomic_flush = vop_crtc_atomic_flush, 1618 .atomic_enable = vop_crtc_atomic_enable, 1619 .atomic_disable = vop_crtc_atomic_disable, 1620 }; 1621 1622 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1623 { 1624 struct rockchip_crtc_state *rockchip_state; 1625 1626 if (WARN_ON(!crtc->state)) 1627 return NULL; 1628 1629 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), 1630 sizeof(*rockchip_state), GFP_KERNEL); 1631 if (!rockchip_state) 1632 return NULL; 1633 1634 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1635 return &rockchip_state->base; 1636 } 1637 1638 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1639 struct drm_crtc_state *state) 1640 { 1641 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1642 1643 __drm_atomic_helper_crtc_destroy_state(&s->base); 1644 kfree(s); 1645 } 1646 1647 static void vop_crtc_reset(struct drm_crtc *crtc) 1648 { 1649 struct rockchip_crtc_state *crtc_state = 1650 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1651 1652 if (crtc->state) 1653 vop_crtc_destroy_state(crtc, crtc->state); 1654 1655 if (crtc_state) 1656 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1657 else 1658 __drm_atomic_helper_crtc_reset(crtc, NULL); 1659 } 1660 1661 #ifdef CONFIG_DRM_ANALOGIX_DP 1662 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1663 { 1664 struct drm_connector *connector; 1665 struct drm_connector_list_iter conn_iter; 1666 1667 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1668 drm_for_each_connector_iter(connector, &conn_iter) { 1669 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1670 drm_connector_list_iter_end(&conn_iter); 1671 return connector; 1672 } 1673 } 1674 drm_connector_list_iter_end(&conn_iter); 1675 1676 return NULL; 1677 } 1678 1679 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1680 const char *source_name) 1681 { 1682 struct vop *vop = to_vop(crtc); 1683 struct drm_connector *connector; 1684 int ret; 1685 1686 connector = vop_get_edp_connector(vop); 1687 if (!connector) 1688 return -EINVAL; 1689 1690 if (source_name && strcmp(source_name, "auto") == 0) 1691 ret = analogix_dp_start_crc(connector); 1692 else if (!source_name) 1693 ret = analogix_dp_stop_crc(connector); 1694 else 1695 ret = -EINVAL; 1696 1697 return ret; 1698 } 1699 1700 static int 1701 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1702 size_t *values_cnt) 1703 { 1704 if (source_name && strcmp(source_name, "auto") != 0) 1705 return -EINVAL; 1706 1707 *values_cnt = 3; 1708 return 0; 1709 } 1710 1711 #else 1712 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1713 const char *source_name) 1714 { 1715 return -ENODEV; 1716 } 1717 1718 static int 1719 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1720 size_t *values_cnt) 1721 { 1722 return -ENODEV; 1723 } 1724 #endif 1725 1726 static const struct drm_crtc_funcs vop_crtc_funcs = { 1727 .set_config = drm_atomic_helper_set_config, 1728 .page_flip = drm_atomic_helper_page_flip, 1729 .destroy = drm_crtc_cleanup, 1730 .reset = vop_crtc_reset, 1731 .atomic_duplicate_state = vop_crtc_duplicate_state, 1732 .atomic_destroy_state = vop_crtc_destroy_state, 1733 .enable_vblank = vop_crtc_enable_vblank, 1734 .disable_vblank = vop_crtc_disable_vblank, 1735 .set_crc_source = vop_crtc_set_crc_source, 1736 .verify_crc_source = vop_crtc_verify_crc_source, 1737 }; 1738 1739 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1740 { 1741 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1742 struct drm_framebuffer *fb = val; 1743 1744 drm_crtc_vblank_put(&vop->crtc); 1745 drm_framebuffer_put(fb); 1746 } 1747 1748 static void vop_handle_vblank(struct vop *vop) 1749 { 1750 struct drm_device *drm = vop->drm_dev; 1751 struct drm_crtc *crtc = &vop->crtc; 1752 1753 spin_lock(&drm->event_lock); 1754 if (vop->event) { 1755 drm_crtc_send_vblank_event(crtc, vop->event); 1756 drm_crtc_vblank_put(crtc); 1757 vop->event = NULL; 1758 } 1759 spin_unlock(&drm->event_lock); 1760 1761 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1762 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1763 } 1764 1765 static irqreturn_t vop_isr(int irq, void *data) 1766 { 1767 struct vop *vop = data; 1768 struct drm_crtc *crtc = &vop->crtc; 1769 uint32_t active_irqs; 1770 int ret = IRQ_NONE; 1771 1772 /* 1773 * The irq is shared with the iommu. If the runtime-pm state of the 1774 * vop-device is disabled the irq has to be targeted at the iommu. 1775 */ 1776 if (!pm_runtime_get_if_in_use(vop->dev)) 1777 return IRQ_NONE; 1778 1779 if (vop_core_clks_enable(vop)) { 1780 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1781 goto out; 1782 } 1783 1784 /* 1785 * interrupt register has interrupt status, enable and clear bits, we 1786 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1787 */ 1788 spin_lock(&vop->irq_lock); 1789 1790 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1791 /* Clear all active interrupt sources */ 1792 if (active_irqs) 1793 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1794 1795 spin_unlock(&vop->irq_lock); 1796 1797 /* This is expected for vop iommu irqs, since the irq is shared */ 1798 if (!active_irqs) 1799 goto out_disable; 1800 1801 if (active_irqs & DSP_HOLD_VALID_INTR) { 1802 complete(&vop->dsp_hold_completion); 1803 active_irqs &= ~DSP_HOLD_VALID_INTR; 1804 ret = IRQ_HANDLED; 1805 } 1806 1807 if (active_irqs & LINE_FLAG_INTR) { 1808 complete(&vop->line_flag_completion); 1809 active_irqs &= ~LINE_FLAG_INTR; 1810 ret = IRQ_HANDLED; 1811 } 1812 1813 if (active_irqs & FS_INTR) { 1814 drm_crtc_handle_vblank(crtc); 1815 vop_handle_vblank(vop); 1816 active_irqs &= ~FS_INTR; 1817 ret = IRQ_HANDLED; 1818 } 1819 1820 /* Unhandled irqs are spurious. */ 1821 if (active_irqs) 1822 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1823 active_irqs); 1824 1825 out_disable: 1826 vop_core_clks_disable(vop); 1827 out: 1828 pm_runtime_put(vop->dev); 1829 return ret; 1830 } 1831 1832 static void vop_plane_add_properties(struct drm_plane *plane, 1833 const struct vop_win_data *win_data) 1834 { 1835 unsigned int flags = 0; 1836 1837 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1838 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1839 if (flags) 1840 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1841 DRM_MODE_ROTATE_0 | flags); 1842 } 1843 1844 static int vop_create_crtc(struct vop *vop) 1845 { 1846 const struct vop_data *vop_data = vop->data; 1847 struct device *dev = vop->dev; 1848 struct drm_device *drm_dev = vop->drm_dev; 1849 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1850 struct drm_crtc *crtc = &vop->crtc; 1851 struct device_node *port; 1852 int ret; 1853 int i; 1854 1855 /* 1856 * Create drm_plane for primary and cursor planes first, since we need 1857 * to pass them to drm_crtc_init_with_planes, which sets the 1858 * "possible_crtcs" to the newly initialized crtc. 1859 */ 1860 for (i = 0; i < vop_data->win_size; i++) { 1861 struct vop_win *vop_win = &vop->win[i]; 1862 const struct vop_win_data *win_data = vop_win->data; 1863 1864 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1865 win_data->type != DRM_PLANE_TYPE_CURSOR) 1866 continue; 1867 1868 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1869 0, &vop_plane_funcs, 1870 win_data->phy->data_formats, 1871 win_data->phy->nformats, 1872 win_data->phy->format_modifiers, 1873 win_data->type, NULL); 1874 if (ret) { 1875 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1876 ret); 1877 goto err_cleanup_planes; 1878 } 1879 1880 plane = &vop_win->base; 1881 drm_plane_helper_add(plane, &plane_helper_funcs); 1882 vop_plane_add_properties(plane, win_data); 1883 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1884 primary = plane; 1885 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1886 cursor = plane; 1887 } 1888 1889 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1890 &vop_crtc_funcs, NULL); 1891 if (ret) 1892 goto err_cleanup_planes; 1893 1894 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1895 if (vop->lut_regs) { 1896 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1897 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1898 } 1899 1900 /* 1901 * Create drm_planes for overlay windows with possible_crtcs restricted 1902 * to the newly created crtc. 1903 */ 1904 for (i = 0; i < vop_data->win_size; i++) { 1905 struct vop_win *vop_win = &vop->win[i]; 1906 const struct vop_win_data *win_data = vop_win->data; 1907 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1908 1909 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1910 continue; 1911 1912 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1913 possible_crtcs, 1914 &vop_plane_funcs, 1915 win_data->phy->data_formats, 1916 win_data->phy->nformats, 1917 win_data->phy->format_modifiers, 1918 win_data->type, NULL); 1919 if (ret) { 1920 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1921 ret); 1922 goto err_cleanup_crtc; 1923 } 1924 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1925 vop_plane_add_properties(&vop_win->base, win_data); 1926 } 1927 1928 port = of_get_child_by_name(dev->of_node, "port"); 1929 if (!port) { 1930 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1931 dev->of_node); 1932 ret = -ENOENT; 1933 goto err_cleanup_crtc; 1934 } 1935 1936 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1937 vop_fb_unref_worker); 1938 1939 init_completion(&vop->dsp_hold_completion); 1940 init_completion(&vop->line_flag_completion); 1941 crtc->port = port; 1942 1943 ret = drm_self_refresh_helper_init(crtc); 1944 if (ret) 1945 DRM_DEV_DEBUG_KMS(vop->dev, 1946 "Failed to init %s with SR helpers %d, ignoring\n", 1947 crtc->name, ret); 1948 1949 return 0; 1950 1951 err_cleanup_crtc: 1952 drm_crtc_cleanup(crtc); 1953 err_cleanup_planes: 1954 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1955 head) 1956 drm_plane_cleanup(plane); 1957 return ret; 1958 } 1959 1960 static void vop_destroy_crtc(struct vop *vop) 1961 { 1962 struct drm_crtc *crtc = &vop->crtc; 1963 struct drm_device *drm_dev = vop->drm_dev; 1964 struct drm_plane *plane, *tmp; 1965 1966 drm_self_refresh_helper_cleanup(crtc); 1967 1968 of_node_put(crtc->port); 1969 1970 /* 1971 * We need to cleanup the planes now. Why? 1972 * 1973 * The planes are "&vop->win[i].base". That means the memory is 1974 * all part of the big "struct vop" chunk of memory. That memory 1975 * was devm allocated and associated with this component. We need to 1976 * free it ourselves before vop_unbind() finishes. 1977 */ 1978 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1979 head) 1980 drm_plane_cleanup(plane); 1981 1982 /* 1983 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1984 * references the CRTC. 1985 */ 1986 drm_crtc_cleanup(crtc); 1987 drm_flip_work_cleanup(&vop->fb_unref_work); 1988 } 1989 1990 static int vop_initial(struct vop *vop) 1991 { 1992 struct reset_control *ahb_rst; 1993 int i, ret; 1994 1995 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1996 if (IS_ERR(vop->hclk)) { 1997 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1998 return PTR_ERR(vop->hclk); 1999 } 2000 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 2001 if (IS_ERR(vop->aclk)) { 2002 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 2003 return PTR_ERR(vop->aclk); 2004 } 2005 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 2006 if (IS_ERR(vop->dclk)) { 2007 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 2008 return PTR_ERR(vop->dclk); 2009 } 2010 2011 ret = pm_runtime_resume_and_get(vop->dev); 2012 if (ret < 0) { 2013 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 2014 return ret; 2015 } 2016 2017 ret = clk_prepare(vop->dclk); 2018 if (ret < 0) { 2019 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 2020 goto err_put_pm_runtime; 2021 } 2022 2023 /* Enable both the hclk and aclk to setup the vop */ 2024 ret = clk_prepare_enable(vop->hclk); 2025 if (ret < 0) { 2026 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 2027 goto err_unprepare_dclk; 2028 } 2029 2030 ret = clk_prepare_enable(vop->aclk); 2031 if (ret < 0) { 2032 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2033 goto err_disable_hclk; 2034 } 2035 2036 /* 2037 * do hclk_reset, reset all vop registers. 2038 */ 2039 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2040 if (IS_ERR(ahb_rst)) { 2041 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2042 ret = PTR_ERR(ahb_rst); 2043 goto err_disable_aclk; 2044 } 2045 reset_control_assert(ahb_rst); 2046 usleep_range(10, 20); 2047 reset_control_deassert(ahb_rst); 2048 2049 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2050 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2051 2052 for (i = 0; i < vop->len; i += sizeof(u32)) 2053 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2054 2055 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2056 VOP_REG_SET(vop, common, dsp_blank, 0); 2057 2058 for (i = 0; i < vop->data->win_size; i++) { 2059 struct vop_win *vop_win = &vop->win[i]; 2060 const struct vop_win_data *win = vop_win->data; 2061 int channel = i * 2 + 1; 2062 2063 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2064 vop_win_disable(vop, vop_win); 2065 VOP_WIN_SET(vop, win, gate, 1); 2066 } 2067 2068 vop_cfg_done(vop); 2069 2070 /* 2071 * do dclk_reset, let all config take affect. 2072 */ 2073 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2074 if (IS_ERR(vop->dclk_rst)) { 2075 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2076 ret = PTR_ERR(vop->dclk_rst); 2077 goto err_disable_aclk; 2078 } 2079 reset_control_assert(vop->dclk_rst); 2080 usleep_range(10, 20); 2081 reset_control_deassert(vop->dclk_rst); 2082 2083 clk_disable(vop->hclk); 2084 clk_disable(vop->aclk); 2085 2086 vop->is_enabled = false; 2087 2088 pm_runtime_put_sync(vop->dev); 2089 2090 return 0; 2091 2092 err_disable_aclk: 2093 clk_disable_unprepare(vop->aclk); 2094 err_disable_hclk: 2095 clk_disable_unprepare(vop->hclk); 2096 err_unprepare_dclk: 2097 clk_unprepare(vop->dclk); 2098 err_put_pm_runtime: 2099 pm_runtime_put_sync(vop->dev); 2100 return ret; 2101 } 2102 2103 /* 2104 * Initialize the vop->win array elements. 2105 */ 2106 static void vop_win_init(struct vop *vop) 2107 { 2108 const struct vop_data *vop_data = vop->data; 2109 unsigned int i; 2110 2111 for (i = 0; i < vop_data->win_size; i++) { 2112 struct vop_win *vop_win = &vop->win[i]; 2113 const struct vop_win_data *win_data = &vop_data->win[i]; 2114 2115 vop_win->data = win_data; 2116 vop_win->vop = vop; 2117 2118 if (vop_data->win_yuv2yuv) 2119 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2120 } 2121 } 2122 2123 /** 2124 * rockchip_drm_wait_vact_end 2125 * @crtc: CRTC to enable line flag 2126 * @mstimeout: millisecond for timeout 2127 * 2128 * Wait for vact_end line flag irq or timeout. 2129 * 2130 * Returns: 2131 * Zero on success, negative errno on failure. 2132 */ 2133 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2134 { 2135 struct vop *vop = to_vop(crtc); 2136 unsigned long jiffies_left; 2137 int ret = 0; 2138 2139 if (!crtc || !vop->is_enabled) 2140 return -ENODEV; 2141 2142 mutex_lock(&vop->vop_lock); 2143 if (mstimeout <= 0) { 2144 ret = -EINVAL; 2145 goto out; 2146 } 2147 2148 if (vop_line_flag_irq_is_enabled(vop)) { 2149 ret = -EBUSY; 2150 goto out; 2151 } 2152 2153 reinit_completion(&vop->line_flag_completion); 2154 vop_line_flag_irq_enable(vop); 2155 2156 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2157 msecs_to_jiffies(mstimeout)); 2158 vop_line_flag_irq_disable(vop); 2159 2160 if (jiffies_left == 0) { 2161 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2162 ret = -ETIMEDOUT; 2163 goto out; 2164 } 2165 2166 out: 2167 mutex_unlock(&vop->vop_lock); 2168 return ret; 2169 } 2170 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2171 2172 static int vop_bind(struct device *dev, struct device *master, void *data) 2173 { 2174 struct platform_device *pdev = to_platform_device(dev); 2175 const struct vop_data *vop_data; 2176 struct drm_device *drm_dev = data; 2177 struct vop *vop; 2178 struct resource *res; 2179 int ret, irq; 2180 2181 vop_data = of_device_get_match_data(dev); 2182 if (!vop_data) 2183 return -ENODEV; 2184 2185 /* Allocate vop struct and its vop_win array */ 2186 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2187 GFP_KERNEL); 2188 if (!vop) 2189 return -ENOMEM; 2190 2191 vop->dev = dev; 2192 vop->data = vop_data; 2193 vop->drm_dev = drm_dev; 2194 dev_set_drvdata(dev, vop); 2195 2196 vop_win_init(vop); 2197 2198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2199 vop->regs = devm_ioremap_resource(dev, res); 2200 if (IS_ERR(vop->regs)) 2201 return PTR_ERR(vop->regs); 2202 vop->len = resource_size(res); 2203 2204 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2205 if (res) { 2206 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2207 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2208 return -EINVAL; 2209 } 2210 vop->lut_regs = devm_ioremap_resource(dev, res); 2211 if (IS_ERR(vop->lut_regs)) 2212 return PTR_ERR(vop->lut_regs); 2213 } 2214 2215 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2216 if (!vop->regsbak) 2217 return -ENOMEM; 2218 2219 irq = platform_get_irq(pdev, 0); 2220 if (irq < 0) { 2221 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2222 return irq; 2223 } 2224 vop->irq = (unsigned int)irq; 2225 2226 spin_lock_init(&vop->reg_lock); 2227 spin_lock_init(&vop->irq_lock); 2228 mutex_init(&vop->vop_lock); 2229 2230 ret = vop_create_crtc(vop); 2231 if (ret) 2232 return ret; 2233 2234 pm_runtime_enable(&pdev->dev); 2235 2236 ret = vop_initial(vop); 2237 if (ret < 0) { 2238 DRM_DEV_ERROR(&pdev->dev, 2239 "cannot initial vop dev - err %d\n", ret); 2240 goto err_disable_pm_runtime; 2241 } 2242 2243 ret = devm_request_irq(dev, vop->irq, vop_isr, 2244 IRQF_SHARED, dev_name(dev), vop); 2245 if (ret) 2246 goto err_disable_pm_runtime; 2247 2248 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2249 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); 2250 if (IS_ERR(vop->rgb)) { 2251 ret = PTR_ERR(vop->rgb); 2252 goto err_disable_pm_runtime; 2253 } 2254 } 2255 2256 rockchip_drm_dma_init_device(drm_dev, dev); 2257 2258 return 0; 2259 2260 err_disable_pm_runtime: 2261 pm_runtime_disable(&pdev->dev); 2262 vop_destroy_crtc(vop); 2263 return ret; 2264 } 2265 2266 static void vop_unbind(struct device *dev, struct device *master, void *data) 2267 { 2268 struct vop *vop = dev_get_drvdata(dev); 2269 2270 if (vop->rgb) 2271 rockchip_rgb_fini(vop->rgb); 2272 2273 pm_runtime_disable(dev); 2274 vop_destroy_crtc(vop); 2275 2276 clk_unprepare(vop->aclk); 2277 clk_unprepare(vop->hclk); 2278 clk_unprepare(vop->dclk); 2279 } 2280 2281 const struct component_ops vop_component_ops = { 2282 .bind = vop_bind, 2283 .unbind = vop_unbind, 2284 }; 2285 EXPORT_SYMBOL_GPL(vop_component_ops); 2286