1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_flip_work.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_gem_atomic_helper.h> 27 #include <drm/drm_gem_framebuffer_helper.h> 28 #include <drm/drm_plane_helper.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/drm_self_refresh_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #ifdef CONFIG_DRM_ANALOGIX_DP 34 #include <drm/bridge/analogix_dp.h> 35 #endif 36 37 #include "rockchip_drm_drv.h" 38 #include "rockchip_drm_gem.h" 39 #include "rockchip_drm_fb.h" 40 #include "rockchip_drm_vop.h" 41 #include "rockchip_rgb.h" 42 43 #define VOP_WIN_SET(vop, win, name, v) \ 44 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 45 #define VOP_SCL_SET(vop, win, name, v) \ 46 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->ext->name, \ 49 win->base, ~0, v, #name) 50 51 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 52 do { \ 53 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 54 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 55 } while (0) 56 57 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 58 do { \ 59 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 60 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 61 } while (0) 62 63 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 64 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 65 66 #define VOP_REG_SET(vop, group, name, v) \ 67 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 68 69 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 70 do { \ 71 int i, reg = 0, mask = 0; \ 72 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 73 if (vop->data->intr->intrs[i] & type) { \ 74 reg |= (v) << i; \ 75 mask |= 1 << i; \ 76 } \ 77 } \ 78 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 79 } while (0) 80 #define VOP_INTR_GET_TYPE(vop, name, type) \ 81 vop_get_intr_type(vop, &vop->data->intr->name, type) 82 83 #define VOP_WIN_GET(vop, win, name) \ 84 vop_read_reg(vop, win->base, &win->phy->name) 85 86 #define VOP_WIN_HAS_REG(win, name) \ 87 (!!(win->phy->name.mask)) 88 89 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 91 92 #define VOP_WIN_TO_INDEX(vop_win) \ 93 ((vop_win) - (vop_win)->vop->win) 94 95 #define VOP_AFBC_SET(vop, name, v) \ 96 do { \ 97 if ((vop)->data->afbc) \ 98 vop_reg_set((vop), &(vop)->data->afbc->name, \ 99 0, ~0, v, #name); \ 100 } while (0) 101 102 #define to_vop(x) container_of(x, struct vop, crtc) 103 #define to_vop_win(x) container_of(x, struct vop_win, base) 104 105 #define AFBC_FMT_RGB565 0x0 106 #define AFBC_FMT_U8U8U8U8 0x5 107 #define AFBC_FMT_U8U8U8 0x4 108 109 #define AFBC_TILE_16x16 BIT(4) 110 111 /* 112 * The coefficients of the following matrix are all fixed points. 113 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 114 * They are all represented in two's complement. 115 */ 116 static const uint32_t bt601_yuv2rgb[] = { 117 0x4A8, 0x0, 0x662, 118 0x4A8, 0x1E6F, 0x1CBF, 119 0x4A8, 0x812, 0x0, 120 0x321168, 0x0877CF, 0x2EB127 121 }; 122 123 enum vop_pending { 124 VOP_PENDING_FB_UNREF, 125 }; 126 127 struct vop_win { 128 struct drm_plane base; 129 const struct vop_win_data *data; 130 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 131 struct vop *vop; 132 }; 133 134 struct rockchip_rgb; 135 struct vop { 136 struct drm_crtc crtc; 137 struct device *dev; 138 struct drm_device *drm_dev; 139 bool is_enabled; 140 141 struct completion dsp_hold_completion; 142 unsigned int win_enabled; 143 144 /* protected by dev->event_lock */ 145 struct drm_pending_vblank_event *event; 146 147 struct drm_flip_work fb_unref_work; 148 unsigned long pending; 149 150 struct completion line_flag_completion; 151 152 const struct vop_data *data; 153 154 uint32_t *regsbak; 155 void __iomem *regs; 156 void __iomem *lut_regs; 157 158 /* physical map length of vop register */ 159 uint32_t len; 160 161 /* one time only one process allowed to config the register */ 162 spinlock_t reg_lock; 163 /* lock vop irq reg */ 164 spinlock_t irq_lock; 165 /* protects crtc enable/disable */ 166 struct mutex vop_lock; 167 168 unsigned int irq; 169 170 /* vop AHP clk */ 171 struct clk *hclk; 172 /* vop dclk */ 173 struct clk *dclk; 174 /* vop share memory frequency */ 175 struct clk *aclk; 176 177 /* vop dclk reset */ 178 struct reset_control *dclk_rst; 179 180 /* optional internal rgb encoder */ 181 struct rockchip_rgb *rgb; 182 183 struct vop_win win[]; 184 }; 185 186 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 187 { 188 writel(v, vop->regs + offset); 189 vop->regsbak[offset >> 2] = v; 190 } 191 192 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 193 { 194 return readl(vop->regs + offset); 195 } 196 197 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 198 const struct vop_reg *reg) 199 { 200 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 201 } 202 203 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 204 uint32_t _offset, uint32_t _mask, uint32_t v, 205 const char *reg_name) 206 { 207 int offset, mask, shift; 208 209 if (!reg || !reg->mask) { 210 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 211 return; 212 } 213 214 offset = reg->offset + _offset; 215 mask = reg->mask & _mask; 216 shift = reg->shift; 217 218 if (reg->write_mask) { 219 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 220 } else { 221 uint32_t cached_val = vop->regsbak[offset >> 2]; 222 223 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 224 vop->regsbak[offset >> 2] = v; 225 } 226 227 if (reg->relaxed) 228 writel_relaxed(v, vop->regs + offset); 229 else 230 writel(v, vop->regs + offset); 231 } 232 233 static inline uint32_t vop_get_intr_type(struct vop *vop, 234 const struct vop_reg *reg, int type) 235 { 236 uint32_t i, ret = 0; 237 uint32_t regs = vop_read_reg(vop, 0, reg); 238 239 for (i = 0; i < vop->data->intr->nintrs; i++) { 240 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 241 ret |= vop->data->intr->intrs[i]; 242 } 243 244 return ret; 245 } 246 247 static inline void vop_cfg_done(struct vop *vop) 248 { 249 VOP_REG_SET(vop, common, cfg_done, 1); 250 } 251 252 static bool has_rb_swapped(uint32_t format) 253 { 254 switch (format) { 255 case DRM_FORMAT_XBGR8888: 256 case DRM_FORMAT_ABGR8888: 257 case DRM_FORMAT_BGR888: 258 case DRM_FORMAT_BGR565: 259 return true; 260 default: 261 return false; 262 } 263 } 264 265 static bool has_uv_swapped(uint32_t format) 266 { 267 switch (format) { 268 case DRM_FORMAT_NV21: 269 case DRM_FORMAT_NV61: 270 case DRM_FORMAT_NV42: 271 return true; 272 default: 273 return false; 274 } 275 } 276 277 static enum vop_data_format vop_convert_format(uint32_t format) 278 { 279 switch (format) { 280 case DRM_FORMAT_XRGB8888: 281 case DRM_FORMAT_ARGB8888: 282 case DRM_FORMAT_XBGR8888: 283 case DRM_FORMAT_ABGR8888: 284 return VOP_FMT_ARGB8888; 285 case DRM_FORMAT_RGB888: 286 case DRM_FORMAT_BGR888: 287 return VOP_FMT_RGB888; 288 case DRM_FORMAT_RGB565: 289 case DRM_FORMAT_BGR565: 290 return VOP_FMT_RGB565; 291 case DRM_FORMAT_NV12: 292 case DRM_FORMAT_NV21: 293 return VOP_FMT_YUV420SP; 294 case DRM_FORMAT_NV16: 295 case DRM_FORMAT_NV61: 296 return VOP_FMT_YUV422SP; 297 case DRM_FORMAT_NV24: 298 case DRM_FORMAT_NV42: 299 return VOP_FMT_YUV444SP; 300 default: 301 DRM_ERROR("unsupported format[%08x]\n", format); 302 return -EINVAL; 303 } 304 } 305 306 static int vop_convert_afbc_format(uint32_t format) 307 { 308 switch (format) { 309 case DRM_FORMAT_XRGB8888: 310 case DRM_FORMAT_ARGB8888: 311 case DRM_FORMAT_XBGR8888: 312 case DRM_FORMAT_ABGR8888: 313 return AFBC_FMT_U8U8U8U8; 314 case DRM_FORMAT_RGB888: 315 case DRM_FORMAT_BGR888: 316 return AFBC_FMT_U8U8U8; 317 case DRM_FORMAT_RGB565: 318 case DRM_FORMAT_BGR565: 319 return AFBC_FMT_RGB565; 320 /* either of the below should not be reachable */ 321 default: 322 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 323 return -EINVAL; 324 } 325 326 return -EINVAL; 327 } 328 329 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 330 uint32_t dst, bool is_horizontal, 331 int vsu_mode, int *vskiplines) 332 { 333 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 334 335 if (vskiplines) 336 *vskiplines = 0; 337 338 if (is_horizontal) { 339 if (mode == SCALE_UP) 340 val = GET_SCL_FT_BIC(src, dst); 341 else if (mode == SCALE_DOWN) 342 val = GET_SCL_FT_BILI_DN(src, dst); 343 } else { 344 if (mode == SCALE_UP) { 345 if (vsu_mode == SCALE_UP_BIL) 346 val = GET_SCL_FT_BILI_UP(src, dst); 347 else 348 val = GET_SCL_FT_BIC(src, dst); 349 } else if (mode == SCALE_DOWN) { 350 if (vskiplines) { 351 *vskiplines = scl_get_vskiplines(src, dst); 352 val = scl_get_bili_dn_vskip(src, dst, 353 *vskiplines); 354 } else { 355 val = GET_SCL_FT_BILI_DN(src, dst); 356 } 357 } 358 } 359 360 return val; 361 } 362 363 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 364 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 365 uint32_t dst_h, const struct drm_format_info *info) 366 { 367 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 368 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 369 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 370 bool is_yuv = false; 371 uint16_t cbcr_src_w = src_w / info->hsub; 372 uint16_t cbcr_src_h = src_h / info->vsub; 373 uint16_t vsu_mode; 374 uint16_t lb_mode; 375 uint32_t val; 376 int vskiplines; 377 378 if (info->is_yuv) 379 is_yuv = true; 380 381 if (dst_w > 3840) { 382 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 383 return; 384 } 385 386 if (!win->phy->scl->ext) { 387 VOP_SCL_SET(vop, win, scale_yrgb_x, 388 scl_cal_scale2(src_w, dst_w)); 389 VOP_SCL_SET(vop, win, scale_yrgb_y, 390 scl_cal_scale2(src_h, dst_h)); 391 if (is_yuv) { 392 VOP_SCL_SET(vop, win, scale_cbcr_x, 393 scl_cal_scale2(cbcr_src_w, dst_w)); 394 VOP_SCL_SET(vop, win, scale_cbcr_y, 395 scl_cal_scale2(cbcr_src_h, dst_h)); 396 } 397 return; 398 } 399 400 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 401 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 402 403 if (is_yuv) { 404 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 405 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 406 if (cbcr_hor_scl_mode == SCALE_DOWN) 407 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 408 else 409 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 410 } else { 411 if (yrgb_hor_scl_mode == SCALE_DOWN) 412 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 413 else 414 lb_mode = scl_vop_cal_lb_mode(src_w, false); 415 } 416 417 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 418 if (lb_mode == LB_RGB_3840X2) { 419 if (yrgb_ver_scl_mode != SCALE_NONE) { 420 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 421 return; 422 } 423 if (cbcr_ver_scl_mode != SCALE_NONE) { 424 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 425 return; 426 } 427 vsu_mode = SCALE_UP_BIL; 428 } else if (lb_mode == LB_RGB_2560X4) { 429 vsu_mode = SCALE_UP_BIL; 430 } else { 431 vsu_mode = SCALE_UP_BIC; 432 } 433 434 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 435 true, 0, NULL); 436 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 437 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 438 false, vsu_mode, &vskiplines); 439 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 440 441 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 442 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 443 444 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 445 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 446 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 447 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 448 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 449 if (is_yuv) { 450 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 451 dst_w, true, 0, NULL); 452 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 453 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 454 dst_h, false, vsu_mode, &vskiplines); 455 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 456 457 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 458 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 459 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 460 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 461 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 462 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 463 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 464 } 465 } 466 467 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 468 { 469 unsigned long flags; 470 471 if (WARN_ON(!vop->is_enabled)) 472 return; 473 474 spin_lock_irqsave(&vop->irq_lock, flags); 475 476 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 477 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 478 479 spin_unlock_irqrestore(&vop->irq_lock, flags); 480 } 481 482 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 483 { 484 unsigned long flags; 485 486 if (WARN_ON(!vop->is_enabled)) 487 return; 488 489 spin_lock_irqsave(&vop->irq_lock, flags); 490 491 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 492 493 spin_unlock_irqrestore(&vop->irq_lock, flags); 494 } 495 496 /* 497 * (1) each frame starts at the start of the Vsync pulse which is signaled by 498 * the "FRAME_SYNC" interrupt. 499 * (2) the active data region of each frame ends at dsp_vact_end 500 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 501 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 502 * 503 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 504 * Interrupts 505 * LINE_FLAG -------------------------------+ 506 * FRAME_SYNC ----+ | 507 * | | 508 * v v 509 * | Vsync | Vbp | Vactive | Vfp | 510 * ^ ^ ^ ^ 511 * | | | | 512 * | | | | 513 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 514 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 515 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 516 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 517 */ 518 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 519 { 520 uint32_t line_flag_irq; 521 unsigned long flags; 522 523 spin_lock_irqsave(&vop->irq_lock, flags); 524 525 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 526 527 spin_unlock_irqrestore(&vop->irq_lock, flags); 528 529 return !!line_flag_irq; 530 } 531 532 static void vop_line_flag_irq_enable(struct vop *vop) 533 { 534 unsigned long flags; 535 536 if (WARN_ON(!vop->is_enabled)) 537 return; 538 539 spin_lock_irqsave(&vop->irq_lock, flags); 540 541 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 542 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 543 544 spin_unlock_irqrestore(&vop->irq_lock, flags); 545 } 546 547 static void vop_line_flag_irq_disable(struct vop *vop) 548 { 549 unsigned long flags; 550 551 if (WARN_ON(!vop->is_enabled)) 552 return; 553 554 spin_lock_irqsave(&vop->irq_lock, flags); 555 556 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 557 558 spin_unlock_irqrestore(&vop->irq_lock, flags); 559 } 560 561 static int vop_core_clks_enable(struct vop *vop) 562 { 563 int ret; 564 565 ret = clk_enable(vop->hclk); 566 if (ret < 0) 567 return ret; 568 569 ret = clk_enable(vop->aclk); 570 if (ret < 0) 571 goto err_disable_hclk; 572 573 return 0; 574 575 err_disable_hclk: 576 clk_disable(vop->hclk); 577 return ret; 578 } 579 580 static void vop_core_clks_disable(struct vop *vop) 581 { 582 clk_disable(vop->aclk); 583 clk_disable(vop->hclk); 584 } 585 586 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 587 { 588 const struct vop_win_data *win = vop_win->data; 589 590 if (win->phy->scl && win->phy->scl->ext) { 591 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 592 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 593 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 594 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 595 } 596 597 VOP_WIN_SET(vop, win, enable, 0); 598 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 599 } 600 601 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 602 { 603 struct vop *vop = to_vop(crtc); 604 int ret, i; 605 606 ret = pm_runtime_get_sync(vop->dev); 607 if (ret < 0) { 608 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 609 return ret; 610 } 611 612 ret = vop_core_clks_enable(vop); 613 if (WARN_ON(ret < 0)) 614 goto err_put_pm_runtime; 615 616 ret = clk_enable(vop->dclk); 617 if (WARN_ON(ret < 0)) 618 goto err_disable_core; 619 620 /* 621 * Slave iommu shares power, irq and clock with vop. It was associated 622 * automatically with this master device via common driver code. 623 * Now that we have enabled the clock we attach it to the shared drm 624 * mapping. 625 */ 626 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 627 if (ret) { 628 DRM_DEV_ERROR(vop->dev, 629 "failed to attach dma mapping, %d\n", ret); 630 goto err_disable_dclk; 631 } 632 633 spin_lock(&vop->reg_lock); 634 for (i = 0; i < vop->len; i += 4) 635 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 636 637 /* 638 * We need to make sure that all windows are disabled before we 639 * enable the crtc. Otherwise we might try to scan from a destroyed 640 * buffer later. 641 * 642 * In the case of enable-after-PSR, we don't need to worry about this 643 * case since the buffer is guaranteed to be valid and disabling the 644 * window will result in screen glitches on PSR exit. 645 */ 646 if (!old_state || !old_state->self_refresh_active) { 647 for (i = 0; i < vop->data->win_size; i++) { 648 struct vop_win *vop_win = &vop->win[i]; 649 650 vop_win_disable(vop, vop_win); 651 } 652 } 653 654 if (vop->data->afbc) { 655 struct rockchip_crtc_state *s; 656 /* 657 * Disable AFBC and forget there was a vop window with AFBC 658 */ 659 VOP_AFBC_SET(vop, enable, 0); 660 s = to_rockchip_crtc_state(crtc->state); 661 s->enable_afbc = false; 662 } 663 664 vop_cfg_done(vop); 665 666 spin_unlock(&vop->reg_lock); 667 668 /* 669 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 670 */ 671 vop->is_enabled = true; 672 673 spin_lock(&vop->reg_lock); 674 675 VOP_REG_SET(vop, common, standby, 1); 676 677 spin_unlock(&vop->reg_lock); 678 679 drm_crtc_vblank_on(crtc); 680 681 return 0; 682 683 err_disable_dclk: 684 clk_disable(vop->dclk); 685 err_disable_core: 686 vop_core_clks_disable(vop); 687 err_put_pm_runtime: 688 pm_runtime_put_sync(vop->dev); 689 return ret; 690 } 691 692 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 693 { 694 struct vop *vop = to_vop(crtc); 695 int i; 696 697 spin_lock(&vop->reg_lock); 698 699 for (i = 0; i < vop->data->win_size; i++) { 700 struct vop_win *vop_win = &vop->win[i]; 701 const struct vop_win_data *win = vop_win->data; 702 703 VOP_WIN_SET(vop, win, enable, 704 enabled && (vop->win_enabled & BIT(i))); 705 } 706 vop_cfg_done(vop); 707 708 spin_unlock(&vop->reg_lock); 709 } 710 711 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 712 struct drm_atomic_state *state) 713 { 714 struct vop *vop = to_vop(crtc); 715 716 WARN_ON(vop->event); 717 718 if (crtc->state->self_refresh_active) 719 rockchip_drm_set_win_enabled(crtc, false); 720 721 mutex_lock(&vop->vop_lock); 722 723 drm_crtc_vblank_off(crtc); 724 725 if (crtc->state->self_refresh_active) 726 goto out; 727 728 /* 729 * Vop standby will take effect at end of current frame, 730 * if dsp hold valid irq happen, it means standby complete. 731 * 732 * we must wait standby complete when we want to disable aclk, 733 * if not, memory bus maybe dead. 734 */ 735 reinit_completion(&vop->dsp_hold_completion); 736 vop_dsp_hold_valid_irq_enable(vop); 737 738 spin_lock(&vop->reg_lock); 739 740 VOP_REG_SET(vop, common, standby, 1); 741 742 spin_unlock(&vop->reg_lock); 743 744 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 745 msecs_to_jiffies(200))) 746 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 747 748 vop_dsp_hold_valid_irq_disable(vop); 749 750 vop->is_enabled = false; 751 752 /* 753 * vop standby complete, so iommu detach is safe. 754 */ 755 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 756 757 clk_disable(vop->dclk); 758 vop_core_clks_disable(vop); 759 pm_runtime_put(vop->dev); 760 761 out: 762 mutex_unlock(&vop->vop_lock); 763 764 if (crtc->state->event && !crtc->state->active) { 765 spin_lock_irq(&crtc->dev->event_lock); 766 drm_crtc_send_vblank_event(crtc, crtc->state->event); 767 spin_unlock_irq(&crtc->dev->event_lock); 768 769 crtc->state->event = NULL; 770 } 771 } 772 773 static void vop_plane_destroy(struct drm_plane *plane) 774 { 775 drm_plane_cleanup(plane); 776 } 777 778 static inline bool rockchip_afbc(u64 modifier) 779 { 780 return modifier == ROCKCHIP_AFBC_MOD; 781 } 782 783 static bool rockchip_mod_supported(struct drm_plane *plane, 784 u32 format, u64 modifier) 785 { 786 if (modifier == DRM_FORMAT_MOD_LINEAR) 787 return true; 788 789 if (!rockchip_afbc(modifier)) { 790 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 791 792 return false; 793 } 794 795 return vop_convert_afbc_format(format) >= 0; 796 } 797 798 static int vop_plane_atomic_check(struct drm_plane *plane, 799 struct drm_atomic_state *state) 800 { 801 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 802 plane); 803 struct drm_crtc *crtc = new_plane_state->crtc; 804 struct drm_crtc_state *crtc_state; 805 struct drm_framebuffer *fb = new_plane_state->fb; 806 struct vop_win *vop_win = to_vop_win(plane); 807 const struct vop_win_data *win = vop_win->data; 808 int ret; 809 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 810 DRM_PLANE_HELPER_NO_SCALING; 811 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 812 DRM_PLANE_HELPER_NO_SCALING; 813 814 if (!crtc || WARN_ON(!fb)) 815 return 0; 816 817 crtc_state = drm_atomic_get_existing_crtc_state(state, 818 crtc); 819 if (WARN_ON(!crtc_state)) 820 return -EINVAL; 821 822 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 823 min_scale, max_scale, 824 true, true); 825 if (ret) 826 return ret; 827 828 if (!new_plane_state->visible) 829 return 0; 830 831 ret = vop_convert_format(fb->format->format); 832 if (ret < 0) 833 return ret; 834 835 /* 836 * Src.x1 can be odd when do clip, but yuv plane start point 837 * need align with 2 pixel. 838 */ 839 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 840 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 841 return -EINVAL; 842 } 843 844 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 845 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 846 return -EINVAL; 847 } 848 849 if (rockchip_afbc(fb->modifier)) { 850 struct vop *vop = to_vop(crtc); 851 852 if (!vop->data->afbc) { 853 DRM_ERROR("vop does not support AFBC\n"); 854 return -EINVAL; 855 } 856 857 ret = vop_convert_afbc_format(fb->format->format); 858 if (ret < 0) 859 return ret; 860 861 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 862 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 863 new_plane_state->src.x1, 864 new_plane_state->src.y1, fb->offsets[0]); 865 return -EINVAL; 866 } 867 868 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 869 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 870 new_plane_state->rotation); 871 return -EINVAL; 872 } 873 } 874 875 return 0; 876 } 877 878 static void vop_plane_atomic_disable(struct drm_plane *plane, 879 struct drm_atomic_state *state) 880 { 881 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 882 plane); 883 struct vop_win *vop_win = to_vop_win(plane); 884 struct vop *vop = to_vop(old_state->crtc); 885 886 if (!old_state->crtc) 887 return; 888 889 spin_lock(&vop->reg_lock); 890 891 vop_win_disable(vop, vop_win); 892 893 spin_unlock(&vop->reg_lock); 894 } 895 896 static void vop_plane_atomic_update(struct drm_plane *plane, 897 struct drm_atomic_state *state) 898 { 899 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 900 plane); 901 struct drm_crtc *crtc = new_state->crtc; 902 struct vop_win *vop_win = to_vop_win(plane); 903 const struct vop_win_data *win = vop_win->data; 904 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 905 struct vop *vop = to_vop(new_state->crtc); 906 struct drm_framebuffer *fb = new_state->fb; 907 unsigned int actual_w, actual_h; 908 unsigned int dsp_stx, dsp_sty; 909 uint32_t act_info, dsp_info, dsp_st; 910 struct drm_rect *src = &new_state->src; 911 struct drm_rect *dest = &new_state->dst; 912 struct drm_gem_object *obj, *uv_obj; 913 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 914 unsigned long offset; 915 dma_addr_t dma_addr; 916 uint32_t val; 917 bool rb_swap, uv_swap; 918 int win_index = VOP_WIN_TO_INDEX(vop_win); 919 int format; 920 int is_yuv = fb->format->is_yuv; 921 int i; 922 923 /* 924 * can't update plane when vop is disabled. 925 */ 926 if (WARN_ON(!crtc)) 927 return; 928 929 if (WARN_ON(!vop->is_enabled)) 930 return; 931 932 if (!new_state->visible) { 933 vop_plane_atomic_disable(plane, state); 934 return; 935 } 936 937 obj = fb->obj[0]; 938 rk_obj = to_rockchip_obj(obj); 939 940 actual_w = drm_rect_width(src) >> 16; 941 actual_h = drm_rect_height(src) >> 16; 942 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 943 944 dsp_info = (drm_rect_height(dest) - 1) << 16; 945 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 946 947 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 948 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 949 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 950 951 offset = (src->x1 >> 16) * fb->format->cpp[0]; 952 offset += (src->y1 >> 16) * fb->pitches[0]; 953 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 954 955 /* 956 * For y-mirroring we need to move address 957 * to the beginning of the last line. 958 */ 959 if (new_state->rotation & DRM_MODE_REFLECT_Y) 960 dma_addr += (actual_h - 1) * fb->pitches[0]; 961 962 format = vop_convert_format(fb->format->format); 963 964 spin_lock(&vop->reg_lock); 965 966 if (rockchip_afbc(fb->modifier)) { 967 int afbc_format = vop_convert_afbc_format(fb->format->format); 968 969 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 970 VOP_AFBC_SET(vop, hreg_block_split, 0); 971 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 972 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 973 VOP_AFBC_SET(vop, pic_size, act_info); 974 } 975 976 VOP_WIN_SET(vop, win, format, format); 977 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 978 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 979 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 980 VOP_WIN_SET(vop, win, y_mir_en, 981 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 982 VOP_WIN_SET(vop, win, x_mir_en, 983 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 984 985 if (is_yuv) { 986 int hsub = fb->format->hsub; 987 int vsub = fb->format->vsub; 988 int bpp = fb->format->cpp[1]; 989 990 uv_obj = fb->obj[1]; 991 rk_uv_obj = to_rockchip_obj(uv_obj); 992 993 offset = (src->x1 >> 16) * bpp / hsub; 994 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 995 996 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 997 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 998 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 999 1000 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 1001 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 1002 win_yuv2yuv, 1003 y2r_coefficients[i], 1004 bt601_yuv2rgb[i]); 1005 } 1006 1007 uv_swap = has_uv_swapped(fb->format->format); 1008 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1009 } 1010 1011 if (win->phy->scl) 1012 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1013 drm_rect_width(dest), drm_rect_height(dest), 1014 fb->format); 1015 1016 VOP_WIN_SET(vop, win, act_info, act_info); 1017 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1018 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1019 1020 rb_swap = has_rb_swapped(fb->format->format); 1021 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1022 1023 /* 1024 * Blending win0 with the background color doesn't seem to work 1025 * correctly. We only get the background color, no matter the contents 1026 * of the win0 framebuffer. However, blending pre-multiplied color 1027 * with the default opaque black default background color is a no-op, 1028 * so we can just disable blending to get the correct result. 1029 */ 1030 if (fb->format->has_alpha && win_index > 0) { 1031 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1032 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1033 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1034 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1035 SRC_BLEND_M0(ALPHA_PER_PIX) | 1036 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1037 SRC_FACTOR_M0(ALPHA_ONE); 1038 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1039 1040 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1041 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1042 VOP_WIN_SET(vop, win, alpha_en, 1); 1043 } else { 1044 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1045 VOP_WIN_SET(vop, win, alpha_en, 0); 1046 } 1047 1048 VOP_WIN_SET(vop, win, enable, 1); 1049 vop->win_enabled |= BIT(win_index); 1050 spin_unlock(&vop->reg_lock); 1051 } 1052 1053 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1054 struct drm_atomic_state *state) 1055 { 1056 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1057 plane); 1058 struct vop_win *vop_win = to_vop_win(plane); 1059 const struct vop_win_data *win = vop_win->data; 1060 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1061 DRM_PLANE_HELPER_NO_SCALING; 1062 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1063 DRM_PLANE_HELPER_NO_SCALING; 1064 struct drm_crtc_state *crtc_state; 1065 1066 if (plane != new_plane_state->crtc->cursor) 1067 return -EINVAL; 1068 1069 if (!plane->state) 1070 return -EINVAL; 1071 1072 if (!plane->state->fb) 1073 return -EINVAL; 1074 1075 if (state) 1076 crtc_state = drm_atomic_get_existing_crtc_state(state, 1077 new_plane_state->crtc); 1078 else /* Special case for asynchronous cursor updates. */ 1079 crtc_state = plane->crtc->state; 1080 1081 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1082 min_scale, max_scale, 1083 true, true); 1084 } 1085 1086 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1087 struct drm_atomic_state *state) 1088 { 1089 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1090 plane); 1091 struct vop *vop = to_vop(plane->state->crtc); 1092 struct drm_framebuffer *old_fb = plane->state->fb; 1093 1094 plane->state->crtc_x = new_state->crtc_x; 1095 plane->state->crtc_y = new_state->crtc_y; 1096 plane->state->crtc_h = new_state->crtc_h; 1097 plane->state->crtc_w = new_state->crtc_w; 1098 plane->state->src_x = new_state->src_x; 1099 plane->state->src_y = new_state->src_y; 1100 plane->state->src_h = new_state->src_h; 1101 plane->state->src_w = new_state->src_w; 1102 swap(plane->state->fb, new_state->fb); 1103 1104 if (vop->is_enabled) { 1105 vop_plane_atomic_update(plane, state); 1106 spin_lock(&vop->reg_lock); 1107 vop_cfg_done(vop); 1108 spin_unlock(&vop->reg_lock); 1109 1110 /* 1111 * A scanout can still be occurring, so we can't drop the 1112 * reference to the old framebuffer. To solve this we get a 1113 * reference to old_fb and set a worker to release it later. 1114 * FIXME: if we perform 500 async_update calls before the 1115 * vblank, then we can have 500 different framebuffers waiting 1116 * to be released. 1117 */ 1118 if (old_fb && plane->state->fb != old_fb) { 1119 drm_framebuffer_get(old_fb); 1120 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1121 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1122 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1123 } 1124 } 1125 } 1126 1127 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1128 .atomic_check = vop_plane_atomic_check, 1129 .atomic_update = vop_plane_atomic_update, 1130 .atomic_disable = vop_plane_atomic_disable, 1131 .atomic_async_check = vop_plane_atomic_async_check, 1132 .atomic_async_update = vop_plane_atomic_async_update, 1133 }; 1134 1135 static const struct drm_plane_funcs vop_plane_funcs = { 1136 .update_plane = drm_atomic_helper_update_plane, 1137 .disable_plane = drm_atomic_helper_disable_plane, 1138 .destroy = vop_plane_destroy, 1139 .reset = drm_atomic_helper_plane_reset, 1140 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1141 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1142 .format_mod_supported = rockchip_mod_supported, 1143 }; 1144 1145 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1146 { 1147 struct vop *vop = to_vop(crtc); 1148 unsigned long flags; 1149 1150 if (WARN_ON(!vop->is_enabled)) 1151 return -EPERM; 1152 1153 spin_lock_irqsave(&vop->irq_lock, flags); 1154 1155 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1156 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1157 1158 spin_unlock_irqrestore(&vop->irq_lock, flags); 1159 1160 return 0; 1161 } 1162 1163 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1164 { 1165 struct vop *vop = to_vop(crtc); 1166 unsigned long flags; 1167 1168 if (WARN_ON(!vop->is_enabled)) 1169 return; 1170 1171 spin_lock_irqsave(&vop->irq_lock, flags); 1172 1173 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1174 1175 spin_unlock_irqrestore(&vop->irq_lock, flags); 1176 } 1177 1178 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1179 const struct drm_display_mode *mode, 1180 struct drm_display_mode *adjusted_mode) 1181 { 1182 struct vop *vop = to_vop(crtc); 1183 unsigned long rate; 1184 1185 /* 1186 * Clock craziness. 1187 * 1188 * Key points: 1189 * 1190 * - DRM works in in kHz. 1191 * - Clock framework works in Hz. 1192 * - Rockchip's clock driver picks the clock rate that is the 1193 * same _OR LOWER_ than the one requested. 1194 * 1195 * Action plan: 1196 * 1197 * 1. Try to set the exact rate first, and confirm the clock framework 1198 * can provide it. 1199 * 1200 * 2. If the clock framework cannot provide the exact rate, we should 1201 * add 999 Hz to the requested rate. That way if the clock we need 1202 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1203 * the clock framework will actually give us the right clock. 1204 * 1205 * 3. Get the clock framework to round the rate for us to tell us 1206 * what it will actually make. 1207 * 1208 * 4. Store the rounded up rate so that we don't need to worry about 1209 * this in the actual clk_set_rate(). 1210 */ 1211 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1212 if (rate / 1000 != adjusted_mode->clock) 1213 rate = clk_round_rate(vop->dclk, 1214 adjusted_mode->clock * 1000 + 999); 1215 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1216 1217 return true; 1218 } 1219 1220 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1221 { 1222 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1223 } 1224 1225 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1226 { 1227 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1228 unsigned int i; 1229 1230 for (i = 0; i < crtc->gamma_size; i++) { 1231 u32 word; 1232 1233 word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1234 (drm_color_lut_extract(lut[i].green, 10) << 10) | 1235 drm_color_lut_extract(lut[i].blue, 10); 1236 writel(word, vop->lut_regs + i * 4); 1237 } 1238 } 1239 1240 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1241 struct drm_crtc_state *old_state) 1242 { 1243 struct drm_crtc_state *state = crtc->state; 1244 unsigned int idle; 1245 int ret; 1246 1247 if (!vop->lut_regs) 1248 return; 1249 /* 1250 * To disable gamma (gamma_lut is null) or to write 1251 * an update to the LUT, clear dsp_lut_en. 1252 */ 1253 spin_lock(&vop->reg_lock); 1254 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1255 vop_cfg_done(vop); 1256 spin_unlock(&vop->reg_lock); 1257 1258 /* 1259 * In order to write the LUT to the internal memory, 1260 * we need to first make sure the dsp_lut_en bit is cleared. 1261 */ 1262 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1263 idle, !idle, 5, 30 * 1000); 1264 if (ret) { 1265 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1266 return; 1267 } 1268 1269 if (!state->gamma_lut) 1270 return; 1271 1272 spin_lock(&vop->reg_lock); 1273 vop_crtc_write_gamma_lut(vop, crtc); 1274 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1275 vop_cfg_done(vop); 1276 spin_unlock(&vop->reg_lock); 1277 } 1278 1279 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1280 struct drm_atomic_state *state) 1281 { 1282 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1283 crtc); 1284 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1285 crtc); 1286 struct vop *vop = to_vop(crtc); 1287 1288 /* 1289 * Only update GAMMA if the 'active' flag is not changed, 1290 * otherwise it's updated by .atomic_enable. 1291 */ 1292 if (crtc_state->color_mgmt_changed && 1293 !crtc_state->active_changed) 1294 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1295 } 1296 1297 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1298 struct drm_atomic_state *state) 1299 { 1300 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1301 crtc); 1302 struct vop *vop = to_vop(crtc); 1303 const struct vop_data *vop_data = vop->data; 1304 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1305 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1306 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1307 u16 hdisplay = adjusted_mode->hdisplay; 1308 u16 htotal = adjusted_mode->htotal; 1309 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1310 u16 hact_end = hact_st + hdisplay; 1311 u16 vdisplay = adjusted_mode->vdisplay; 1312 u16 vtotal = adjusted_mode->vtotal; 1313 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1314 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1315 u16 vact_end = vact_st + vdisplay; 1316 uint32_t pin_pol, val; 1317 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1318 int ret; 1319 1320 if (old_state && old_state->self_refresh_active) { 1321 drm_crtc_vblank_on(crtc); 1322 rockchip_drm_set_win_enabled(crtc, true); 1323 return; 1324 } 1325 1326 /* 1327 * If we have a GAMMA LUT in the state, then let's make sure 1328 * it's updated. We might be coming out of suspend, 1329 * which means the LUT internal memory needs to be re-written. 1330 */ 1331 if (crtc->state->gamma_lut) 1332 vop_crtc_gamma_set(vop, crtc, old_state); 1333 1334 mutex_lock(&vop->vop_lock); 1335 1336 WARN_ON(vop->event); 1337 1338 ret = vop_enable(crtc, old_state); 1339 if (ret) { 1340 mutex_unlock(&vop->vop_lock); 1341 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1342 return; 1343 } 1344 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1345 BIT(HSYNC_POSITIVE) : 0; 1346 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1347 BIT(VSYNC_POSITIVE) : 0; 1348 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1349 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1350 1351 switch (s->output_type) { 1352 case DRM_MODE_CONNECTOR_LVDS: 1353 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1354 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1355 VOP_REG_SET(vop, output, rgb_en, 1); 1356 break; 1357 case DRM_MODE_CONNECTOR_eDP: 1358 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1359 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1360 VOP_REG_SET(vop, output, edp_en, 1); 1361 break; 1362 case DRM_MODE_CONNECTOR_HDMIA: 1363 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1364 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1365 VOP_REG_SET(vop, output, hdmi_en, 1); 1366 break; 1367 case DRM_MODE_CONNECTOR_DSI: 1368 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1369 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1370 VOP_REG_SET(vop, output, mipi_en, 1); 1371 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1372 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1373 break; 1374 case DRM_MODE_CONNECTOR_DisplayPort: 1375 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1376 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1377 VOP_REG_SET(vop, output, dp_en, 1); 1378 break; 1379 default: 1380 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1381 s->output_type); 1382 } 1383 1384 /* 1385 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1386 */ 1387 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1388 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1389 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1390 1391 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1392 VOP_REG_SET(vop, common, pre_dither_down, 1); 1393 else 1394 VOP_REG_SET(vop, common, pre_dither_down, 0); 1395 1396 if (dither_bpc == 6) { 1397 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1398 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1399 VOP_REG_SET(vop, common, dither_down_en, 1); 1400 } else { 1401 VOP_REG_SET(vop, common, dither_down_en, 0); 1402 } 1403 1404 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1405 1406 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1407 val = hact_st << 16; 1408 val |= hact_end; 1409 VOP_REG_SET(vop, modeset, hact_st_end, val); 1410 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1411 1412 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1413 val = vact_st << 16; 1414 val |= vact_end; 1415 VOP_REG_SET(vop, modeset, vact_st_end, val); 1416 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1417 1418 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1419 1420 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1421 1422 VOP_REG_SET(vop, common, standby, 0); 1423 mutex_unlock(&vop->vop_lock); 1424 } 1425 1426 static bool vop_fs_irq_is_pending(struct vop *vop) 1427 { 1428 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1429 } 1430 1431 static void vop_wait_for_irq_handler(struct vop *vop) 1432 { 1433 bool pending; 1434 int ret; 1435 1436 /* 1437 * Spin until frame start interrupt status bit goes low, which means 1438 * that interrupt handler was invoked and cleared it. The timeout of 1439 * 10 msecs is really too long, but it is just a safety measure if 1440 * something goes really wrong. The wait will only happen in the very 1441 * unlikely case of a vblank happening exactly at the same time and 1442 * shouldn't exceed microseconds range. 1443 */ 1444 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1445 !pending, 0, 10 * 1000); 1446 if (ret) 1447 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1448 1449 synchronize_irq(vop->irq); 1450 } 1451 1452 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1453 struct drm_atomic_state *state) 1454 { 1455 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1456 crtc); 1457 struct vop *vop = to_vop(crtc); 1458 struct drm_plane *plane; 1459 struct drm_plane_state *plane_state; 1460 struct rockchip_crtc_state *s; 1461 int afbc_planes = 0; 1462 1463 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1464 crtc_state->gamma_lut) { 1465 unsigned int len; 1466 1467 len = drm_color_lut_size(crtc_state->gamma_lut); 1468 if (len != crtc->gamma_size) { 1469 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1470 len, crtc->gamma_size); 1471 return -EINVAL; 1472 } 1473 } 1474 1475 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1476 plane_state = 1477 drm_atomic_get_plane_state(crtc_state->state, plane); 1478 if (IS_ERR(plane_state)) { 1479 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1480 plane->name); 1481 return PTR_ERR(plane_state); 1482 } 1483 1484 if (drm_is_afbc(plane_state->fb->modifier)) 1485 ++afbc_planes; 1486 } 1487 1488 if (afbc_planes > 1) { 1489 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1490 return -EINVAL; 1491 } 1492 1493 s = to_rockchip_crtc_state(crtc_state); 1494 s->enable_afbc = afbc_planes > 0; 1495 1496 return 0; 1497 } 1498 1499 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1500 struct drm_atomic_state *state) 1501 { 1502 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1503 crtc); 1504 struct drm_atomic_state *old_state = old_crtc_state->state; 1505 struct drm_plane_state *old_plane_state, *new_plane_state; 1506 struct vop *vop = to_vop(crtc); 1507 struct drm_plane *plane; 1508 struct rockchip_crtc_state *s; 1509 int i; 1510 1511 if (WARN_ON(!vop->is_enabled)) 1512 return; 1513 1514 spin_lock(&vop->reg_lock); 1515 1516 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1517 s = to_rockchip_crtc_state(crtc->state); 1518 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1519 vop_cfg_done(vop); 1520 1521 spin_unlock(&vop->reg_lock); 1522 1523 /* 1524 * There is a (rather unlikely) possiblity that a vblank interrupt 1525 * fired before we set the cfg_done bit. To avoid spuriously 1526 * signalling flip completion we need to wait for it to finish. 1527 */ 1528 vop_wait_for_irq_handler(vop); 1529 1530 spin_lock_irq(&crtc->dev->event_lock); 1531 if (crtc->state->event) { 1532 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1533 WARN_ON(vop->event); 1534 1535 vop->event = crtc->state->event; 1536 crtc->state->event = NULL; 1537 } 1538 spin_unlock_irq(&crtc->dev->event_lock); 1539 1540 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1541 new_plane_state, i) { 1542 if (!old_plane_state->fb) 1543 continue; 1544 1545 if (old_plane_state->fb == new_plane_state->fb) 1546 continue; 1547 1548 drm_framebuffer_get(old_plane_state->fb); 1549 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1550 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1551 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1552 } 1553 } 1554 1555 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1556 .mode_fixup = vop_crtc_mode_fixup, 1557 .atomic_check = vop_crtc_atomic_check, 1558 .atomic_begin = vop_crtc_atomic_begin, 1559 .atomic_flush = vop_crtc_atomic_flush, 1560 .atomic_enable = vop_crtc_atomic_enable, 1561 .atomic_disable = vop_crtc_atomic_disable, 1562 }; 1563 1564 static void vop_crtc_destroy(struct drm_crtc *crtc) 1565 { 1566 drm_crtc_cleanup(crtc); 1567 } 1568 1569 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1570 { 1571 struct rockchip_crtc_state *rockchip_state; 1572 1573 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1574 if (!rockchip_state) 1575 return NULL; 1576 1577 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1578 return &rockchip_state->base; 1579 } 1580 1581 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1582 struct drm_crtc_state *state) 1583 { 1584 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1585 1586 __drm_atomic_helper_crtc_destroy_state(&s->base); 1587 kfree(s); 1588 } 1589 1590 static void vop_crtc_reset(struct drm_crtc *crtc) 1591 { 1592 struct rockchip_crtc_state *crtc_state = 1593 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1594 1595 if (crtc->state) 1596 vop_crtc_destroy_state(crtc, crtc->state); 1597 1598 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1599 } 1600 1601 #ifdef CONFIG_DRM_ANALOGIX_DP 1602 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1603 { 1604 struct drm_connector *connector; 1605 struct drm_connector_list_iter conn_iter; 1606 1607 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1608 drm_for_each_connector_iter(connector, &conn_iter) { 1609 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1610 drm_connector_list_iter_end(&conn_iter); 1611 return connector; 1612 } 1613 } 1614 drm_connector_list_iter_end(&conn_iter); 1615 1616 return NULL; 1617 } 1618 1619 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1620 const char *source_name) 1621 { 1622 struct vop *vop = to_vop(crtc); 1623 struct drm_connector *connector; 1624 int ret; 1625 1626 connector = vop_get_edp_connector(vop); 1627 if (!connector) 1628 return -EINVAL; 1629 1630 if (source_name && strcmp(source_name, "auto") == 0) 1631 ret = analogix_dp_start_crc(connector); 1632 else if (!source_name) 1633 ret = analogix_dp_stop_crc(connector); 1634 else 1635 ret = -EINVAL; 1636 1637 return ret; 1638 } 1639 1640 static int 1641 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1642 size_t *values_cnt) 1643 { 1644 if (source_name && strcmp(source_name, "auto") != 0) 1645 return -EINVAL; 1646 1647 *values_cnt = 3; 1648 return 0; 1649 } 1650 1651 #else 1652 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1653 const char *source_name) 1654 { 1655 return -ENODEV; 1656 } 1657 1658 static int 1659 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1660 size_t *values_cnt) 1661 { 1662 return -ENODEV; 1663 } 1664 #endif 1665 1666 static const struct drm_crtc_funcs vop_crtc_funcs = { 1667 .set_config = drm_atomic_helper_set_config, 1668 .page_flip = drm_atomic_helper_page_flip, 1669 .destroy = vop_crtc_destroy, 1670 .reset = vop_crtc_reset, 1671 .atomic_duplicate_state = vop_crtc_duplicate_state, 1672 .atomic_destroy_state = vop_crtc_destroy_state, 1673 .enable_vblank = vop_crtc_enable_vblank, 1674 .disable_vblank = vop_crtc_disable_vblank, 1675 .set_crc_source = vop_crtc_set_crc_source, 1676 .verify_crc_source = vop_crtc_verify_crc_source, 1677 }; 1678 1679 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1680 { 1681 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1682 struct drm_framebuffer *fb = val; 1683 1684 drm_crtc_vblank_put(&vop->crtc); 1685 drm_framebuffer_put(fb); 1686 } 1687 1688 static void vop_handle_vblank(struct vop *vop) 1689 { 1690 struct drm_device *drm = vop->drm_dev; 1691 struct drm_crtc *crtc = &vop->crtc; 1692 1693 spin_lock(&drm->event_lock); 1694 if (vop->event) { 1695 drm_crtc_send_vblank_event(crtc, vop->event); 1696 drm_crtc_vblank_put(crtc); 1697 vop->event = NULL; 1698 } 1699 spin_unlock(&drm->event_lock); 1700 1701 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1702 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1703 } 1704 1705 static irqreturn_t vop_isr(int irq, void *data) 1706 { 1707 struct vop *vop = data; 1708 struct drm_crtc *crtc = &vop->crtc; 1709 uint32_t active_irqs; 1710 int ret = IRQ_NONE; 1711 1712 /* 1713 * The irq is shared with the iommu. If the runtime-pm state of the 1714 * vop-device is disabled the irq has to be targeted at the iommu. 1715 */ 1716 if (!pm_runtime_get_if_in_use(vop->dev)) 1717 return IRQ_NONE; 1718 1719 if (vop_core_clks_enable(vop)) { 1720 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1721 goto out; 1722 } 1723 1724 /* 1725 * interrupt register has interrupt status, enable and clear bits, we 1726 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1727 */ 1728 spin_lock(&vop->irq_lock); 1729 1730 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1731 /* Clear all active interrupt sources */ 1732 if (active_irqs) 1733 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1734 1735 spin_unlock(&vop->irq_lock); 1736 1737 /* This is expected for vop iommu irqs, since the irq is shared */ 1738 if (!active_irqs) 1739 goto out_disable; 1740 1741 if (active_irqs & DSP_HOLD_VALID_INTR) { 1742 complete(&vop->dsp_hold_completion); 1743 active_irqs &= ~DSP_HOLD_VALID_INTR; 1744 ret = IRQ_HANDLED; 1745 } 1746 1747 if (active_irqs & LINE_FLAG_INTR) { 1748 complete(&vop->line_flag_completion); 1749 active_irqs &= ~LINE_FLAG_INTR; 1750 ret = IRQ_HANDLED; 1751 } 1752 1753 if (active_irqs & FS_INTR) { 1754 drm_crtc_handle_vblank(crtc); 1755 vop_handle_vblank(vop); 1756 active_irqs &= ~FS_INTR; 1757 ret = IRQ_HANDLED; 1758 } 1759 1760 /* Unhandled irqs are spurious. */ 1761 if (active_irqs) 1762 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1763 active_irqs); 1764 1765 out_disable: 1766 vop_core_clks_disable(vop); 1767 out: 1768 pm_runtime_put(vop->dev); 1769 return ret; 1770 } 1771 1772 static void vop_plane_add_properties(struct drm_plane *plane, 1773 const struct vop_win_data *win_data) 1774 { 1775 unsigned int flags = 0; 1776 1777 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1778 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1779 if (flags) 1780 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1781 DRM_MODE_ROTATE_0 | flags); 1782 } 1783 1784 static int vop_create_crtc(struct vop *vop) 1785 { 1786 const struct vop_data *vop_data = vop->data; 1787 struct device *dev = vop->dev; 1788 struct drm_device *drm_dev = vop->drm_dev; 1789 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1790 struct drm_crtc *crtc = &vop->crtc; 1791 struct device_node *port; 1792 int ret; 1793 int i; 1794 1795 /* 1796 * Create drm_plane for primary and cursor planes first, since we need 1797 * to pass them to drm_crtc_init_with_planes, which sets the 1798 * "possible_crtcs" to the newly initialized crtc. 1799 */ 1800 for (i = 0; i < vop_data->win_size; i++) { 1801 struct vop_win *vop_win = &vop->win[i]; 1802 const struct vop_win_data *win_data = vop_win->data; 1803 1804 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1805 win_data->type != DRM_PLANE_TYPE_CURSOR) 1806 continue; 1807 1808 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1809 0, &vop_plane_funcs, 1810 win_data->phy->data_formats, 1811 win_data->phy->nformats, 1812 win_data->phy->format_modifiers, 1813 win_data->type, NULL); 1814 if (ret) { 1815 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1816 ret); 1817 goto err_cleanup_planes; 1818 } 1819 1820 plane = &vop_win->base; 1821 drm_plane_helper_add(plane, &plane_helper_funcs); 1822 vop_plane_add_properties(plane, win_data); 1823 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1824 primary = plane; 1825 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1826 cursor = plane; 1827 } 1828 1829 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1830 &vop_crtc_funcs, NULL); 1831 if (ret) 1832 goto err_cleanup_planes; 1833 1834 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1835 if (vop->lut_regs) { 1836 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1837 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1838 } 1839 1840 /* 1841 * Create drm_planes for overlay windows with possible_crtcs restricted 1842 * to the newly created crtc. 1843 */ 1844 for (i = 0; i < vop_data->win_size; i++) { 1845 struct vop_win *vop_win = &vop->win[i]; 1846 const struct vop_win_data *win_data = vop_win->data; 1847 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1848 1849 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1850 continue; 1851 1852 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1853 possible_crtcs, 1854 &vop_plane_funcs, 1855 win_data->phy->data_formats, 1856 win_data->phy->nformats, 1857 win_data->phy->format_modifiers, 1858 win_data->type, NULL); 1859 if (ret) { 1860 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1861 ret); 1862 goto err_cleanup_crtc; 1863 } 1864 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1865 vop_plane_add_properties(&vop_win->base, win_data); 1866 } 1867 1868 port = of_get_child_by_name(dev->of_node, "port"); 1869 if (!port) { 1870 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1871 dev->of_node); 1872 ret = -ENOENT; 1873 goto err_cleanup_crtc; 1874 } 1875 1876 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1877 vop_fb_unref_worker); 1878 1879 init_completion(&vop->dsp_hold_completion); 1880 init_completion(&vop->line_flag_completion); 1881 crtc->port = port; 1882 1883 ret = drm_self_refresh_helper_init(crtc); 1884 if (ret) 1885 DRM_DEV_DEBUG_KMS(vop->dev, 1886 "Failed to init %s with SR helpers %d, ignoring\n", 1887 crtc->name, ret); 1888 1889 return 0; 1890 1891 err_cleanup_crtc: 1892 drm_crtc_cleanup(crtc); 1893 err_cleanup_planes: 1894 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1895 head) 1896 drm_plane_cleanup(plane); 1897 return ret; 1898 } 1899 1900 static void vop_destroy_crtc(struct vop *vop) 1901 { 1902 struct drm_crtc *crtc = &vop->crtc; 1903 struct drm_device *drm_dev = vop->drm_dev; 1904 struct drm_plane *plane, *tmp; 1905 1906 drm_self_refresh_helper_cleanup(crtc); 1907 1908 of_node_put(crtc->port); 1909 1910 /* 1911 * We need to cleanup the planes now. Why? 1912 * 1913 * The planes are "&vop->win[i].base". That means the memory is 1914 * all part of the big "struct vop" chunk of memory. That memory 1915 * was devm allocated and associated with this component. We need to 1916 * free it ourselves before vop_unbind() finishes. 1917 */ 1918 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1919 head) 1920 vop_plane_destroy(plane); 1921 1922 /* 1923 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1924 * references the CRTC. 1925 */ 1926 drm_crtc_cleanup(crtc); 1927 drm_flip_work_cleanup(&vop->fb_unref_work); 1928 } 1929 1930 static int vop_initial(struct vop *vop) 1931 { 1932 struct reset_control *ahb_rst; 1933 int i, ret; 1934 1935 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1936 if (IS_ERR(vop->hclk)) { 1937 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1938 return PTR_ERR(vop->hclk); 1939 } 1940 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1941 if (IS_ERR(vop->aclk)) { 1942 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1943 return PTR_ERR(vop->aclk); 1944 } 1945 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1946 if (IS_ERR(vop->dclk)) { 1947 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1948 return PTR_ERR(vop->dclk); 1949 } 1950 1951 ret = pm_runtime_get_sync(vop->dev); 1952 if (ret < 0) { 1953 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1954 return ret; 1955 } 1956 1957 ret = clk_prepare(vop->dclk); 1958 if (ret < 0) { 1959 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1960 goto err_put_pm_runtime; 1961 } 1962 1963 /* Enable both the hclk and aclk to setup the vop */ 1964 ret = clk_prepare_enable(vop->hclk); 1965 if (ret < 0) { 1966 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1967 goto err_unprepare_dclk; 1968 } 1969 1970 ret = clk_prepare_enable(vop->aclk); 1971 if (ret < 0) { 1972 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1973 goto err_disable_hclk; 1974 } 1975 1976 /* 1977 * do hclk_reset, reset all vop registers. 1978 */ 1979 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1980 if (IS_ERR(ahb_rst)) { 1981 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1982 ret = PTR_ERR(ahb_rst); 1983 goto err_disable_aclk; 1984 } 1985 reset_control_assert(ahb_rst); 1986 usleep_range(10, 20); 1987 reset_control_deassert(ahb_rst); 1988 1989 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1990 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1991 1992 for (i = 0; i < vop->len; i += sizeof(u32)) 1993 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1994 1995 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1996 VOP_REG_SET(vop, common, dsp_blank, 0); 1997 1998 for (i = 0; i < vop->data->win_size; i++) { 1999 struct vop_win *vop_win = &vop->win[i]; 2000 const struct vop_win_data *win = vop_win->data; 2001 int channel = i * 2 + 1; 2002 2003 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2004 vop_win_disable(vop, vop_win); 2005 VOP_WIN_SET(vop, win, gate, 1); 2006 } 2007 2008 vop_cfg_done(vop); 2009 2010 /* 2011 * do dclk_reset, let all config take affect. 2012 */ 2013 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2014 if (IS_ERR(vop->dclk_rst)) { 2015 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2016 ret = PTR_ERR(vop->dclk_rst); 2017 goto err_disable_aclk; 2018 } 2019 reset_control_assert(vop->dclk_rst); 2020 usleep_range(10, 20); 2021 reset_control_deassert(vop->dclk_rst); 2022 2023 clk_disable(vop->hclk); 2024 clk_disable(vop->aclk); 2025 2026 vop->is_enabled = false; 2027 2028 pm_runtime_put_sync(vop->dev); 2029 2030 return 0; 2031 2032 err_disable_aclk: 2033 clk_disable_unprepare(vop->aclk); 2034 err_disable_hclk: 2035 clk_disable_unprepare(vop->hclk); 2036 err_unprepare_dclk: 2037 clk_unprepare(vop->dclk); 2038 err_put_pm_runtime: 2039 pm_runtime_put_sync(vop->dev); 2040 return ret; 2041 } 2042 2043 /* 2044 * Initialize the vop->win array elements. 2045 */ 2046 static void vop_win_init(struct vop *vop) 2047 { 2048 const struct vop_data *vop_data = vop->data; 2049 unsigned int i; 2050 2051 for (i = 0; i < vop_data->win_size; i++) { 2052 struct vop_win *vop_win = &vop->win[i]; 2053 const struct vop_win_data *win_data = &vop_data->win[i]; 2054 2055 vop_win->data = win_data; 2056 vop_win->vop = vop; 2057 2058 if (vop_data->win_yuv2yuv) 2059 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2060 } 2061 } 2062 2063 /** 2064 * rockchip_drm_wait_vact_end 2065 * @crtc: CRTC to enable line flag 2066 * @mstimeout: millisecond for timeout 2067 * 2068 * Wait for vact_end line flag irq or timeout. 2069 * 2070 * Returns: 2071 * Zero on success, negative errno on failure. 2072 */ 2073 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2074 { 2075 struct vop *vop = to_vop(crtc); 2076 unsigned long jiffies_left; 2077 int ret = 0; 2078 2079 if (!crtc || !vop->is_enabled) 2080 return -ENODEV; 2081 2082 mutex_lock(&vop->vop_lock); 2083 if (mstimeout <= 0) { 2084 ret = -EINVAL; 2085 goto out; 2086 } 2087 2088 if (vop_line_flag_irq_is_enabled(vop)) { 2089 ret = -EBUSY; 2090 goto out; 2091 } 2092 2093 reinit_completion(&vop->line_flag_completion); 2094 vop_line_flag_irq_enable(vop); 2095 2096 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2097 msecs_to_jiffies(mstimeout)); 2098 vop_line_flag_irq_disable(vop); 2099 2100 if (jiffies_left == 0) { 2101 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2102 ret = -ETIMEDOUT; 2103 goto out; 2104 } 2105 2106 out: 2107 mutex_unlock(&vop->vop_lock); 2108 return ret; 2109 } 2110 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2111 2112 static int vop_bind(struct device *dev, struct device *master, void *data) 2113 { 2114 struct platform_device *pdev = to_platform_device(dev); 2115 const struct vop_data *vop_data; 2116 struct drm_device *drm_dev = data; 2117 struct vop *vop; 2118 struct resource *res; 2119 int ret, irq; 2120 2121 vop_data = of_device_get_match_data(dev); 2122 if (!vop_data) 2123 return -ENODEV; 2124 2125 /* Allocate vop struct and its vop_win array */ 2126 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2127 GFP_KERNEL); 2128 if (!vop) 2129 return -ENOMEM; 2130 2131 vop->dev = dev; 2132 vop->data = vop_data; 2133 vop->drm_dev = drm_dev; 2134 dev_set_drvdata(dev, vop); 2135 2136 vop_win_init(vop); 2137 2138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2139 vop->regs = devm_ioremap_resource(dev, res); 2140 if (IS_ERR(vop->regs)) 2141 return PTR_ERR(vop->regs); 2142 vop->len = resource_size(res); 2143 2144 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2145 if (res) { 2146 if (!vop_data->lut_size) { 2147 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2148 return -EINVAL; 2149 } 2150 vop->lut_regs = devm_ioremap_resource(dev, res); 2151 if (IS_ERR(vop->lut_regs)) 2152 return PTR_ERR(vop->lut_regs); 2153 } 2154 2155 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2156 if (!vop->regsbak) 2157 return -ENOMEM; 2158 2159 irq = platform_get_irq(pdev, 0); 2160 if (irq < 0) { 2161 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2162 return irq; 2163 } 2164 vop->irq = (unsigned int)irq; 2165 2166 spin_lock_init(&vop->reg_lock); 2167 spin_lock_init(&vop->irq_lock); 2168 mutex_init(&vop->vop_lock); 2169 2170 ret = vop_create_crtc(vop); 2171 if (ret) 2172 return ret; 2173 2174 pm_runtime_enable(&pdev->dev); 2175 2176 ret = vop_initial(vop); 2177 if (ret < 0) { 2178 DRM_DEV_ERROR(&pdev->dev, 2179 "cannot initial vop dev - err %d\n", ret); 2180 goto err_disable_pm_runtime; 2181 } 2182 2183 ret = devm_request_irq(dev, vop->irq, vop_isr, 2184 IRQF_SHARED, dev_name(dev), vop); 2185 if (ret) 2186 goto err_disable_pm_runtime; 2187 2188 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2189 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 2190 if (IS_ERR(vop->rgb)) { 2191 ret = PTR_ERR(vop->rgb); 2192 goto err_disable_pm_runtime; 2193 } 2194 } 2195 2196 rockchip_drm_dma_init_device(drm_dev, dev); 2197 2198 return 0; 2199 2200 err_disable_pm_runtime: 2201 pm_runtime_disable(&pdev->dev); 2202 vop_destroy_crtc(vop); 2203 return ret; 2204 } 2205 2206 static void vop_unbind(struct device *dev, struct device *master, void *data) 2207 { 2208 struct vop *vop = dev_get_drvdata(dev); 2209 2210 if (vop->rgb) 2211 rockchip_rgb_fini(vop->rgb); 2212 2213 pm_runtime_disable(dev); 2214 vop_destroy_crtc(vop); 2215 2216 clk_unprepare(vop->aclk); 2217 clk_unprepare(vop->hclk); 2218 clk_unprepare(vop->dclk); 2219 } 2220 2221 const struct component_ops vop_component_ops = { 2222 .bind = vop_bind, 2223 .unbind = vop_unbind, 2224 }; 2225 EXPORT_SYMBOL_GPL(vop_component_ops); 2226