1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 */ 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/display/drm_hdmi_helper.h> 10 #include <drm/display/drm_hdmi_state_helper.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_probe_helper.h> 14 #include <drm/drm_simple_kms_helper.h> 15 16 #include <linux/clk.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 #include "rk3066_hdmi.h" 22 23 #include "rockchip_drm_drv.h" 24 25 #define DEFAULT_PLLA_RATE 30000000 26 27 struct hdmi_data_info { 28 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ 29 unsigned int enc_out_format; 30 unsigned int colorimetry; 31 }; 32 33 struct rk3066_hdmi_i2c { 34 struct i2c_adapter adap; 35 36 u8 ddc_addr; 37 u8 segment_addr; 38 u8 stat; 39 40 struct mutex i2c_lock; /* For i2c operation. */ 41 struct completion cmpltn; 42 }; 43 44 struct rk3066_hdmi { 45 struct device *dev; 46 struct drm_device *drm_dev; 47 struct regmap *grf_regmap; 48 int irq; 49 struct clk *hclk; 50 void __iomem *regs; 51 52 struct drm_bridge bridge; 53 struct drm_connector *connector; 54 struct rockchip_encoder encoder; 55 56 struct rk3066_hdmi_i2c *i2c; 57 58 unsigned int tmdsclk; 59 60 struct hdmi_data_info hdmi_data; 61 }; 62 63 static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) 64 { 65 return container_of(bridge, struct rk3066_hdmi, bridge); 66 } 67 68 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) 69 { 70 return readl_relaxed(hdmi->regs + offset); 71 } 72 73 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) 74 { 75 writel_relaxed(val, hdmi->regs + offset); 76 } 77 78 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, 79 u32 msk, u32 val) 80 { 81 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 82 83 temp |= val & msk; 84 hdmi_writeb(hdmi, offset, temp); 85 } 86 87 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) 88 { 89 int ddc_bus_freq; 90 91 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; 92 93 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 94 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 95 96 /* Clear the EDID interrupt flag and mute the interrupt. */ 97 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 98 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); 99 } 100 101 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) 102 { 103 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; 104 } 105 106 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) 107 { 108 u8 current_mode, next_mode; 109 u8 i = 0; 110 111 current_mode = rk3066_hdmi_get_power_mode(hdmi); 112 113 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); 114 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); 115 116 if (current_mode == mode) 117 return; 118 119 do { 120 if (current_mode > mode) { 121 next_mode = current_mode / 2; 122 } else { 123 if (current_mode < HDMI_SYS_POWER_MODE_A) 124 next_mode = HDMI_SYS_POWER_MODE_A; 125 else 126 next_mode = current_mode * 2; 127 } 128 129 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); 130 131 if (next_mode != HDMI_SYS_POWER_MODE_D) { 132 hdmi_modb(hdmi, HDMI_SYS_CTRL, 133 HDMI_SYS_POWER_MODE_MASK, next_mode); 134 } else { 135 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 136 HDMI_SYS_POWER_MODE_D | 137 HDMI_SYS_PLL_RESET_MASK); 138 usleep_range(90, 100); 139 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 140 HDMI_SYS_POWER_MODE_D | 141 HDMI_SYS_PLLB_RESET); 142 usleep_range(90, 100); 143 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 144 HDMI_SYS_POWER_MODE_D); 145 } 146 current_mode = next_mode; 147 i = i + 1; 148 } while ((next_mode != mode) && (i < 5)); 149 150 /* 151 * When the IP controller isn't configured with accurate video timing, 152 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, 153 * so we need to init the TMDS rate to the PCLK rate and reconfigure 154 * the DDC clock. 155 */ 156 if (mode < HDMI_SYS_POWER_MODE_D) 157 hdmi->tmdsclk = DEFAULT_PLLA_RATE; 158 } 159 160 static int rk3066_hdmi_bridge_clear_infoframe(struct drm_bridge *bridge, 161 enum hdmi_infoframe_type type) 162 { 163 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 164 165 if (type != HDMI_INFOFRAME_TYPE_AVI) { 166 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 167 return 0; 168 } 169 170 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, HDMI_INFOFRAME_AVI); 171 172 return 0; 173 } 174 175 static int 176 rk3066_hdmi_bridge_write_infoframe(struct drm_bridge *bridge, 177 enum hdmi_infoframe_type type, 178 const u8 *buffer, size_t len) 179 { 180 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 181 ssize_t i; 182 183 if (type != HDMI_INFOFRAME_TYPE_AVI) { 184 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 185 return 0; 186 } 187 188 rk3066_hdmi_bridge_clear_infoframe(bridge, type); 189 190 for (i = 0; i < len; i++) 191 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, buffer[i]); 192 193 return 0; 194 } 195 196 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, 197 struct drm_display_mode *mode) 198 { 199 int value, vsync_offset; 200 201 /* Set the details for the external polarity and interlace mode. */ 202 value = HDMI_EXT_VIDEO_SET_EN; 203 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 204 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; 205 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 206 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; 207 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 208 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; 209 210 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) 211 vsync_offset = 6; 212 else 213 vsync_offset = 0; 214 215 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; 216 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); 217 218 /* Set the details for the external video timing. */ 219 value = mode->htotal; 220 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); 221 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); 222 223 value = mode->htotal - mode->hdisplay; 224 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); 225 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); 226 227 value = mode->htotal - mode->hsync_start; 228 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); 229 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); 230 231 value = mode->hsync_end - mode->hsync_start; 232 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); 233 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); 234 235 value = mode->vtotal; 236 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); 237 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); 238 239 value = mode->vtotal - mode->vdisplay; 240 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); 241 242 value = mode->vtotal - mode->vsync_start + vsync_offset; 243 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); 244 245 value = mode->vsync_end - mode->vsync_start; 246 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); 247 248 return 0; 249 } 250 251 static void 252 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) 253 { 254 hdmi_writeb(hdmi, offset, value); 255 hdmi_modb(hdmi, HDMI_SYS_CTRL, 256 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); 257 usleep_range(90, 100); 258 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); 259 usleep_range(900, 1000); 260 } 261 262 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) 263 { 264 /* TMDS uses the same frequency as dclk. */ 265 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); 266 267 /* 268 * The semi-public documentation does not describe the hdmi registers 269 * used by the function rk3066_hdmi_phy_write(), so we keep using 270 * these magic values for now. 271 */ 272 if (hdmi->tmdsclk > 100000000) { 273 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); 274 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 275 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 276 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 277 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); 278 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); 279 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 280 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); 281 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 282 } else if (hdmi->tmdsclk > 50000000) { 283 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); 284 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 285 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 286 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 287 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); 288 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); 289 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 290 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 291 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 292 } else { 293 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); 294 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 295 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 296 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 297 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); 298 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); 299 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 300 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 301 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 302 } 303 } 304 305 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, 306 struct drm_atomic_state *state) 307 { 308 struct drm_bridge *bridge = &hdmi->bridge; 309 struct drm_connector *connector; 310 struct drm_display_info *display; 311 struct drm_display_mode *mode; 312 struct drm_connector_state *new_conn_state; 313 struct drm_crtc_state *new_crtc_state; 314 315 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 316 317 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 318 if (WARN_ON(!new_conn_state)) 319 return -EINVAL; 320 321 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 322 if (WARN_ON(!new_crtc_state)) 323 return -EINVAL; 324 325 display = &connector->display_info; 326 mode = &new_crtc_state->adjusted_mode; 327 328 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 329 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 330 331 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || 332 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || 333 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || 334 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) 335 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 336 else 337 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 338 339 hdmi->tmdsclk = mode->clock * 1000; 340 341 /* Mute video and audio output. */ 342 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, 343 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); 344 345 /* Set power state to mode B. */ 346 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) 347 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 348 349 /* Input video mode is RGB 24 bit. Use external data enable signal. */ 350 hdmi_modb(hdmi, HDMI_AV_CTRL1, 351 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); 352 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, 353 HDMI_VIDEO_OUTPUT_RGB444 | 354 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | 355 HDMI_VIDEO_INPUT_COLOR_RGB); 356 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); 357 358 rk3066_hdmi_config_video_timing(hdmi, mode); 359 360 if (display->is_hdmi) { 361 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 362 HDMI_VIDEO_MODE_HDMI); 363 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 364 } else { 365 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); 366 } 367 368 rk3066_hdmi_config_phy(hdmi); 369 370 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); 371 372 /* 373 * When the IP controller is configured with accurate video 374 * timing, the TMDS clock source should be switched to 375 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode 376 * clock rate and reconfigure the DDC clock. 377 */ 378 rk3066_hdmi_i2c_init(hdmi); 379 380 /* Unmute video output. */ 381 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 382 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); 383 return 0; 384 } 385 386 static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 387 struct drm_atomic_state *state) 388 { 389 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 390 struct drm_connector_state *conn_state; 391 struct drm_crtc_state *crtc_state; 392 int mux, val; 393 394 conn_state = drm_atomic_get_new_connector_state(state, hdmi->connector); 395 if (WARN_ON(!conn_state)) 396 return; 397 398 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 399 if (WARN_ON(!crtc_state)) 400 return; 401 402 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, &hdmi->encoder.encoder); 403 if (mux) 404 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; 405 else 406 val = HDMI_VIDEO_SEL << 16; 407 408 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); 409 410 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", 411 (mux) ? "1" : "0"); 412 413 rk3066_hdmi_setup(hdmi, state); 414 } 415 416 static void rk3066_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 417 struct drm_atomic_state *state) 418 { 419 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 420 421 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); 422 423 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { 424 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, 425 HDMI_VIDEO_AUDIO_DISABLE_MASK); 426 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 427 HDMI_AUDIO_CP_LOGIC_RESET_MASK, 428 HDMI_AUDIO_CP_LOGIC_RESET); 429 usleep_range(500, 510); 430 } 431 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 432 } 433 434 static int 435 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 436 struct drm_crtc_state *crtc_state, 437 struct drm_connector_state *conn_state) 438 { 439 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 440 441 s->output_mode = ROCKCHIP_OUT_MODE_P888; 442 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 443 444 return 0; 445 } 446 447 static const 448 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { 449 .atomic_check = rk3066_hdmi_encoder_atomic_check, 450 }; 451 452 static enum drm_connector_status 453 rk3066_hdmi_bridge_detect(struct drm_bridge *bridge) 454 { 455 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 456 457 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? 458 connector_status_connected : connector_status_disconnected; 459 } 460 461 static const struct drm_edid * 462 rk3066_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) 463 { 464 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 465 const struct drm_edid *drm_edid; 466 467 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 468 if (!drm_edid) 469 dev_dbg(hdmi->dev, "failed to get edid\n"); 470 471 return drm_edid; 472 } 473 474 static enum drm_mode_status 475 rk3066_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 476 const struct drm_display_info *info, 477 const struct drm_display_mode *mode) 478 { 479 u32 vic = drm_match_cea_mode(mode); 480 481 if (vic > 1) 482 return MODE_OK; 483 else 484 return MODE_BAD; 485 } 486 487 static const struct drm_bridge_funcs rk3066_hdmi_bridge_funcs = { 488 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 489 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 490 .atomic_reset = drm_atomic_helper_bridge_reset, 491 .atomic_enable = rk3066_hdmi_bridge_atomic_enable, 492 .atomic_disable = rk3066_hdmi_bridge_atomic_disable, 493 .detect = rk3066_hdmi_bridge_detect, 494 .edid_read = rk3066_hdmi_bridge_edid_read, 495 .hdmi_clear_infoframe = rk3066_hdmi_bridge_clear_infoframe, 496 .hdmi_write_infoframe = rk3066_hdmi_bridge_write_infoframe, 497 .mode_valid = rk3066_hdmi_bridge_mode_valid, 498 }; 499 500 501 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) 502 { 503 struct rk3066_hdmi *hdmi = dev_id; 504 irqreturn_t ret = IRQ_NONE; 505 u8 interrupt; 506 507 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) 508 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); 509 510 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); 511 if (interrupt) 512 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); 513 514 if (interrupt & HDMI_INTR_EDID_MASK) { 515 hdmi->i2c->stat = interrupt; 516 complete(&hdmi->i2c->cmpltn); 517 } 518 519 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) 520 ret = IRQ_WAKE_THREAD; 521 522 return ret; 523 } 524 525 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) 526 { 527 struct rk3066_hdmi *hdmi = dev_id; 528 529 drm_helper_hpd_irq_event(hdmi->connector->dev); 530 531 return IRQ_HANDLED; 532 } 533 534 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 535 { 536 int length = msgs->len; 537 u8 *buf = msgs->buf; 538 int ret; 539 540 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); 541 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) 542 return -EAGAIN; 543 544 while (length--) 545 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); 546 547 return 0; 548 } 549 550 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 551 { 552 /* 553 * The DDC module only supports read EDID message, so 554 * we assume that each word write to this i2c adapter 555 * should be the offset of the EDID word address. 556 */ 557 if (msgs->len != 1 || 558 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 559 return -EINVAL; 560 561 reinit_completion(&hdmi->i2c->cmpltn); 562 563 if (msgs->addr == DDC_SEGMENT_ADDR) 564 hdmi->i2c->segment_addr = msgs->buf[0]; 565 if (msgs->addr == DDC_ADDR) 566 hdmi->i2c->ddc_addr = msgs->buf[0]; 567 568 /* Set edid fifo first address. */ 569 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); 570 571 /* Set edid word address 0x00/0x80. */ 572 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 573 574 /* Set edid segment pointer. */ 575 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 576 577 return 0; 578 } 579 580 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, 581 struct i2c_msg *msgs, int num) 582 { 583 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); 584 struct rk3066_hdmi_i2c *i2c = hdmi->i2c; 585 int i, ret = 0; 586 587 mutex_lock(&i2c->i2c_lock); 588 589 rk3066_hdmi_i2c_init(hdmi); 590 591 /* Unmute HDMI EDID interrupt. */ 592 hdmi_modb(hdmi, HDMI_INTR_MASK1, 593 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); 594 i2c->stat = 0; 595 596 for (i = 0; i < num; i++) { 597 DRM_DEV_DEBUG(hdmi->dev, 598 "xfer: num: %d/%d, len: %d, flags: %#x\n", 599 i + 1, num, msgs[i].len, msgs[i].flags); 600 601 if (msgs[i].flags & I2C_M_RD) 602 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); 603 else 604 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); 605 606 if (ret < 0) 607 break; 608 } 609 610 if (!ret) 611 ret = num; 612 613 /* Mute HDMI EDID interrupt. */ 614 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 615 616 mutex_unlock(&i2c->i2c_lock); 617 618 return ret; 619 } 620 621 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) 622 { 623 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 624 } 625 626 static const struct i2c_algorithm rk3066_hdmi_algorithm = { 627 .master_xfer = rk3066_hdmi_i2c_xfer, 628 .functionality = rk3066_hdmi_i2c_func, 629 }; 630 631 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) 632 { 633 struct i2c_adapter *adap; 634 struct rk3066_hdmi_i2c *i2c; 635 int ret; 636 637 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 638 if (!i2c) 639 return ERR_PTR(-ENOMEM); 640 641 mutex_init(&i2c->i2c_lock); 642 init_completion(&i2c->cmpltn); 643 644 adap = &i2c->adap; 645 adap->owner = THIS_MODULE; 646 adap->dev.parent = hdmi->dev; 647 adap->dev.of_node = hdmi->dev->of_node; 648 adap->algo = &rk3066_hdmi_algorithm; 649 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); 650 i2c_set_adapdata(adap, hdmi); 651 652 ret = devm_i2c_add_adapter(hdmi->dev, adap); 653 if (ret) { 654 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", 655 adap->name); 656 devm_kfree(hdmi->dev, i2c); 657 return ERR_PTR(ret); 658 } 659 660 hdmi->i2c = i2c; 661 662 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 663 664 return adap; 665 } 666 667 static int 668 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) 669 { 670 struct drm_encoder *encoder = &hdmi->encoder.encoder; 671 struct device *dev = hdmi->dev; 672 int ret; 673 674 encoder->possible_crtcs = 675 drm_of_find_possible_crtcs(drm, dev->of_node); 676 677 /* 678 * If we failed to find the CRTC(s) which this encoder is 679 * supposed to be connected to, it's because the CRTC has 680 * not been registered yet. Defer probing, and hope that 681 * the required CRTC is added later. 682 */ 683 if (encoder->possible_crtcs == 0) 684 return -EPROBE_DEFER; 685 686 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); 687 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 688 689 hdmi->bridge.driver_private = hdmi; 690 hdmi->bridge.funcs = &rk3066_hdmi_bridge_funcs; 691 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 692 DRM_BRIDGE_OP_EDID | 693 DRM_BRIDGE_OP_HDMI | 694 DRM_BRIDGE_OP_HPD; 695 hdmi->bridge.of_node = hdmi->dev->of_node; 696 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 697 hdmi->bridge.vendor = "Rockchip"; 698 hdmi->bridge.product = "RK3066 HDMI"; 699 700 hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi); 701 if (IS_ERR(hdmi->bridge.ddc)) 702 return PTR_ERR(hdmi->bridge.ddc); 703 704 if (IS_ERR(hdmi->bridge.ddc)) 705 return PTR_ERR(hdmi->bridge.ddc); 706 707 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 708 if (ret) 709 return ret; 710 711 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 712 if (ret) 713 return ret; 714 715 hdmi->connector = drm_bridge_connector_init(drm, encoder); 716 if (IS_ERR(hdmi->connector)) { 717 ret = PTR_ERR(hdmi->connector); 718 dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret); 719 return ret; 720 } 721 722 drm_connector_attach_encoder(hdmi->connector, encoder); 723 724 return 0; 725 } 726 727 static int rk3066_hdmi_bind(struct device *dev, struct device *master, 728 void *data) 729 { 730 struct platform_device *pdev = to_platform_device(dev); 731 struct drm_device *drm = data; 732 struct rk3066_hdmi *hdmi; 733 int irq; 734 int ret; 735 736 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 737 if (!hdmi) 738 return -ENOMEM; 739 740 hdmi->dev = dev; 741 hdmi->drm_dev = drm; 742 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 743 if (IS_ERR(hdmi->regs)) 744 return PTR_ERR(hdmi->regs); 745 746 irq = platform_get_irq(pdev, 0); 747 if (irq < 0) 748 return irq; 749 750 hdmi->hclk = devm_clk_get(dev, "hclk"); 751 if (IS_ERR(hdmi->hclk)) { 752 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); 753 return PTR_ERR(hdmi->hclk); 754 } 755 756 ret = clk_prepare_enable(hdmi->hclk); 757 if (ret) { 758 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); 759 return ret; 760 } 761 762 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 763 "rockchip,grf"); 764 if (IS_ERR(hdmi->grf_regmap)) { 765 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); 766 ret = PTR_ERR(hdmi->grf_regmap); 767 goto err_disable_hclk; 768 } 769 770 /* internal hclk = hdmi_hclk / 25 */ 771 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); 772 773 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 774 usleep_range(999, 1000); 775 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); 776 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); 777 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); 778 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); 779 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 780 781 ret = rk3066_hdmi_register(drm, hdmi); 782 if (ret) 783 goto err_disable_hclk; 784 785 dev_set_drvdata(dev, hdmi); 786 787 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, 788 rk3066_hdmi_irq, IRQF_SHARED, 789 dev_name(dev), hdmi); 790 if (ret) { 791 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); 792 goto err_cleanup_hdmi; 793 } 794 795 return 0; 796 797 err_cleanup_hdmi: 798 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 799 err_disable_hclk: 800 clk_disable_unprepare(hdmi->hclk); 801 802 return ret; 803 } 804 805 static void rk3066_hdmi_unbind(struct device *dev, struct device *master, 806 void *data) 807 { 808 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); 809 810 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 811 812 clk_disable_unprepare(hdmi->hclk); 813 } 814 815 static const struct component_ops rk3066_hdmi_ops = { 816 .bind = rk3066_hdmi_bind, 817 .unbind = rk3066_hdmi_unbind, 818 }; 819 820 static int rk3066_hdmi_probe(struct platform_device *pdev) 821 { 822 return component_add(&pdev->dev, &rk3066_hdmi_ops); 823 } 824 825 static void rk3066_hdmi_remove(struct platform_device *pdev) 826 { 827 component_del(&pdev->dev, &rk3066_hdmi_ops); 828 } 829 830 static const struct of_device_id rk3066_hdmi_dt_ids[] = { 831 { .compatible = "rockchip,rk3066-hdmi" }, 832 { /* sentinel */ }, 833 }; 834 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); 835 836 struct platform_driver rk3066_hdmi_driver = { 837 .probe = rk3066_hdmi_probe, 838 .remove = rk3066_hdmi_remove, 839 .driver = { 840 .name = "rockchip-rk3066-hdmi", 841 .of_match_table = rk3066_hdmi_dt_ids, 842 }, 843 }; 844